SU1711325A1 - Shaper of pulses - Google Patents

Abstract

The invention relates to a pulse technique and can be used in software-time devices designed to form synchronous pulse sequences in spatially separated devices having a single time system. The purpose of the invention — an increase in synchronization accuracy by matching the significant moments of the generated pulses to the current time — is achieved by introducing a generator of 13 codes gated by an element. 1t 14 comparison of codes, bus 8 timestamp pulse labels, bus 9 start-up time code, bus 10 signal of start-up time code recording, period code bus 11, bus 12 current time code. The device also contains a generator of 1 pulses, a counter of 2 pulses, an RS flip-flop 3, an element OR 4, an initial installation bus 5, a bus b of the pulse-duration code, an output bus 7. 3 s, p. f-ly, 4 ill. And so you ate

Description

FIG. f

The invention relates to a pulse technique and may be used in software-time devices designed to form synchronous pulse sequences in spatially separated devices having a single time system.

The purpose of the invention is to improve the synchronization accuracy by matching the significant moments of the generated pulses to the current time.

Figure 1 shows the functional diagram of the pulse former; FIGS. 2 and 3 show embodiments of the coder; on fmg.4 - schematic diagram of the synchronous shaper single pulse.

The pulse shaper (figure 1) contains a generator of 1 pulses, a counter of 2 pulses, RS-flip-flop 3, element OR 4, bus 5 initial installation, bus b code pulse duration, output bus 7, bus 8 pulse tags of the time scale, bus 9 code start-up time, start-up time code recording signal bus 10, period code bus 11, current time code bus 12, code generator 13, and gated code comparison element 1.4.

The code generator 13 (FIG. 2) contains the first 15 and second 16 pulse counters, the AND 17 element and the memory element 18, or (FIG. 3) the IL 19 element, the single-pulse synchronous driver 20, the selector-multiplexer 21, the adder 22 codes and memory element 23.

A synchronous shaper 20 of a single pulse contains three triggers 24-26, each of which is D-type.

The first output of the pulse generator 1 is connected to the counting input of the pulse counter 2, the A input of the gated code comparison element 14 is connected to the current time code bus 12, the B input of the gated code comparison element 14 is connected to the output of the code generator 13, Gated code comparison element 14 connected to the bus 8 pulse tags of the time scale and to the first input of the code generator 13, the second input of the code generator 13 is connected to the output of the gated code comparison element 14 and. with the S-input of the RS flip-flop Z, the direct output of the RS-flip-flop Z is connected to the output bus 7 and to the write input of the counter 2 pulses, the R-input of the RS flip-flop Z is connected to the output of the OR 4 element, the first input of the OR 4 element is connected to bus 5 initial installation, the second input element OR 4 is connected to the output of the earth of the pulse counter 2, the information input of the pulse counter 2 is connected to the bus 6 of the pulse duration code, the second output of the pulse generator 1 is connected to the third input of the code generator 13, the fourth input of the code generator 13 is connected with bus 11 ne code iodine, fifth input of the bus 13 kodovsoedinen Yusignala initial recording start time code, the sixth

0 the input of the imaging unit 13 codes connected to the bus 9 code start time.

The output of the memory element 18 is connected to the output of the code generator 13 codes, the synchronization input of the memory element 18 is connected to

5, the first input of the imaging unit 13 codes, the information input of the memory element 18 is connected to the output of the first counter of 15 pulses, the counting input of the first counter of 15 pulses is connected to the counting input

0 of the second counter 16 pulses and with the output of the element And 17, the first input element And 17 is connected to the third input of the imaging unit 13 codes, the second input of the element And 17 is connected to the output of the loan of the second counter 16

5 pulses, the information input of the second pulse counter 16 of the pulses is connected to the fourth input of the imaging unit 13 of the codes, the recording input of the second counter of the pulses 16 is connected to the second input of the imaging unit 13

0 codes, the fifth input of the imaging unit 13 of the codes is connected to the recording input of the first pulse counter 15, the information input of the first pulse counter 15 is connected to the sixth input of the imaging unit 13 codes.

5 The output of the memory element 23 is connected to the output of the code generator 13 and to the A-input of the code adder 22, the input of the code adder 22 is connected to the fourth input of the code generator 13, the output of the code generator

0 13 codes are connected to the first information input of the selector-multiplexer 21, the second information input of the selector-multiplexer 21 is connected to the sixth input of the driver - 13 codes, the output

5 of the selector-multiplexer 21 is connected to the information input of the memory element 23, the synchronization time of the memory element 23 is connected to the output of the OR element 19, the first input of the OR element 19 is connected to

0 by the second input of the imaging unit 13 codes, the second input of the OR element 19 is connected to the output of the synchronous imaging unit 20 of a single pulse, the first input of the synchronous imaging unit 20 of a single pulse 5 is connected to the first input of the imaging unit 13 of the single pulse connected to the input of the selector control- multiplexer 21 and with the fifth input shaper 13 codes, the third input

synchronous shaper 20 single pulse connected to the third input shaper 1-3 codes.

The C input of the first trigger 24 is connected to the first input of the synchronous driver 20 of a single pulse, the second input of the synchronous driver 20 of a single pulse is connected to the C input of the second trigger 25, the D input of the second trigger 25 is connected to the logical zero bus, the S input of the second the trigger 25 is connected to the S-VHBD of the first trigger 24 and with the direct output of the third trigger 26, the inverse output of the third trigger 26 is connected to the output of the synchronous driver 20 of a single pulse, the third input of the synchronous driver 20 of a single pulse is connected to C by the input of the third trigger 26, the D input of the third trigger 26 is connected to the direct output of the first trigger, the D input of the first trigger 24 is connected to the direct output of the second trigger 25.

The process of forming a pulse (pulses) consists of successive stages in time: loading the time of grabbing the leading edge of the first pulse to the current time of day into the driver 13 codes, loading the code of the pulse duration into the counter 2 pulses, waiting for the moment of coincidence of the current time code days of a centralized time scale with a given start time code, the formation of a pulse of equality of codes, the formation of a leading edge of a pulse along the leading edge of a pulse of equality of codes, and simultaneously Calculating the absolute increment code of the formation of the next pulse relative to the start time, calculating the next code for binding the time of the leading edge of the next pulse to the current time of day, followed by replacing the old code 13 with the calculated code at the output of the generator, as well as converting the pulse code value in the counter 2 pulses per interval defining the pulse duration. At the end of the transformation, the leading edge of the pulse is formed .;

The pulse generator 1 is designed for the continuous formation of two pulse sequences, the first (first output) sequence of the sample time interval, the second (second output) the auxiliary pulse sequence with a higher pulse frequency than the first. The ratio between the pulse frequency is A, where A is an integer greater than two (A 2, 3, 4 ...).

Pulse counter 2 is designed to convert the code into a time interval by counting the pulses of the reference time interval. It works in subtraction mode from the entered code value to zero. The counting time determines the duration of the generated pulse.

RS flip-flop 3 is designed to form an output pulse.

The code generator 13 is designed to calculate the code of the time reference for the formation of the leading edge of the pulse being formed, the first code value at the output of the code generator 13 is equal to the code value loaded on the start-up time code bus 9, the subsequent code values at the output of the code generator 13 codes are defined as the sum of the current value of the output code and the value of the period code loaded via the bus 11 of the period code. In the operation of addition, the codes of the terms are summed up either without any transformations, when the code arrives via the bus 12 of the current time code in the binary number system, or with the transformation according to the law of summation of the time of day when the code arrives through the bus 12 code of the current time in binary-decimal number system.

The method of summing the time codes in the code generator 13 is determined by the form in which the current time code is represented on the bus 12 of the current time code.

The gated code comparison element 14 is intended to form the output pulse when the reference code value of the centralized scale of the current time of day is equal, i.e. The output pulse is phased with a system time scale.

When the codes on the A- and B-inputs of the gated code comparison element 14 are matched, a pulse of the impulse label of the time scale passes from the C input to the output of the gated code comparison element 14, goes to the S input of the RS flip-flop 3, which is set to one This, thereby forming the leading edge of the output pulse on the output bus 7, as well as this pulse, enters the second runner of the code generator 13, in which the arrival of the pulse records the period code from the bus 11 and then adds the recorded K-bit the period code with the N-bit start time code, which is set at the output of the driver 13 codes. If NK, then the K-bit code is supplemented to an M-bit by higher bits with zero value. The result of the summation replaces the old value of the start time code at the output of the former 13 codes.

Before the pulse shaper starts operation, the RS-trigger 3 is set up according to the signal received via the bus 5 of the initial setup. On the bus 6 of the pulse width code, an Mr- discharge code () is applied, which is recorded in the counter 2 pulses in the absence of a pulse at the output of the pulse former.

On the bus 9 of the start-up time code, the N-bit code of the time of the formation of the leading edge of the first pulse is applied to the current time of day, then a write pulse is written to the bus 10 of the recording signal of the start-up time code; in the shaper 13 codes. The recorded code is set at the output of the code generator 13 codes and is fed to the B input of the gated code comparison element 14.

On the current time code bus 12, the A-input of the gated code comparison element 14 is supplied at the current time of day of the centralized time scale, which is digitized by a pulse mark of the time scale fed through the bus 8 of the time-scale pulse tags to the C input of the gated code comparison element 14.

The level of the logical unit on the output bus 7 is fed to the input of the record of the counter 2 pulses and translates it into the counting mode. The entered code value of the duration of the generated pulse is reduced; the sample time intervals are reduced to zero; a pulse appears at the output of the pulse counter 2, which through the OR 4 element enters the R input of the RS flip-flop Z. RS-tpnrrep 3 goes to the zero state , thereby forming the leading edge of the pulse and allowing the recording of the code of the pulse duration in the counter 2 pulses.

The shaper 13 codes works as follows (Fig, 2),

The initial start time code from bus 9 of the initial start time code is recorded in the first pulse counter 15 by the arrival of the write pulse on the bus 10 of the initial start time code write signal and by the termination of each pulse of the time scale mark (i.e. on the falling edge) from bus 8 the impulse labels of the time scale are periodically rewritten into the memory element 18 and fed to the output of the imaging unit 13

codes. In the initial state, the second counter of 16 pulses is reset to zero, since by turning on the power it reduces its content to zero, the output of the loan of the second counter of 16 pulses is low potential, which prohibits the passage of the auxiliary clock frequency through AND 17 and the counting inputs of the first and second counters 15 and 16

0 pulses. When a code equality pulse arrives at the second input of the imaging unit 13 codes, the period code is written from the period code bus 11 to the second counter 16 pulses, while

5 has a value other than zero. At the output of the loan of the second counter of 16 pulses, the level of the logical unit is established and the auxiliary clock frequency is fed to the counting inputs of the first and second counters 15 and 16 pulses. When the code reaches the zero value at the output of the loan of the second counter of 16 pulses, the logic zero level is established and the arrival of clock pulses at the counting inputs

5 counters are terminated. The number of clock pulses arriving at the counting input of the first pulse counter 15 is determined by the code value recorded in the second pulse counter 16. Thus, the code was copied from the second counter of 16 pulses to the first counter of 15 pulses. Since the first counter of 15 pulses is summing, the rewritable

5 codes from the second counter 16 pulses to the current code of the first counter 15 pulses. If the period code has a zero value, then at the output of the loan of the second counter of 16 pulses the level is logical zero

0 does not change, the auxiliary clock frequency does not arrive at the counting inputs of the first and second counters 15 and 16, and the code of the first counter 15 of pulses does not change its value,

5 The presence of the auxiliary clock frequency, i.e. sequences of pulses with a higher pulse frequency than the frequency of pulse marks, makes it possible to avoid false coincidence of codes in the built-in code comparison element 14 when the code of the first pulse counter 15 is incremented. Thus, between two adjacent impulse labels of the time scale (one discretion), the code is increased in the first counter of 15 pulses by 2.3, ... discretes of time and the value of the time code at the output of the code generator 13 after the match becomes greater than the value of the current time code of the scale of time.

The memory element 18 is intended to eliminate the occurrence of a logic code for the start time, which can occur at the output of the summing first counter 15 pulses at the moments of its switching during counting.

The initial start time code from bus 9 of the initial start time code (Fig. 3) through the selector-multiplexer 21 is recorded in memory element 23 on the front of a pulse from the output of a single pulse synchronous driver 20, which is formed when the first write pulse is received sequentially at the inputs of this driver. from the bus 10 of the signal recording the time code of the initial start-up, the falling edge of the pulse of the time scale mark from the bus / 8 pulse marks of the time scale and the leading edge of the pulse of the auxiliary frequency. Thus, the initial start code is recorded during the absence of a time stamp pulse label, the recorded code goes to the output of the generator of 13 codes, as well as to the A input of the code adder 22, which is summed with the period code from the period code bus 11.

The result from the output of the adder 22 of the codes is fed through the selector-multiplexer 21 to the information input of the memory element 23. PDI: when a pulse of equality of codes arrives at the second input of the imaging unit of 13 codes, the result of the code is recorded on the trailing edge of the code summation result from the bus 11 of the period code, i.e. there is a replacement of the old value of the start time code with a new one in the absence of the impulse label of the time scale.

The work of the pulse shaper.

Initial state.

The initial installation bus 5 receives a pulse of the level of a logical unit. This pulse through the element OR 4 is fed to the R input of the RS flip-flop 3 and sets it to the zero state. The level of logical zero from the output of the RS flip-flop 3 is fed to the input of the record of the counter 2 pulses.

The pulse shaper can operate in four modes: the formation of single pulses, the formation of a sequence of pulses of constant frequency and constant duration, the formation of a sequence of pulses in the stationary frequency of variable duration and the formation of pulses of variable duration (for example, a pseudo-random sequence).

The pulse shaper can work with the N-bit potential binary (binary-decimal) code of the current

time of day, presented in parallel form.

The first mode.

On the bus 6 of the pulse width code 5, the code of the pulse duration is set, on the bus 9 of the start-up time code - the start-up time code, on the bus 11 of the period code - the zero value of the period code. Then, a start-up time code 0 is written to the driver.

13 inputs by applying to the bus 10 a write signal of the time code of the initial start of the write pulse.

With the equality of the compared codes 5 time at the output of the gated element

Comparing codes for a pulse, corresponding to the beginning of the pulse formation time, the pulse duration is equal to the duration of the pulse marks of the time scale on the bus 8 of the pulse marks of the time scale. The initial start pulse of the logic unit level from the output of the gated code comparison element 14 is fed to the S input of the RS flip-flop 3 and translates it into

5 single state.

The signal level of the logical unit from the output of the RS flip-flop 3 is fed to the input of the record of the counter of 2 pulses, enabling the counting. Pulse counter 2 operates in read mode and determines the duration of the pulse being formed. After the termination of the counting at the output of the loan of the counter 2 pulses, the pulse of the level of the logical unit, which through the OR 4 element goes to

5 The R input of the RS flip-flop is 3 and puts it in the zero state. Pulse counter 2 goes to the information input information recording state. Impulse formation is complete. In this case, the shaper of 13 codes changed the old value of the start time code to a new one, which is equal to the old value, since the period code is zero, and, therefore, the sum of the codes is unchanged. Current time

5, the time scale has a larger value than the start time code value, and no next pulse is generated. In order to form the next single pulse, it is necessary to form 13 codes to write the code of the new start time, and on the bus 6 of the code for the pulse duration, set the new code value for the duration of the formed pulse. Thus formed

5 single pulses correspond to the current time. The second mode.

The mode of formation of a sequence of pulses of constant duration

and a constant frequency analog to the mode of formation of single pulses.

On the bus b of the pulse width code, a code of the duration of the pulses is set. On the period code bus 11, a code for the period of the generated pulses is established.

The formation of the first initial start pulse occurs in the same way as the first mode. The generated initial start pulse from the output of the gated code comparison element 14 is fed to the second input of the code generator 13. According to this pulse, the shaper 13 codes summarizes the start time and period codes, then shifts the output of the old time code value to a new one, and then the process repeats.

To change the period, duration or time of the initial start-up, it is necessary to change the codes on the corresponding tires.

The third mode.

The formation of a sequence of pulses of a constant frequency of variable duration occurs similarly to the formation of pulses of a constant duration. The difference is that after the formation of the initial start-up pulse and the switching of the RS-flip-flop 3 into a single state on the bus 6 of the pulse duration code, a new value of the duration code is established. When using a computer as a device for controlling a pulse driver and storing start-up time codes, a period code and a duration code, the logic-zero-level signal on the output bus 7 can be used as an interrupt demand signal. When the demand signal appears, the computer changes the duration code on bus 6 of the pulse width code.

Fourth mode.

The formation of pulses of variable frequency of variable duration is similar to the formation of pulses of constant frequency of variable duration. The difference is that according to the interrupt request signal, the duration code on the bus 6 of the pulse duration code is changed and the period code on the bus 11 of the period code is changed.

Thus, the invention provides the formation of pulses corresponding to the current time.

The synchronous shaper 20 of a single pulse is designed to form a single pulse of the level of a logical unit during the absence

impulse label time scale. After successive arrival of the leading edge of the signal for recording the start-up time code (bus 10) and the trailing edge

a pulse arriving from the bus 8 pulse marks of the time scale, a pulse is generated at the output of the synchronous driver 20 of a single pulse. The pulses at the inputs of CT1 and C of the synchronous shaper 20 of a single pulse arrive continuously (respectively, from d | ay 8 pulse marks of the time scale and from the first output of the generator of 1 pulses). In the absence of a pulse at the input

5 CT2, at the output of a single pulse synchronous driver 20, a logical zero level is set.

Synchronous shaper 20 single pulse at the time of power on

0 works as follows.

Suppose that any one of the power triggers is set to zero. The logic zero level through the fronts of the pulses arriving at the C inputs is transmitted to the direct output of the third trigger 26, and then transmitted to the S inputs of the first and second trigger 24 and 25 and sets them to the state of the logical one at the output. First incoming impulse to C input

0 of the third trigger 26 will transfer it to the state of a logical unit at the direct output and the state of the logical zero at the inverse output. Thus, at the output of the synchronous driver 20 of a single impulse, a level of logic zero is set.

The incoming edge of the start-up time code recording signal, which enters the CT2 input, will translate the second trigger 25 of the synchronous single-pulse driver 20 of the single pulse to the zero state. The first trailing edge of the timestamp pulse, which is input to the CT1 input, will translate the first trigger 24 to the zero state, the forward

5, the front of the first pulse following the above from the first output of the generator 1 of pulses to the input C will transfer the third trigger 26 to the zero state at the forward output (the single state on the inverse

0 exit). The logic zero level arrives at the S-inputs of the first and second triggers 24 and 25 and sets them to a single state. The next pulse arriving at the C input of the third trigger 26 will translate it into a single state at the direct output (zero state at the inverse output). Thus, the formation of a single pulse of the level of a logical unit, the duration of which is equal to the period of the pulses coming from the first output of the pulse generator 1, is produced.

On the period code bus 11, a period code of the generated pulses is set (input 4 of the code generator 13, FIG. 3). On the start-up time code bus 9 (input 6), the start-up time code is set. On bus 10 of the signal of the start-up time code recording, the logical zero level is set. The selector multiplexer 21 passes through the first information input. According to the logic unit level signal, the selector-multiplexer 21 passes the start-up time code via the second information input to the information input of the memory element 23. On the leading edge of this pulse, the synchronous shaper 20 of a single pulse generates a single pulse, on the falling front of which a start-up code is written to the element 23 of the unit. This code is transmitted to the output of the imaging unit 13 codes and to the A input of the adder 22 codes. At the output of the adder 22 codes, a time code is formed, equal to the sum of the start-up time and period codes. This code is fed to the first information input of the selector-multiplexer 21, from the output of which it is fed to the information input of the memory element 23. This code will be recorded in the memory element 23 by the falling edge of the pulse generated by the comparing element 14 of the code comparison (FIG. 1). Thus, at the output of the imaging unit 13 codes, the time code of the next start was formed.

Claims (4)

Claims 1. A pulse shaper comprising a pulse generator, the first output of which is connected to the counter input of a pulse counter, an RS flip-flop, an OR element, an initial setup bus, a pulse code code bus, an output bus, and in order to improve the synchronization accuracy by linking the significant moments of the generated pulses to the current time, the pulse time-stamp tire, the start-up time code bus, the start-up time code recording signal bus, the code a period, a current time code bus, a code generator, a gated code comparison element, the A input of which is connected to the current time code bus, a B input input with a code generator output, a C input input with a bus of pulse time scale tags and the first input of the code generator, the second input of which is connected to the output of the gated code comparison element and to the S input RS flip-flop, the direct output of which is connected to the output bus and the write input of the pulse counter, the R input to the output of the OR element, the first input of which is connected to the initial setting bus, the second input to the output of the pulse counter loan, the information input of which is connected to the pulse code code bus, the second output of the pulse generator is connected to the third input of the code generator, the fourth input of which is connected to the period code bus, the fifth input - to the start-up time code recording signal bus, the sixth input - to the bus yes start-up time. 2. The former according to claim 1, wherein the driver of the codes contains the first and second pulse counters, the element I and the memory element whose output is connected to the output of the driver of the codes, the synchronization input is the first input of the code generator, the information input with the output of the first pulse counter, the counting input of which is connected to the counting input of the second pulse counter and the output of the I element, the first input of which is connected to the third input of the code generator, the second input.- with the loan output of the second counter impulse c, the information input of which is connected to the fourth input of the code generator, the recording input is connected to the third input of the code generator, the fifth input of which is connected to the recording input of the first pulse counter, the information input of which is connected to the sixth input of the code generator. 3. The feedformer of claim 1, wherein the code generator contains the element OR, the synchronous driver of a single pulse, the selector-multiplexer, the code adder, the memory element, the output of which is connected to the output of the code generator and with the A-input of the code adder, the B-input of which is connected to the fourth input of the code generator, the output to the first information input of the selector-multiplexer, the second information input of which is connected to the sixth input of the code generator, output to the information input of the memory element, the synchronization count input of which is connected with, the output of the OR element. the first input of which is connected to the second input of the code generator, the second input with the output of a single-pulse synchronous driver, the first input of which is connected to the first input of the code generator, the second input - to the control input of the selector-multiplexer and the fifth input of the code generator, the third input - with the third input shaper codes. 4. The shaper of p. 3, of which is the fact that the synchronous shaper of a single pulse contains three flip-flops, each of which is D-type, the C input of the first of which is connected to the first input of the synchronous shaper a single pulse whose second input is connected to the C-input of the second trigger, the D-input of which connected to the bus logical zero, S-input - with the S-input of the first trigger and with the direct output of the third trigger, the inverse output of which is connected to the output of the synchronous single-pulse driver, the third input of which is connected to the C-input of the third trigger, whose O-input is connected with the direct output of the first trigger, the D input of which is connected to the direct output of the second trigger. Log in Log 2 Login5 Login it Login / J n Exit 15 but l sixteen B (Ng Fig z Figz Fi & 4