SU1633496A1 - Device for reducing fibonacci codes to minimal form - Google Patents

Abstract

The invention relates to computing and is intended to obtain both minimal and other forms of representation of Fibonacci codes. The purpose of the invention is to enhance the functionality by obtaining intermediate code combinations and performing the Fibonacci p-code conversion. The device contains information input 1, information output 2, shift register 3, convolution unit 4, elements OR 5-9, elements AND 10-13, elements NOT 14 and 15, triggers 16 and 17, master oscillator 18, shift register 19, counters 20 and 21, start input 22 and alarm device 23. At the initial moment, the shift register 3 is in the parallel information recording mode. At the start signal from input 22, the n-bit code from input, 5 1 is written to shift register 3. Further operation of the device is determined by the signal from the output of convolution unit 4 and the state of shift registers 3 and 19. If, after each cycle of operation of the device, the convolution condition for the next (p + 1) bits is not met, a unit is recorded in counter 20, its overflow on output 23 signals that intermediate form of representation of the source code has been received at output 2. The overflow signal of counter 20 increases the content of counter 21 by one. The overflow of the counter 21 signals the end of the process of bringing the code to its minimum form, and the device is returned to its initial state. 1 il. Yu f oo with 4 SO O5

Description

The invention relates to computer technology and is intended to obtain both minimal and other forms of representing Fibonacci codes. The purpose of the invention is the expansion of functionality by obtaining intermediate code combinations and performing the conversion of p-Fibonacci codes. The device contains information input 1, information output 2, shift register 3, convolution unit 4, elements OR 5-9,

elements And 10-13, elements NOT 14 and 15, triggers 16 and 17, the master oscillator 18, the shift register 19, counters 20 and 21, the input 22 start and signal output 23 of the device. At the initial moment, the shift register 3 is in the mode of parallel information recording. By a start signal from input 22, a n-bit code from input 1 is written into shift register 3. Further operation of the device is determined by the signal from the output of convolution unit 4 and the state of shift registers 3 and 19. If, after each clock cycle of the device, the convolution condition for the next (p + 1) -th digits is not fulfilled, a unit is written to counter 20, its overflow at output 23 signals that an intermediate form of source code representation has been received at output 2. The overflow signal of counter 20 increases the contents of counter 21 by one. The overflow of the counter 21 signals the end of the process of bringing the code to a minimum form, and the device is restored to its original state. 1 ill.

a

8

1633496

3

1633496

4

The invention relates to computer technology and is intended to reduce the Fibonacci codes to a minimum form.

The aim of the invention is to expand the functionality by obtaining intermediate code combinations and performing the conversion of p-Fibonacci codes. 10

The drawing shows a diagram of a device for reducing Fibonacci codes to a minimum form.

The device contains an information input 1, information output 2, 15

first shift register 3, convolution block 4, fifth element OR 5, second to fourth elements OR 6-8, first element OR 9, first to fourth elements AND 10-13, first 14? 0

and the second 15 elements are NOT, the first 16 and second 17 triggers, the oscillator 18, the second shift register 19, the second 20 and the first 21 counters, trigger input 22, signal output 23. 25

The device operates as follows.

In the initial state, shift registers 3 and 19, counters 20 and 21 contain zeros. Triggers 16 and 17 are in zero state. The logic 0 signal from the direct output of the trigger 16 prohibits the operation of the master oscillator 18. The logical 1 signal from the inverse output of the trigger 16 through the elements 35 OR 6 and 7 is fed to the input of the shift register 3 mode and determines its operation mode. In the initial state, register 3 is in the mode of parallel recording of information. By dd input 1, an η-bit sneaker is fed, which should be reduced to a minimum form. At the same time, a trigger signal is received at input 22. According to this signal, coming through the OR element 5 to the 45th sync input of shift register 3, the latter receives an input code, and this code is written in the η higher digits of the shift register 3, zero is entered in the lower p digits, and in the (p + 1) -th digit additionally, the contents of the least significant bit of the code entering the input 1 are entered. At the same time, the start signal additionally resets the counters 20 and 21 and, via the OR element 8, the second trigger 17 and shift register 19. The start signal before leads trigger 16 to a single state and allows the operation of master oscillator 18, under the influence of clock signals which shift information in shift registers 3 and 19 and increase the contents of counter 20. The convolution unit 4 verifies the convolution condition for the current (p + 1) - x bits of the source code. The most important operation of the device is determined by the signal from the output of the convolution unit 4. If, after each operation cycle, the convolution condition for the next (p + 1) -th digits is not fulfilled, then at its output there is a zero signal, element And 10 is closed and at its output there is a zero signal. Therefore, at the output of the element NOT 15, a single signal that allows the counter 20 to work and through the OR element 7 is fed to the first input of the shift register 3 mode input, the second input of the mode setting of which there is a zero signal from the output of the OR 6 element, since trigger 16 is in the unit condition. In this case, the shift register 3 is in the shift mode information in the direction of the higher digits (conditionally left) ·. Since the shift register 19 contains zeros, the element And 12 is open for information. The contents of the senior bit of the shift register 3 through the elements And 12 and OR 9 is fed to the input of the shift bit of the shift register 3. After the arrival of the next clock signal, the contents of this register are shifted to the left, and the shift value of the least bit is entered in the lower digit. If the convolution condition is satisfied, then at the output of the convolution unit 4 a single signal appears, which, through the element 14, sets the trigger 17 of the control to a single state. At the same time, a single signal is fed to the second input of the And 10 element, the output of which is also a single signal, and accordingly, a single signal will appear at the second input of the shift register 3 mode input, and zero at the first input of the mode reference. Before the arrival of the next clock signal, the shift register 3 is in the shift mode towards the lower digits (shift to the right) with zero being entered in the highest digit. With the arrival of the next clock signal, the contents of the trigger 17 is entered in the low order of the register 19 shift ·! At the direct exit of the junior time 1633496

10

fifteen

a series of this register, a single signal appears, and on the inverse output of the least significant bit - zero. A single signal from the output of the least significant bit of the shift register 19 through the AND 13 and OR 9 elements is fed to the input of the shift bit of the shift register 3 and the latter is transferred to the left shift mode. After the arrival of the next clock signal in the low order of register 3 shift is entered one and the contents of register 3 is shifted to the discharge to the left. Information is also shifted in register 19 and a zero signal appears at the inverse output of the second bit of the register. With this signal, the elements And 12 and 13 are closed and at the output of the element OR 9 there is a zero signal. Thus, the following 20 p + 1 clock cycles after the next leftward shift of the contents of the shift register 3 to its lowest digit are recorded zeros regardless of the convolution result in block 4. After p + 1 clock cycles at the direct output of the last (p + 2) th digit shift register 19 there is a single signal, which is fed to the second input of the element And 11 and after the next clock signal through the elements And 11 and OR8, the shift register and trigger 17 is set to zero. The process described above is repeated until the counter 20 is overflowed, the conversion module of which is equal to n + p + 2. The overflow signal of this counter at output 23 signals the receipt at the output 2 of an intermediate code modification of the source code, over which the operation of reduction to a minimum form is performed. Thus, in the device, it is possible to obtain intermediate forms, Fibonacci codes. Counter overflow signal 20 increases the contents of counter 2 by one. The counter recounting module 21 is chosen equal to p / p + 1, since more convolutions in the η-bit Fibonacci code are impossible. The overflow of the counter 21 signals the complete end of the process of bringing the code to a minimum form and puts the trigger 16 in its original state.

25

19

thirty

35

40

45

fifty

The contents of the senior n + 1 bits of register 3 shift corresponds to the minimum form of the original number. To cast the 1st Fibonacci code to mi55

The minimal form of convolution block 4 is performed on one element I.

Claims (2)

Claim Device for reducing Fibonacci codes to the minimum form, containing the first shift register, the convolution unit, the first and second elements OR from the first to the fourth elements AND, the first and second elements NOT, the first and second triggers, the master oscillator and the first counter, and the device start input connected to the input of the set in "1" of the first trigger, the input of the set to "0" of which is connected to the overflow output of the first counter, the output of the master oscillator is connected to the first input of the second element And, the output of the high bit of the first shift register ha is connected to the first input of the third element And, whose output and output of the fourth element And are connected respectively to the inputs of the first OR element, the output of which is connected to the input of the discharge that is moved when shifting towards the older bits, the first shift register, inputs c (p + 2) ~ go by (n + 1 + p) -th (p is a code parameter, η is a code width) whose information input bits are connected respectively to the bits of the information input of the device, the output of the first element is NOT connected to the installation input in "1" second trigger, outputs two st The second digits of the first shift register are connected to the first and second inputs of the convolution block, respectively; the outputs of the bits from the (p + 2) -th to (n + p + +1) -th first shift register are the outputs of the higher bits of the information output of the device, differing by that, in order to extend the functionality by obtaining intermediate code combinations and performing the conversion of the Fibonacci p-codes, it contains the second shift register, the second counter, the third through fifth PPC elements, and the output of the (p + 1) -th digit of the first register shift is the low-order output of the information output of the device, the output (n + pK) of the first digit of the first shift register is connected to the (K + 2) th input of the convolution unit (K = 1 ... p-1), the output of which is connected to the entrance of the first ele1633496 ment NOT, the device launch input is connected to the first input of the fifth element OR, with the installation inputs to the "O" of the first and second counters, the inputs $ p-low-order bits of the information input of the first shift register are connected to the input of the zero potential of the device, the low-order input of the information input of the device is connected to the input (p + 1) -th digit of the information input of the first shift register, the input of the discharge slid when shifting towards the lower digits, which is connected to the input of the zero potential of the device, the output of the second element AND is connected to the first input of the fourth element OR, the second input of which is connected to the input start of the device, the output of the fourth element 2 0 OR is connected to the installation inputs to ”0" of the second trigger and second shift register, the synchronous input of which is connected to the second input of the fifth OR element, the synchronous input of the second counter 25 and the output of the master oscillator, the direct output of the first trigger is connected to the trigger input of the master oscillator, the inverse output of the first trigger is connected to the first inputs of the third and 39 The second OR element, the outputs of which are respectively connected to the first and second inputs of setting the mode of the first shift register, the clock input of the first shift register is connected to the output of the fifth OR element, the output of the first AND element is connected to the second input of the second OR element and the second element input, the output of which is connected with the second input of the third element OR and the resolution enable input of the second counter, the overflow output of which is the signal output of the device and connected to the synchronous input of the first counter, the output of the second three Hera is connected to the information input of the third shift register, the inverse output of the first discharge of which and the output of the convolution unit are connected respectively to the first and second inputs of the first element I, the direct outputs of the first and (p + 2) -th digits of the second shift register are connected respectively to the first input of the fourth the element And the second input of the second element And the inverse output of the M-th (M = = 2 ... p + 2) of the second shift register category is connected to the M-inputs of the third and fourth elements I.