SU746502A1 - Device for comparing mn-digit binary numbers - Google Patents

Description

one

The invention relates to the field of automation and computer technology, can be used in computer systems for the selection of extreme numbers and numbers differing from a given attribute.

A device for comparing binary numbers is known, containing subtractive counters of compared numbers, reversible counters, summing up 1 counters of maximum and minimum differences, summing counters of the largest and smallest numbers, elements AND, OR, differentiating circuits, triggers, pulse generator l} .15

The device works on the principle of reducing the contents of deducting counters until a zero code is received in them and at the same time filling up 20 counters of the largest and smallest numbers, and after detecting the smallest number, filling the counters of the smallest and largest difference of numbers.

A disadvantage of the known device 25 is complexity and low speed, since the time required for comparing numbers is t () / fo where f is the frequency of the pulse generator, Nrri is the code of the maximum of 30

the number of numbers written in one of the subtractive counters. .

It is also known a device that contains an element of equivalence, the informational first inputs of which are connected to the device input buses, the second Bxoflu - to the control bus, the OR element, the output of which is connected to the first input of the element AND, the elements AND, OR, NOT, registers 5,

A disadvantage of the known device is its limited functionality, which reduces to the definition of extreme numbers.

The aim of the invention is to expand the functionality by providing the definition of extreme numbers and searching for numbers by features.

The goal is achieved by the fact that in the device containing m elements of equivalence, the infogging first inputs of which are connected to the input buses of the device, the second inputs to the first control bus, an OR element whose output is connected to the first input of the AND, m D-flip-flops, and the output of each i-ro element of equivalence is connected with informational 1,;,:,::. ., - :: ..- / VHSdsm 1st D-flip-flop and with the i-th input of the element OR, where, 2 ,,,, t, the synchronization inputs of the D-flip-flop are connected to the output of the And element, the second and the third inputs of which are connected to the second and third control buses of the device, the fourth control bus of the device is connected to the (t + 1) input of the OR element, the direct output of each 1st D-flip-flop is connected to the control input i -ro of the element of equivalence, the installation inputs in a single way D-flip-flops are connected to the installation bus in the initial state of the device, Functional diagram of the device put on the drawing,. The device contains m equivalence elements, m D-trigger 2, the element OR 3, the element AND 4, control buses 5–9. The device works as follows. m n-bit binary numbers x - ,,, вХ each is applied to its element of equivalence at the same time bitwise, starting with the highest order. The control bus 5 is given signals of a logical 0 or logical H when searching for the corresponding minimum or maximum numbers, as well as a specified number Y when searching for the specified numbers or a sign of a number when searching for numbers on the basis of. By the signal of the logical H supplied to the control bus 9, all m D-flip-flops 2 are set to their initial state. The control bus 6 of the choice of the type of operation is given a logical signal when searching for logical extreme numbers and 1 when searching for numbers on the basis of. On the control bus 7 of the code MasKy (the mask code is sequentially bitwise and simultaneously with the numbers X and Y; Actuating signals are sent to the control bus 8, The search for the maximum of the set of m numbers is performed as follows. On the control bus b. A logical O is applied, the control bus 7 is supplied with a mask code, all bits of which contain a logical signal. The control bus 5 is set to a logical signal. All D-flip-flops 2 are set to one Hji4Hpe state by the signal on control bus 9, all the control inputs of all the elements Next, with the first clocking pulse, the bits of all numbers are sent to the first breaths of the corresponding elements of the equivalence, the signals. Kiffifopfiix by singing the tag if (--| and times the number of i-ro numbers, C | (.d - output, the signal 1-go D-flip-flop, formed

Claims (1)

V 4 fc- - "------- after the end of (K-1) -th cycle, where, 2, ,,,, p. Consequently, when searching for the maximum number, i.e., when, at the first comparison cycle, a logical 1 signal is generated at the output of those equivalence elements, xj, 1, the OR OR 3 element detects at least one of the incoming signals. Obviously a number. cannot be maximal and should be excluded from further analysis, if among the received values of the highest bit of all numbers there is at least one unit, and in the highest bit of the given number is zero. If the output signal of the element OR 3 (Pj) is equal to one, then the same clock pulse through the element AND 4 goes to the C inputs of all D-flip-flops, of which only those with the O signal are present in the zero state Consequently, the control inputs of the equivalence elements of the corresponding D-flip-flops, which have changed their state, will receive a signal to prevent further analogous numbers from the corresponding numbers. If Pc 0, g, e, all the numbers of this bit are not equal to Y, the clock pulse will not go to the C inputs of D-flip-flops and their state will not change. At the next cycle, at the first inputs of all mc-hem equivalences, the values of the next most significant number of processed numbers are received and the comparison process proceeds similarly. As a result, the maximum numbers whose locations are fixed by a trigger that did not change the source state, Comparison can end at the first cycle if there is only one unit number among the highest-order values of m numbers. Similarly, the search for the minimum number is performed. The search for a number by a sign, a particular case of which is the search for a given number, is performed as follows. Suppose a search is made for a number, in which category it is a single value, and in e it is zero and indifferent. dah, where f 0, 1 ,,,,, p, e CC, Therefore, the input of the device is sequentially bitwise and at the same time with m numbers the mask code, the kth, C of which bits have a single value, and the rest are null . The control bus 5 is also supplied successively bitwise and simultaneously with m numbers the number Y with the above values of the ith and ith bits. All b-triggers are set to a single ccx; that is, With the first clock pulse, the snapshots of all m numbers are fed to the first inputs of the corresponding equivalence elements. At the output of the element OR 3 there is a single signal, regardless of whether they are equal or About function (Y XK) QK ,, (CC –q2.fV - I К-Ч / «« «A to K x - Clock pulses arrive at the C inputs D - triggers only in K-th and ft-o-M cycles, therefore, during the remaining cycles there will be no change in the state of the circuit. Then, in the K-th cycle, those numbers whose K-th digit has a zero value are excluded from the analysis, and in the -th so those numbers, In -th and bit of which has a single value (Yc; -x),; 0, then the number x is to be excluded and, if (the number of yy is to be excluded, where r 0.1, ,,., T, g 7 i. In the end, after the n comparison steps, D-flip-flops that did not change the initial state will record the location of numbers with specified attributes. The search for a given number is carried out in a similar way, only the mask code should have all digits are single, and a specified number is supplied to the control bus 5. Thus, this device allows determining extreme numbers and numbers with a given attribute for the n conversion steps, and the information received at the input X, x, ... x does not erase that allows you to repeat the opera ii comparing, and location of numbers determined EDC trigger having a single state at the end of the comparison operation. The invention The device for comparing n p-bit binary numbers, containing m equivalence elements, the information first inputs of which are connected to the device input buses, the second inputs - with the first control bus, the OR element, the output of which is connected to the first input of the AND element, differing By the fact that, in order to expand the functionality by providing the definition of extreme numbers and searching for numbers by signs, the D-triggers are entered into it, and the output of every 1st equivalence element is connected to info the d input of the d.th D-trigger and the iM input of the OR element, where 1 1,2 ,,,, t, the synchronization inputs of the d-trigger are connected to the output of the AND element, the second and third inputs of which are connected to the second and third control device buses, the fourth control device bus is connected to the (t + 1) -th input of the OR element, the direct output of each i-ro D-flip-flop is connected to the control input of the 1st equivalence element, the inputs of the one-unit setting of the Triggers are connected to bus reset the device. Sources of information taken into account in the examination 1, USSR Copyright Certificate - 444180, cl, (3 06 F 7/04, 20.05,71, 2, USSR Author's Certificate 478303, cl, G 06 F 7/04, 15 , 05.72 (prototype),