SU1381479A1 - Digital display - Google Patents

Abstract

The invention relates to automation and computing and can be used in computer control systems and control panels. The purpose of the invention is to simplify the device. The goal is achieved by the fact that the device containing the pulse generator 1, the first counter 8, the decoder 9, the register register 5, the digital indicators 10, the second counter 3, the multiplexer 4, the block of registers 6, the element AND 2, the elements of AND-OR 7. 2 Il.

Description

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The invention relates to automation and computing technology and can be used in electronic computer control systems and control panels.

The purpose of the invention is to simplify the device.

Figure 1 shows the block diagram of the proposed device; figure 2 - block diagram of registers used in the device.

The device contains a generator of 1 pulses, the element And 2, the second counter 3, multiplexer 4, register 5 of the fifth, block 6 registers, elements I-IPI 7, the first counter 8, the first decoder 9, python indicators 10, the first (informational) input 11 , the second input (code) 12 and the third (installation) input 13 of the device.

Block 6 of the registers contains the fourth 14, first 15, second 16 and third 17 registers.

Register 5 contains the third counter 18, the trigger 19 and the second decoder 20.

The device works as follows.

In the initial state, the signal from the installation input 13 of the device, the contents of the comma 5 register and the register 14 of the register 6, is set to the zero state. The control inputs of the sample registers 15-17 receive a zero level signal, as a result of which a high impedance state is established at the outputs of the registers. At the same time, the digital indicators 10 are extinguished, since the code of forbidden information enters their information inputs.

On the information input 11 of the device receives the positional data code. for indication. The input code arrives, 45 starting from the higher bits. When there is a single signal at the i-th input of multiplexer 4 and when counter 3 reaches the corresponding binary code, a resolution signal appears at the output of multiplexer 4, which enters the input of the AND 2 element, prohibiting the passage of pulses from the pulse generator 1 to counter 3 and stops counter 3. The output signal from multiplexer 4 allows the binary code to be written, which corresponds to the incoming code from the data in the block of registers 6. At the same time

Register 3 of the com- mand is entered into the information that is present at the input (comma-code) 12 of the device. In this case, the first output of the fourth shift register 14 sets the write enable signal to the first register 15. When a new data code arrives, the corresponding binary code is entered into the register 15, while the second output of the shift register is set to enable the write signal to the second register 16 The initial content of register 15 is rewritten in register 16, that is, the information is shifted to the tetrad. Each time a data code is received, the content of the third counter 18 increases by one and corresponds to the number of entered bits, i.e. The display of familiarity in the group of digital indicators 10. When the signal is received by a decimal point on the second input 12, the trigger 19 generates a resolution signal that goes to the gate input of the second decoder 20. The output code from the counter goes to the second descrambler 20, from the output of which the address of the decimal point is received. To the control input of the decimal point of the digital indicators 10.

The clock pulses also trigger the counter 8, the output binary code of which is decrypted by the first decoder 9. At the output of the latter, the address of the sign is generated, synchronously with which the sign of the corresponding tetrad from block 6 of registers is received through the AND-OR 7 elements. The address of the mark goes to the inputs for recording digital indicators 10, and the mark code goes to the information inputs of the digital indicators.

In this way, the digits of the input number are displayed on the digital indicators. With the arrival of new bits, the contents of counter 18 are increased, and the contents of block 6 of registers are shifted by the tetrad, while the displayed number, together with the decimal point per group. ne indicators are shifted one place to the left.

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Thus, the invention allows to improve the technical characteristics, reduce hardware costs,

Thus, the invention allows to improve the technical characteristics, reduce hardware costs,

. will lead to a decrease in the cost of the device, increases the reliability of the device.

Claims (2)

1. A device for digital indication, comprising a pulse generator, the first output of which is connected to the counting input of the first counter, a descrambler, a register, the information input of which is the first input of the device, digital indicators, characterized in that, to simplify the device, it contains the element AND, the second counter, multiplexer, block of registers, AND-OR elements, the outputs of which are connected to the information inputs of digital indicators, the first control inputs of which are connected to the outputs of the decoder and the inputs of the AND-OR elements, the second inputs of which are connected to the outputs of the register block, the information input of which is connected to the output of the second counter and the control input of the multiplexer, whose information input is the second input of the device, and the output of the register the register is commanded and the first input of the element I, whose second input is connected to the second output of the pulse generator, and the output to the counting input of the second counter, the second control inputs of the digital indicators are connected to the output register point instruction, and adjusting the inputs of which registers are block the third input device. 2. The device according to claim 1, that is, that the register block contains the first, second, third and quarter registers, the setup inputs of which are the setup input of the register block, and the clock inputs - clock input the register register; the information input of the first register is the information input of the register block; the output of the first register is connected to the information input of the second register, the output of which is connected to the information input of the third register; the outputs of the first, second and third registers are outputs of the block Registers first output of the fourth register is connected to the control input of the first register, a second output - to the control input of the second register, the third output - to the control input of the third register, information of the fourth input register connected to the bus logic unit capacity. number code Utt (jf account Nat setup 0ut. 2 Code Znoka II notebook code heat } 2mfmpad 1 Code Signs in Ptetraz