SU1156074A1 - Control device with check - Google Patents

Abstract

A CONTROL CONTROL DEVICE containing a synchronization unit, a mode setting unit, a timer, a memory unit, a first register, a cycle counter, a switch, a comparison unit, the first and second groups of elements AND, the first, second, third and fourth elements OR, and the output the first element OR is connected to the reset input of the first register, the outputs of which are connected to the first inputs of the elements AND of the first group, the first group of outputs of the memory unit is connected to the group of information inputs of the timer, the output of which is connected to the control input the switch, the switch outputs are the device outputs, the output of the second element OR is connected to the first input of the third element OR and the direct inputs of the elements AND of the second group, and the reset code of the mode setting unit is connected to the trigger input of the synchronization unit, in that in order to increase the depth of control, the second register, the first and second start triggers, the first and second response triggers, the control trigger, the program end trigger, the cycle end trigger, the third and fourth groups of elements And, spot are entered into the device. ten AND elements, five OR elements, the first and second interval setting blocks, each of which contains an interval counter, the first and second control triggers, five AND elements, the first and second OR elements, and the output of the fourth OR element is connected to the reset input of the second the register, the outputs to (L toyi are connected to the second inputs of elements AND of the group, the outputs of elements AND of the first group are connected to the corresponding address inputs of the memory block, the second group of outputs of which is connected to the group of information inputs of the switch The output of the memory block is connected to the first input of the AND transient element, the output of which is connected to the J and K inputs of the end of the cycle trigger, the first output of the SNR block is connected to the first inputs 4 of the second and third elements AND, to the trigger inputs control and trigger the end of the cycle, the output of which is connected to the second input of the second element And, the output of the timer is connected to the second input of the first element And the third input of the second element And, the output of which is connected to the counting input of the cycle counter and the first input of the fifth Yshi element, outputs the fourth and fifth elements And are connected respectively to the first input of the sixth element OR and J-input of the right trigger

Description

pa start, the output of the first trigger trigger is connected to the first inputs of the seventh OR element and the sixth AND element, the output of which is connected to the second input of the sixth OR element, the unit code of the first response trigger is connected to the first input of the seventh And element and the L input of the second response trigger, output which is connected to the second input of the seventh element And, the outputs of the sixth and seventh elements OR are connected respectively to the first input of the eighth element And and the J input of the second trigger trigger, zero output of which is connected to the first R inputs the first and second control triggers and the first input of the first element OR of each of the interval setting blocks, the forward input of the ninth AND element, the second input of the eighth AND element, the timer reset input, the R-end trigger input of the loop and the second input of that element OR, the output of the fifth element OR is connected to the first input of the first and fourth elements OR, the output of the eighth element AND is connected to the C input of the second trigger trigger, the single output of which is connected to the first AND 10 inputs of the tenth and eleventh elements And These outputs of the mode setting block are connected to the first input elements of the third group, the outputs of which are connected to the inverse inputs of the elements of the second group and the group of information inputs of the cycle counter, the outputs of the elements of the second group are connected to the group of reset inputs of the cycle counter, the overflow outputs of which are connected to the second input the third element And the inverse input of the third element And

the output of which is connected to the first input of the display unit, the third group of outputs of the memory block is connected to the first inputs of elements AND of the fourth group, the outputs of which are connected to the group of informational inputs of intervals of each of the intervals setting blocks, the output of the third element And with the end-of-program trigger input, the output of which is connected to the second input of the twelfth AND element, the output of which is connected to the first input of the eighth OR element, the overflow output of the loop counter En with the second input of the display unit, the reset code of the mode setting unit is connected to the second input of the eighth OR element and the first input of the second EGSh element, the stop output of the mode setting unit is connected to the third input of the eighth OR element, the output of which is connected to the R inputs of the first and the second trigger trigger, bringing the output to the initial state of the mode setting block is connected to the fourth input of the eighth OR element and the second input of the second OR element, the output of which is connected to the second inputs of the AND elements of the third group and to R in ohm of the control trigger, the start output of the mode setting block is connected to the second input of the seventh OR element, the first inputs of the fourth and fifth AND elements, the mode setting setting of the mode setting block is connected to the third AND input of the twelfth element and the second input of the third OR element, the output of which is connected to P-input of the end-of-program trigger, the first blocking output of the mode setting block is connected to the second input of the first OR element, the second R-inputs of the first and second control triggers and the second input of the first OR element The first interval setting block, the output of the first element I of which is connected to the first input of the thirteenth element I and the first input of the first group of inputs of the comparison block, the output of the thirteenth element I is connected to the second inputs of elements AND of the fourth group, the second output of the block of the mode setting is connected to the second input the fourth OR element and the R-inputs of the first and second control triggers of the second interval setting block, the output of the first element AND of which is connected to the second input of the thirteenth, element AND, and the first input the second group of inputs of the comparison unit, the output of the synchronous mode of starting the mode setting unit is connected to the second inputs of the fourth and fifth elements AND, the output of the thirteenth, fourteenth and fifteenth elements AND and the ninth element OR are connected respectively to the gates, start-up, clock (m and reset the timer, the second output of the synchronization unit is connected to the first inputs w of the first and second elements And, and to the inputs of the second control trigger of the first interval setting block, the output of the first NIII of which is connected to the reset input with the first block of setting the intervals, the first input of the ninth OR element and the second input of the first group of inputs of the comparison block, the third output of the synchronization block — connections to the C input of the first trigger trigger, the third input of the fourth element. And the second input is the same (the And element, the output of which is connected to the first input of the fifteenth element I and to the first inputs of the third and fourth elements I of the first interval setting block, the fourth output of the synchronization block is connected to the first inputs of the first and second elements I and C the inputs of the second control trigger of the second interval setting block, the output of the first element {CSR of which is connected to the reset input of the interval counter of the second interval setting block, the second input of the ninth W and the second input of the second group of inputs of the comparison block, the fifth output of the synchronization block is connected to the fifth input the fourth element And the second input of the tenth element And, the output of which is connected to the second input of the fifteenth element and the first inputs of the third and fourth elements And the second block of the task intervals, The sixth output of the synchronization unit is connected to the second input of the sixth element K, the seventh output of the synchronization unit is connected to the input of the end of program trigger and the J input of the first control trigger of the first and second interval setting blocks, the outputs of the second IL elements of the first and second inputs of the fourteenth element And, the output of the second element of the first block of the interval setting block is connected to J- and inverse K-inputs; The second control trigger of this block, the group of sync inputs of the first register and the third input of the first group of inputs of the comparison block, the output of which is not compared are connected to the J input of the control trigger, the eighth output of the synchronization block is connected to the C inputs of the first and second response triggers, the output of the second element OR of the second block interval settings are connected to J- and inverse K-inputs of the second control trigger of the second interval setting block, the synchronous input of the second register and the third input of the second group of inputs of the comparison block, info The main outputs of the first and second registers are connected to informational ones of the first and second groups of the comparison unit, the input of the control object's response is connected to the information input of the comparative unit, the information output of which is connected to the third input of the seventh And element, the R input of the second response trigger, J - and the R inputs of the first response trigger, the zero output of which is connected to the R input of the second response trigger, the output of the seventh element AND is connected to the first output of the second element OR ORDEL from the block in the interval setting, the K-inputs of the first and second start triggers, the end of program I trigger, the first response trigger, the control trigger and the first control trigger of each interval setting block are connected to the zero potential bus, the control trigger output is connected to the third input of the display unit and fifth entrance of the eighth

element OR, the output of the second control trigger of each of the interval setting blocks is connected to the second inputs of the first and second elements AND of the corresponding interval setting block, the output of the second element AND of each interval setting blocks is connected to the third input of the first element OR of the corresponding interval setting block, the output of the third element And each of the interval setting blocks is connected to the C input of the first control trigger and the second input of the second element OR the corresponding interval setting block, one The primary and zero outputs of the first control trigger of each of the interval setting blocks are connected to the second inputs of the fourth and third elements, respectively. And the corresponding interval setting blocks, the output of the fourth element of each interval setting blocks are connected to the synchronous input of the interval counter and the first input of the fifth element And the corresponding reference block. intervals the interval counter output of each of the interval setting blocks is connected to. nropifM the input of the fifth element AND the corresponding set of ipterpal job, you move the fiveth element And each of the blocks of the interval set is connected to

the third input of the second element OR of the corresponding interval setting block.

The invention relates to automation and digital computing and can be used in the construction of programmable driver and test driver for automated process control and management systems. The purpose of the invention is to increase the depth of the control at the input of the device to provide asynchronous test and control actions. The introduction of the end-of-cycle and end-of-program triggers of the AND, OR elements and the relationships they cause makes it possible to control the generation of the end-of-cycle signals and the program of test and control actions. The introduction of the third block of Elementals And and the relations arising from them ensures the control of the recording of information in the cycle counter. The introduction of the fourth block of AND elements and their associated links allows the transfer of a code for the duration of intervals from the memory block to the blocks for specifying the intervals. Figure 1 shows the functional diagram of the device for controlling with the control; figure 2 - the same block synchronization; in FIG. 3, the same, control and indication pool, in FIG. A, the functional scheme of the timer; in FIG. 5, the same, comparator unit; 6 is a timing diagram of the operation of the synchronization unit and the interval setting unit. The device for controlling with control contains a synchronization block 1, a mode setting unit 2, a timer 3, the first, 4 and second 5 time setting blocks, a 6 pnm block, a count of 7 cycles, a counter 8 intervals of the block 4, the first 9 and the second 10 registers, switch 11, comparison block 12, first 13 start triggers, first 14 and second 15 response triggers, second 16 start trigger, control 17 trigger, program end trigger 18, cycle end trigger 19, first 20 and second control triggers block 4, first 22, second 23 and third 24 blocks of elements AND, fourth 25, five 26, sixth 27, re My 28th, Tenth 29th, Tenth 30th, Eleventh 31, Tenth 32, Seventh 33, Thirteenth 34, Fourteenth 35, Third 36, Twelfth 37, First 38, Second 39 Elements And devices, Third 40, Fourth 41, First 42 , second 43 and five 44 elements AND block 4, first 45, fourth 46, second 47, third 48, sixth 49, seventh 50, eighth 51 elements OR devices, fourth block of elements AND 52, nine 53, five 54 elements OR, the first 55 and second 56 elements of the OR block 4. Figure 1-2 also uses the following designation: device input 57, device output group 58, first to seventh th outputs 59.159 .8, respectively, of the synchronization block 1, the first - the eighth outputs 60.1-60.8 of block 2, the group of outputs 61.1-61.g of the code for the number of cycles of block 2, the second 62, fifth of 63 and the third 64 inputs of timer 3, output 65 of timer 3, the element outputs 66 and 43, the outputs 67 and 68 of the elements OR 55 and 56 of the first 4 blocks of the interval setting, respectively, the outputs 69-71 of the second 5 blocks of the interval setting, the outputs 72.1-72.p of the fourth block of the elements And 52, the first group of outputs 73.1 73. m of block 6 of memory, the second group of outputs 74.1-74.p code of block 6 of memory, code 75 of the end of the cycle of block 6 of memory, output 76 of the element OR 47, output one 77 counters 7 cycles, output 78.1-78.9 of the first 9 registers, outputs. 79.1-79.5 of the second 10 register, inverse output 80 of the second 16 start trigger, output 81 of the trigger 17 of the control, outputs 82-87 of that 29j one of the above 31 and the fifteenth 30 of the ninth 32, the seventh 33 and the twelfth 37 elements And, respectively, the first 88 and the second 89 outputs of the block 12. The synchronization unit 1 (Fig. 2) contains the first 90 and second 91 pulse distributors, the pulse generator 92, the unit generator 93, the first element AND 94 and the second element AND 95. The mode setting unit (Fig. 3) contains the generator 96 units 1 , the first 97 and the second 98 and the third 99 display elements, the first 100.1 - the third 100.3 resistors of the current limit, the first 101 - the eighth 108 switches for the 9 control 1 action, the group of switches 109.1 109 .f for eadan1M code of the number of cycles. Timer 3 (4v1G.4) contains a trigger 110, side elements I 111, first 112 and second 113 elements AND, element OR 114, and counter 115. Schyuk 12 comparison (r. 5) contains first 116 and 117 second switches, circuit 118 comparisons, the block of elements AND 119 and the element of the ISH 120. The designations in the timing diagram (.6) correspond to the numbers of the outputs or the numbers of the elements that are entered in the functional diagram of THE DEVICE41 FIG.1. I. The purpose of the main elements of the device for control and monitoring. The synchronization unit 1 is designed to form sequences of clock pulses that ensure the synchronization of the operation of all elements of the device. A clock pulse generator 92 generates initial pulse sequences (Fig. 2). It is activated immediately after power is applied. The pulses from the second output of the generator 92 are fed to two parallels, the flap distributor 90 and 91 operating flaxally. One of the distributors 90 and 91 forms three sequences of clock pulses in accordance with the timing diagram of FIG. 6. Clock. the pulses generated at the first output of the pulse generator 92 arrive at the output 59.1 of the synchronization unit 1. The clock pulses generated at the first and second homogeneous outputs of dividers 90 and 91 are fed separately to the outputs 59.2, 59.4, 59.3 and 59.5 ($ 1 synchronization. And the outputs 59.6 and 59, 8 of the synchronization unit 1, clock pulses are received from the outputs of the AND 95 and 9 elements. This ensures the formation of clock pulses only if there are test pulses of the same name simultaneously on the first and fourth outputs of the distributors 90 and 91, respectively. The generator 93 units generates a constant single signal that sync block output 59.7. The mode setting unit 2 (g.) Is designed to generate control actions on the device circuit, to set the number of control formation cycles and to indicate the device status. Elements and 97-100 indicators indicate the initial state of the device, a malfunction devices, the end of the program execution of the formation of control and test effects, respectively. Pushbutton switches 101-104 form a reset, stop, bring to the initial state and start the device circuit, respectively. Turning on the pushbutton switch 105 generates a signal that translates the device from automatic mode to manual. Pushbutton switches 106 and 107 form the interlocking signals of the operation of the first 4 and second 5 blocks of setting the intervals and the first 9 and second 10 registers when monitoring the operation of the device. A pushbutton switch 108 is designed to generate a signal that sets the synchronous start-up mode of the device based on a clock pulse from the output 59.6 of the synchro block. zacin. Pushbutton switches 109.1109 .E allow setting the binary code of the number of formation cycles: control and test actions. Timer 3 (FIG. 4) provides the formation of a control signal to the switch 11, permitting the issuance of a predetermined control or test action of a strictly defined duration at one or several outputs of the group of outputs 58 of the device. The principle of operation and the purpose of the timer 3 elements are as follows. In the counter 115, through the block of elements I 111, a code of the duration of the control signals is written, which 51 is fed to the inputs of the block 3c of the outputs 73.1-73.171 of the block 6 of memory. The write permission gives a signal from the output of the element 34, which enters the input 62 of block 3. While the counter 115 is in the zero state, its inverse output contains a single signal that opens the element 113 and the clock pulses from the output 84 of the element 30 and 30 pass through the elements AND 113 and OR 114 to the zero input of the trigger 110 and set it to its initial state. After the control signal duration code 115 is written to the counter, a single signal disappears at its output and the reset pulses no longer arrive at the trigger input 110. Block 3 enters start up mode. Switching on unit 3 is effected by a pulse arriving at input 64 of unit 3c of an output of element 35. On the falling front of this pulse, which is fed to the combined inputs J and C of trigger 110, the latter is set to one and at output 65 of unit 3 is a single signal that allows control or test signals to be output through a switch 11 to an output 58 of a device. At the same time, the trigger 110 opens an element 112 from its inverse output and an element 112, through which clock pulses start to flow to the input C of the counter 115 The pulses from element 84 of code 30. And the incoming clock pulses are subtracted from the number recorded in the dial 115, and when the latter returns to its original state, a single signal again appears at its output, which opens element 113 and the next clock pulse with output 84 of the element And 30 sets the trigger 110 to its original state. The trigger 110 removes a single signal from the output 65 of block 3 and closes the element 112 at its inverse output element 112, thereby stopping the flow of pulses to the input of counter 115. Thus, the output 65 of block 3 will generate a signal that controls the output information on the output of the device whose duration is strictly determined by the duration code received from the outputs 73.1-73.m of the six-way unit. The counter 115 is set to its initial 4 output by a reset signal received at input 63 of unit 3 of the seed of the element OR 53. Trigger 110 is initially reset with a reset signal removed from inverted output 80 of the second trigger 16. The functional diagram of the device for control and monitoring contains two identical blocks 4 and 5 of specifying the intervals. Consider the purpose of the elements of each block. The counter 8 is intended to count the time interval corresponding to the code of the interval length read from the third group of outputs of the memory block 6. It is a subtracting counter having n inputs (5 5) of parallel code writing, counting input C and reset input R. A single signal appears at the output of the counter only when it is reset. The code is written into the counter from the outputs of the AND 52 block of the elements, which are opened by the enable signal from the output of the AND 34 element. The reset of the counter 8 to its initial state is effected by the output of the OR 55 element, which is set up in three cases when the reset signal arrives from the output 80 of the start trigger 16, when it is in the initial state, when the blocking signal from the output 60.6 of the control panel 2 is received to the display used for checking the device, when the signal from the output of the AND 44 element is received, It is executed at the end of the formed interval. The first control trigger 20 permits the arrival of clock pulses from the output 83 of the element 31. To the counting output of counter 8, its input E is given a signal of a logical unit from output 59.7 of synchronization unit 1, and input K is connected to the zero pole of the power source. When the trigger 20 is in the initial state, the element 40 is opened with a single signal from the inverse output of the trigger 20. Through the element 40 and passes the first clock pulse from the output 83 of the element 41 and along its trailing edge the trigger 20 of the switch to one state. . With a zero signal from an inverse output, it prohibits the passage of subsequent-dead clock pulses through an AND 40 element, and a single direct output signal opens an And 4 element through which the second and subsequent clock pulses from an And 41 element's output arrive at the counting input of counter 8, as well as at the element input And 42. The trigger 20 is reset either by a reset signal from the output 80 of the trigger 16 start, or by a signal sent from the output 60.6 of the control and display console 2. The inputs R of the trigger 20 are united by OR, i.e. H1B can independently transfer the trigger to the initial state. The second control trigger 21 is designed to generate reset pulses of counters 8 and 115, as well as the impulse of write control codes to counters 8 and 115. At the J and K inputs of the trigger, a signal is output from the element OR 56 The input K is inverse. If a single signal appears at the output of the OR 56 element, the flip-flop 21 switches to one on the falling edge of the next clock pulse from the video 39.2 of the synchronization unit 1. A trigger 1 opens the elements AND 43, 44. As a result, the output of the element 44 turns out to be a pulse corresponding to the power between the clock pulses from the output 59.2 of block 1 that goes to its inverse input. This pulse passes through the cell OR 55 reset of the counter 8 and then through the element OR 53 to reset the counter 115. The next clock pulse from the output 59.2 of block 1 passes through the output of the element And 43, opens the blocks of elements And 52 and 111 and thus allows the recording of interval duration codes and for 1; control signaling s in the counters 8 and 115 respectively. Since a zero signal appears at the output of the OR 56 element, this same clock pulse returns its trigger edge 21 to its initial state with its falling edge. As a result, elements And 43, 44 are closed and subsequent clock pulses from output 59.2 of block 1 to their outputs do not pass. Trigger 21 is reset to the initial state with the same signals as trigger 20. Element And 42 allows passage to element of South School 56 (Ntl) -ro of the clock pulse coming from the output of the And 41 element simultaneously to the counting input of the counter 8 and the And 42 element. The number M is determined by the interval duration code previously recorded in the counter 8. Thus, the N 8 pulse returns the counter 8 to initial state. The last signal from the inverse output opens the element AND 42 and the (M + 1) -th clock pulse passes to the element OR 56. The element OR 56 forms pulses corresponding to the beginning and end of the interval defined by the pulse duration code recorded in counter 8. The pulse of the beginning of the interval passes through the element OR 56 from the output of the element AND 40, the pulse of the end of the interval from the output of the element And 42. The element OR 56 forms the pulse of the end of the interval when the input pulse from the output of the element And 33 to its input, which allows reducing the interval against at about Postup lenii corresponding signal from the control object 57 to the input device. . The purpose and principle of operation of the elements of the block 5 for specifying the intervals are similar to those described. The memory unit 6 is designed to store interval duration codes, control duration and test event duration codes, as well as codes. control signals. These codes are stored in memory block 6 at different addresses and simultaneously simultaneously parallel to n, m and -discharge codes, respectively, when one of the 5 inputs of a single signal is received from the output of one of the elements AND block 22. And the output signals of block 6 the memory is present for the entire time interval of the presence of a signal at the input of block 6. One bit of the block 6 of memory is allocated for storing signals of the mark marking the last control code of the impact in the generated sequence (cycle). 6, the memory of the last code at block output 75 appears as a single label tag. The counter 7 cycles is designed to determine a specified number of real-time and control and test actions cycles. . It is a subtraction {{counter}} that has t inputs for parallel recording of the cycle number code, a counting input and one inverse output, a single signal on which appears only when counter 7 is reset. The code for the number of cycles is recorded in counter 7 from outputs 61.1 to 61.t of block 2 of paraphase codes, which are formed by blocks of AND 23 and 24 elements. Permission to write the code to the counter is formed by elements OR 47 when the set signals return to their inputs output from output 60.1 and reset from output 60. 3 controls 2 control and display. The count of the number of cycles is produced by the counter b on the pulses of the end of the cycle, arriving at its counting input from the output 89 of the element And 39. When the device has been working for a given number of cycles, the cycle counter is reset and at its output 77 a single program end signal appears. The registers 9 and 10 are intended to set the number of the interval and form a signal for reading the codes from memory block 6. Both registers are identical and their output signals of the same name are fed to elements AND of the block of elements AND 22. This increases the reliability of the operation of the device, since the read signal from the memory block is formed only with simultaneous output of single signals at the same outputs of registers 9 to 10. Switching registers takes place to the leading edges of the pulses of the end of the interval, which form, respectively, with blocks 4 and 5, the assignment of intervals at the outputs 68 of the elements OR 56. The element OR 45 forms a signal to reset the register 9, if its input s received or a reset signal from the OR gate 54 vkoda or lock signal from the output 60.6 and a control unit 2 displays. Similarly, the OR 46 element generates a reset signal of the register 10 if either a reset signal from the output of the OR 54 element or a blocking signal from the output 60.7 of the control and display console 2 is received on its input. The switch 11 is designed to form control and test effects on one or more outputs 58 of the device.

The switch 11 contains k elements AND, to the combined first inputs of which a signal is fed from the output 65 of unit 3, allowing the issuance of control and test actions to the output 58 of the device. The values of the output signals of the switch 11 are determined by the code received from the outputs 74.1-74. To the memory block 6 to the second inputs of the elements I, and the duration of the output signals is determined by the duration of the signal from the output 65 of the block 3. The comparison unit 12 (FIG. 5) is designed for comparing the response time of the control and monitoring object with predetermined intervals, switching the object's response signal to the inputs of response triggers 14 and 15, checking the coincidence of the same output signals applied by blocks 4 and 5, specifying intervals and registers 9 and 10. Comparison unit 12 generates at its output a .88 signal corresponding to a failure in the operation of the device, or a mismatch between the response time of the object and the specified time interval. To do this, the inputs of the circuit 118 of comparison of block 12 are supplied with the same signals from YYKHODOV1 66, 67 and 68 of block 4 and 69, 70 and 71 of block 5, as well as outputs 78.1 - 78.S of register 9 and 79.1 - 79.S of register 10. When the discrepancy between the values of the signals on at least one pair of identical outputs, the comparison circuit 118 generates a single signal that is fed through the IL 120 element to the output 88 of the comparator 12. The block of elements 119 is designed to form signals corresponding to the number of the realized interval if the same signals are simultaneously entered by registers 9 and 10. The first switch 116 is intended to separate the response of the object to the input 57 of the device and the corresponding number of the realized interval. When coinciding single signals arriving at the input 57 of the device and from the output of the AND 119 block, the first switch P6 passes the data signal of the object's response to the output 89 of the comparison block 12. The second ko mytopatop 117 is designed to control the reaction time of the object specified fy time interval. To this end, its first inputs receive signals of the control object's response, and its second inputs receive signals from the outputs of the 1111 element block. Due to this, the response signal to the object that arrived during a specified interval will not pass to the output of the switch 117. For any signal dropout reaction from a given time interval, the corresponding inverse input KOh iyTaTopa 117 will be open with a zero signal from the output of one of the AND elements of the AND 119 element block, and the response signal will pass through the switch 117 and the AND 120 element to the output 83 of the comparison block 12, about the normal response time of an object to specified time parameters. I Control trigger 17 fixes the fact of error (failure) in the device operation and generates a single signal that returns to the initial state of the start trigger 13 and 16, stops the device, and enters the remote control 2 to indicate the failure of the device, the trigger 17 is set into the next state by the next clock pulse from the output 59.1 of the synchronization unit 1 after the arrival of the single signal at the input D. The reset 17 is reset to the initial state either by the reset signal or the initial signal from the outputs 60.3 and 60.1 of the remote control and display 2, which is fed to the inputs R of the trigger 17 through the element OR A7. The first trigger 13 is designed to synchronously start the device. The switching of the trigger 13 to a single state is effected by clock pulses from the output 59.3 of the synchronization unit 1, which are fed to the input C of the trigger. For a synchronous start of the device, from the outputs 60.4 and 60.8 of the control and indication console 2, single start signals of the device and a synchronous start mode, respectively, are generated, which are fed to the inputs of the And 26 element. The latter generates a single signal to the E input of the trigger 13. After this signal is received, the next a clock pulse from the output 59.3 of the synchronization unit 1 sets the trigger 13 to one state. A trigger 13 opens an element I 27 from its output, through which the clock pulses from the output 59.6 of the synchronization unit 1 pass. At the same time, the signal from the output of the trigger 13 passes through the element OR 50 to the input J of the second trigger 16 of the start, preparing it for inclusion. The trigger 16 starts the device, and after a single signal arrives at input 3, the trigger 16 switches to a single state with a regular clock pulse from output 59.6 of synchronization unit 1, which passes through the open elements AND 27, 28 and the element OR 49 to input C trigger When set to one, the trigger 16 by a zero signal from the inverse output shuts down elements 28 and 32 and removes the reset signal from blocks 4, 3 and 5 of the trigger 19 and registers 9 and 10. At the same time, a single signal from the direct output of trigger 16 opens the elements AND 29 and 31, allowing the passage of clock pulses from the outputs 59.5 and 59.3 of the synchronization unit 1 to the units 3, 4 and 5 of the device, respectively, and thus launched the device into operation. Triggers 13 and 16 are triggered by a signal from the output of the element OR 51, which generates a signal, when one of the following signals arrives at its inputs: a reset signal from the output of 60.1 block 2, a stop signal from the output of 60.2 block 2 output 60.3 of block 2, the signal of the device’s output from the output 81 of the control trigger 17 or the signal The end of the program from the output 87 of the element 36. The response triggers 14 and 15 are designed to generate a pulse at the end of the interval when the signal from the control object is received and the input 57 is arranged real estate. A single signal from the output of the object is fed to the input 57 of the device and then through the first switch 119 of the comparator unit 12 to the inputs R of the trigger 14. As a result, the reset signal from the trigger 14 is removed and it is prepared for switching to the unit state. The switching of the trigger 14 is carried out by the next clock pulse, which is fed to the input of the trigger 14 from the output 59.8 of the synchronization unit 1. The trigger 14, having switched over the falling edge of the clock pulse, with its output signals, prepares the trigger O for the response to switch to one 13 state. The one-trigger 15 temporarily single signal from the direct output of the trigger 1D arrives at the AND 33 element. As a result, at the output 86 of the AND 33 element, a single signal appears, which enters the interval setting blocks 4 and 5. The next clock pulse from the output 59.8 of the synchronization unit 1 is fed to the input of the trigger 15 and on its trailing edge it switches to the one state. With a zero signal from the inverse output, it closes the element AND 33. Thus, at the output of the element 33, a pulse of the end of the interval is formed with a duration equal to the period of the following clock pulses at the output 59.8 of synronization unit 1. The triggers 14 and 15 of the response are returned to the initial state upon termination of the action of the trigger, on the output 89 of the comparator 12. The end of program trigger 18 is designed to separate the pulse signal of the end of the program for generating control or test effects. A constant single signal is output from the 59.7 output of the synchronization unit 1, and input K is connected to the zero pole of the power source. A program end signal is generated at output 77 of counter 7. This signal opens element 36, at the output of which a signal appears at the end of the program in the form of a sequence of pulses with a clock frequency from the output 59.1 of unit 1 sync. This signal simultaneously arrives at element I 37 and input C of trigger 18. The first of the pulse sequence passes to the output of element AND 37 and then to element OR 51 and trigger 13 as a pulse signal at the end of the program. At the same time, trigger 18 is set to one on the trailing edge of the signal. , prohibiting the passage of subsequent pulses through the element and the trigger 18 is set to zero

state by reset signals from input 60.3 of block 2 and installation of block 2 into output from output 60.1. Trigger 10 is blocked in its initial state when outputting device output signal to manual mode at output 60.5 of block 2. At the same time the same signal closes the element And 37, banned-11

the elements OR 54, 45 and 46, the pulse of the end of the cycle will reset the registers 9 and 10.

Element And 25 is intended to form a signal allowing asynchronous start of the device. A trigger pulse passes at its output in the absence of a synchronous signal forming a pulse signal at the end of the program. The OR elements 47 and 48 combine the indicated signals and form a signal arriving at the input R of the flip-flop 18. The flip-flop trigger 19 controls the generation of the loop-end signal. The inputs J and k of the trigger 19 are connected to the output of the element 38 (input K is inverse). When code from memory 6 is read out, code for the last interval of formation of control and test actions from output 75 simultaneously receives a single signal that goes to the first input of the And 38 element. When its second input comes the signal from output 65 of the block. 3, allowing the issuance of the last in a given cycle of control or test actions on the output of the device, a single signal appears at the output of AND 38. It arrives at the output E and K of the flip-flop 19, which with the next clock pulse with the output 59.1 of the synchronization unit 1 switches to one state. A single signal from the output of the trigger 19 is fed to the input of the element And 39. When the output of the last in the cycle of control actions is completed and the signal at the output 65 of block 3 becomes zero, the element 39 opens and its output will receive a regular clock pulse from the output 59.1 of block 1 sync. At the same time, the same impulse, with its trailing edge, switches the trigger 19 to the zero state, so that at its input A there will be a zero signal, and at the input K - a single signal. With its output signal, trigger 19 will close element I 39 and prohibit the passage of subsequent clock pulses from it in code 59.1 of synchronization unit 1. The pulse of the end of the cycle from the output of the element And 39 will go to the counting input of the counter 7, as a result of which the contents of the counter 7 will decrease by one. At the same time, go through

15

start and when a start signal is received from output 60 of block 4. This pulse is a conjunction of clock pulses arriving temporarily at its inputs from outputs 59.3 and 59.5 of block 1 of synchronization. This pulse passes through the element OR 49 and AND 28 and switches the trigger trigger 16 to one state.

Element And 30 generates clock pulses that control the operation of the unit

3only if there are clock pulses from outputs 59.3 and 59.5 at both of its inputs, which provides an additional device for preventing the device from malfunctioning when it fails.

Element And 32 forms the signal to bring the device to its original state. This signal appears at output 85 of element 32, if the counter of the 7 cycles contains the code of the number of cycles that need to be implemented, and the trigger 16 is in the zero state. This signal enters block 2 and is used to indicate the initial state of the device.

Element AND 34 generates control pulses for writing codes into counters 8 of blocks 4, 5 and counter 7 of block 3. And element 35 generates a pulse at the end of the interval that controls switching of the trigger 110 of block 3. And elements 34 and 35 form the indicated signals only at the same time the signals in blocks 4 and 5 set the spacing, which increases the accuracy of the operation of the device.

The block of elements And 52.1-52. permits the passage of a timeout code from the outputs of memory block 6 to the inputs of counters of 8 blocks

4 and 5 set intervals.

Elements I-52.1-52.n are opened by a signal from an output of an element 34.

The OR 54 element generates a reset signal for the counter 115 of the block 3, if at least one of the interval setting blocks 4 and 5 has generated this signal.

The device for controlling the control works as follows.

After power is turned on, the device is reset. To do this, on block 2 using the pushbutton switches 109.1-109. dialing the code of the number of cycles of formation:

5607416

control or test effects that the device must implement. After that, using the push-button switch 101 of the remote control 2, a reset signal is generated, through which all the device memory elements are reset, including the counters 90 and 91 of the synchronization unit 1, and the counter 7 cycles is entered

10 given code of the number of cycles. The signal to the initial state of the device is indicated by the signal at the output 85 of the element 32, which is fed to the indicator 97 of block 2.

15 The device is launched in two modes: asynchronous and synchronous.

With asynchronous start on block 2 using a push button switch

20 104, a Start command is formed, which is fed to output 60.4 of block 2 and then to the input of AND 25.

Clock pulses from the outputs 59.3 and 59.5 of the synchronization block 1 are fed to the inputs of the AND 25 element. The next clock pulse will go to the output of the AND 25 element, and then through the SHSh 49 and AND 28 elements to the C trigger of the start trigger 16 and switch it to the unit state the The latter will remove the reset signal from the circuit elements of the device, close the E 28 element and from, cover the E 29 and 31 elements, through which the clock pulses from the output

.- 59.3 and 59: 5 are delivered to blocks 3, 4, and 5 of the device.

In synchronous start-up, at block 2, using the push-button switch 108, the synchronous start mode is set. The signal from the output 60.8 of block 2 opens the element H 26 and closes the element AND 25. When a signal is received, the Start from the output 60.4 of block 2 to the input J of the flip-flop 13 receives a single HbDi signal, and the next clock impulse from the output 59.3 of the block 1 transfers the trigger 13 to one state the It opens element I. 27, through which the next clock passes.

pulse from output 59.6 of block 1, which synchronizes the trigger. Passing through 1SHN 49 and I 28 elements, this impulse includes a trigger 16, the device is launched into operation in the same way as described.

The first clock pulse from the output 83 of the element And 31 passes through the element 60 and its rear edge switches the trigger 20 to the one state. At the same time, this clock pulse passes through the element OR 56 to the Face of the trigger 21 and to the output 68 of the block 4. During the action of this pulse, the next clock pulse from the output 59.2 of block 1, with its trailing edge, switches the trigger 21 to the unit state. The trigger 21 opens the elements AND 43 and 44. At the output of the element AND 44, a single signal appears which, having passed through the element OR 55, resets the counter 8 and simultaneously enters the input of the comparison circuit 118. The impulse received at the output 68 of block 4 passes the input 6 of register 9 and to the inputs of the comparison circuit 118. With its falling edge, it switches register 9 to the state in which a single signal appears at its output 78.1. When it coincides with the same signal. from the output 79.1 of the register 10 at the output of the element 22. A single signal appears, according to which, from the memory block 6, the codes are counted, corresponding to the first formation interval of the control or test actions. When a pulse from output 68 of block 4 coincides with a pulse of the same name from output 71 of block 5, the output of element I 36 leads to a pulse that goes to the combined J and C inputs of the trigger 110 of block 3 and trailing edge switches it to one. The following clock pulse from output 59.2 of block 1 passes through element 43 at output 66 of block 4. When a pulse of the same name arrives from output 69 of block 5, element 34 forms an impulse that opens the block of elements 52.1-52.n through which the duration code interval passes to the inputs of 5 "counters 8 blocks 4 and 5 and is recorded in these counters. Simultaneously, a pulse from the output: element AND 34 opens the block of elements AND 1 1 of block 3 and the code of the control or test action from the outputs 73.1-73.m of the block 6 writes to the counter 115 block 3. In addition to o, the pulse from the output 66 of block 4 is fed to the input of the comparison circuit 118. The same clock pulse from the 59.2 output. With its falling edge will return 1,418 flip-flop 21 to the initial state, since by this time the signal at the output of the element OR E 56 will be zero. The trigger 20, having switched to the single state, will open the element AND 41, as a result of which the second and subsequent clock pulses 83 of the element 31 will pass through the element AND 41 to the counting input of the counter 8 of the block 4. The counter 8 will start counting the time of the first control interval or test effects. At the same time, the trigger 110 with a zero signal from its inverse output will open the element AND 112 and the counter 115 will start counting the duration of the generated control or test action. A single signal from the direct output of the trigger 110 is sent to the output 65 of block 3 and further to the input of the switch 11, as a result, the output 58 of the device receives control or test actions in accordance with the code received on the switch 11c of the outputs 74.1-74. 6 memories. At the end of the specified duration of the control action, the counter 115 of block 3 returns to its initial state, opens element AND 113, through which the next clock pulse from the output 84 of element AND 30 will pass. This pulse through the element OR 114 will pass to the input R of trigger 110, which will remove a single signal from output 65 of block 3. As a result, switch 11 will stop issuing control or test actions to output 58 of the device. At the end of the countdown of the specified time of the first interval, the counter 8 of block 4 will return to the initial state, which will open the element I 42 and the next clock pulse from the output 83 of the element 31 will pass through the elements 41, 42 and the element IL 56 to the inputs G7 and K of the trigger 21 and the output 68 of block 4. As a result, the outputs of the elements And 43, 44, 35 and 34, similarly to that described, will be successively generated pulses, which will sequentially lead to the initial counters 8 and 115, transfer registers 9 and 10 to the next state, record codes in counters 8 and 115 and re traveling device PE, mining press forming next interval actuating or test action. The interval setting unit 5 is similar to unit 4, in parallel with it, generates a control signal at the outputs 69, 70 and 71. To increase the reliability of the device and significantly reduce the likelihood of issuing spurious control and test actions signals from the outputs 66. 69 and 68 71 And 34 and 35, respectively, which B1 give single output signals only when the single signals at the inputs coincide are supplied. At the same time, the whole device operation time is the same output signals of blocks 4, 5 and registers 9 and 10 are compared by circuit 118 of comparator block 12. Comparison circuit 118 provides a single output signal when the values of at least one pair of like signals are different. When a single signal arrives at input 3 of trigger 17, the latter switches to one with a regular clock pulse from output 59.1 of block 1. Trigger 17 with a single output signal through the OR 51 element resets the device to its original state, and at block 2 it illuminates the error indicator 98. The trigger 17 is reset to the initial state by the Reset or Initial signals from block 2. An important feature of the device operation is the possibility of reducing the interval of formation of control or test actions in accordance with the characteristics of the object of control and management that It significantly improves the accuracy of the timing of the subsequent signals at the output 58 of the device. For this purpose, the desired output of the object is connected to the input 57 of the device. When a single signal appears at input 57, it passes through the switch 116 of the comparison unit 12 to output 89 and the trigger pulse from output 59.8 of block 1 triggers trigger A and a signal appears at output 86 of element 33. On the trailing edge of the next clock pulse from output 59.3 of block 1, trigger 15 triggers and closes element AND 33. The impulse 1 74 20 formed in this way enters the OR 56 elements in blocks 4 and 5, as a result of which they form the necessary control signals as described above, which force the device into the next control action shaping mode despite the fact that the counters 8 have not yet returned to their original state. The triggers 14 and 15 return to their initial state when the signal from the output 89 of the comparison unit 12 is removed. The device implements an algorithm for controlling the time the object performs specified operations in parallel with the main algorithm for issuing test and control actions. For this purpose, the reactions of the object, entering the input 57 of the device, are fed to the inputs of the switch 117 of the comparison unit 12. If the object's response corresponds to the specified interval, then the corresponding input of the switch 117 will close a single signal from the output of the corresponding element AND of the block of elements AND 119 and the signal to the output of the switch 117 will not pass. If the response of the object exceeds the specified interval, then after its expiration the registers 9 and 10 switch to the next position and the signal received. from the object, will pass through the switch 117 and the element OR 120 to the output 88 | of the comparison unit 12. As a result of the next clock pulse from the output 59.1 of the synchronization unit 1, the trigger 17 of the control will operate, the device will stop further functioning and record the fact of an incorrect reaction of the object of control or control. The device functions similarly as described during the implementation of all N-1 () control formation intervals and test actions, where N g is the number of impact formation intervals. When reading from the memory block 6, a set of codes corresponding to the last interval, at the output 75 of the block 6, a single signal is recorded that marks the last interval. This signal arrives at the first input of the element 38, the second input of which receives a signal from the output 65 of block 3, which permits the control or test signals corresponding to the last interval to pass through the switch 11. At the output of the element 38, a single signal appears, as a result of which the next clock pulse from the output 59.1 of block 1 switches trigger 19 to the single state. When the signal at output 65 of block 3 ends, the next clock pulse from output 59.1 of block 1 passes through element 39. At the same time, the same clock pulse from output 59.1 of block 1 returns the flip-flop 19 to the initial state with its falling edge, with the result that the subsequent clock pulses cannot go to the element ID 39 and the pulse from the output of the cell AND 39 corresponds to the end of the cycle of forming control or test actions. It goes to the counting input of the counter for 7 cycles, decreasing its content by one by one. At the same time, it passes through the elements IL 54, 45, 46 and sets them in the initial state, which prepares the implementation of the next work cycle. At the end of the countdown, the time duration of the last interval of the counter 8 of block 4 and 5 returns to the initial state, and the device automatically proceeds to the working out of the next cycle of control formation and testing effects. After processing the last cycle of the pulse from the output of the element 89 And 3, the counter 7 cycles will be reset. At its output 77, a single signal is turned on, and at the output of an element 36 is a sequence of pulses. The signal from output 77 will go to console 2 to indicate the end of the program of the device operation. At the output of the element 37, a pulse signal will be generated corresponding to the end of the device operation. This signal through the 422 element liJlH 51 will reset the trigger 13 and 16 triggers, thereby terminating the operation of the device. To bring the device back to its original state on block 2, the new number of operation cycles of the device is set using the push-button switches 109.1-109.t, and the resetting signal of the device is generated using the push-button switch 103. According to this signal, all the memory elements of the device are brought back to the initial state, and the cycle number code is written to the cycle counter 7. At block 2, the program end indicator 99 goes out and the initial state of the program device 97 lights up. The proposed device provides high reliability of operation, virtually eliminating the possibility of generating false control or test signals, which is ensured by the presence of two blocks 4 and 5 of intervals and two registers 9 and 10. To check the correct functioning of the control elements from block 2 and 107 special blocking signals of block 4 and register 9 or block 5 and register 10. When forming one of these signals, the operation of the corresponding block and register is blocked After the device is started up, the comparator block 12 and the control trigger 17 should detect a failure or failure in the device circuit, as described above. The presence of this mode and provide. its elements and connections allow even greater reliability and reliability of the software device operation.

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Claims (1)

DEVICE FOR MANAGEMENT WITH CONTROL, containing a synchronization unit, a mode setting unit, a timer, a memory unit, a first register, a cycle counter, a switch, a comparison unit, the first and second groups of AND elements, the first, second, third and fourth OR elements, the output of the first OR element being connected with the reset input of the first register, the outputs of which are connected to the first inputs of the AND elements of the first group, the first group of outputs of the memory block is connected to the group of information inputs of the timer, the output of which is connected to the control input of the switch, the outputs of the switch are are output by the device outputs, the output of the second OR element is connected to the first input of the third OR element and the direct inputs of the AND elements of the second group, the reset output of the mode setting unit is connected to the trigger input of the synchronization unit, characterized in that, in order to increase the depth of control, the device is entered in the second register, the first and second start triggers, the first and second response triggers, the control trigger, the end of program trigger, the end of cycle trigger, the third and fourth groups of AND elements, fifteen AND elements, five OR elements, first the first and second interval setting blocks, each of which contains an interval counter, the first and second control triggers, five AND elements, the first and second OR elements, and the output of the fourth OR element is connected to the reset input of the second register, the outputs of which are connected to the second inputs of the AND elements groups, outputs of elements And the first group is connected to the corresponding address inputs of the memory block, the second group of outputs of which is connected to the group of information inputs of the switch, the output of the memory block is connected to the first input of the first element And, the output of which is connected by the J- and K-inputs of the end of cycle trigger, the first output of the synchronization unit is connected to the first inputs of the second and third elements of And, with the inputs of the control trigger and the end of the cycle trigger, the output of which is connected to the second input of the second AND element, . the timer output is connected to the second input of the first AND element and the third input of the second AND element, whose output is connected to the counting input of the cycle counter and the first input of the fifth OR element, the outputs of the fourth and fifth AND elements are connected respectively> With the first input of the sixth OR element and the J input of the first trigger 1156074, the output of the first trigger is connected to the first inputs of the seventh OR element and the sixth element AND, the output of which is connected to the second input of the sixth OR element, the unit output of the first response trigger is connected to the first the input of the seventh AND element and the 7th input of the second response trigger, the output of which is connected to the second input of the seventh AND element, the outputs of the sixth and seventh OR elements are connected respectively to the first input of the eighth AND element and the E-input nth start trigger, the zero output of which is connected to the first R inputs of the first and second control triggers and the first input of the first OR element of each interval setting unit, the direct input of the ninth element AND, the second input of the eighth element Y, the timer reset input, the R input of the end of the cycle trigger and the second input of the fifth OR element, the output of the fifth OR element is connected to the first input of the first and fourth OR elements, the output of the eighth AND element is connected to the C-input of the second trigger, the single output of which is connected to the first and inputs of the tenth and eleventh elements Й, the group of information outputs of the mode setting unit is connected to the first inputs of the elements of the third group, the outputs of which are connected to the inverse inputs of the elements of the second group and the group of information inputs of the loop counter, the outputs of the elements of the second group are connected to the group of counter reset inputs cycles, the overflow outputs of which are connected to the second input of the third element And and the inverse input of the third element And, the output of which is connected to the first input of the display unit, the third the group of * outputs of the memory block is connected to the first inputs of the AND elements of the fourth group, the outputs of which are connected to the group of information inputs of the intervals of each of the interval setting blocks, the output of the third AND element is connected to the first input of the twelfth AND element and to the trigger input of the end of the program, the output of which is connected to the second input of the twelfth element AND, the output of which is connected to the first input of the eighth element OR, the overflow output of the cycle counter is connected to the second input of the display unit, the output of the reset unit the mov is connected to the second input of the eighth OR element and the first input of the second IL element, the stop output of the mode setting unit is connected to the third input of the eighth OR element, the output of which is connected to the R-inputs of the first and second start triggers, the initialization output of the mode setting unit is connected with the fourth input of the eighth OR element and the second input of the second OR element, the output of which is connected to the second inputs of the AND elements of the third group and with the R input of the control trigger, the start output of the mode setting unit is connected to the second m the input of the seventh OR element, the first inputs of the fourth and fifth elements AND, the mode setting output of the mode setting unit is connected to the third, the input of the twelfth element And and the second input of the third OR element, the output of which is connected to the R-input of the end of the program trigger, the first output of the task unit lock modes is connected to the second input of the first OR element, the second R-inputs of the first and second control triggers and the second input of the first OR element of the first interval setting unit, the output of the first AND element of which is connected to the first input of the thirteenth AND element and with the first input of the first Group of inputs of the comparison unit, the output of the thirteenth AND element is connected to the second inputs of the AND elements of the fourth group, the second lockout output of the mode unit is connected to the second input of the fourth OR element and the R-inputs of the first and second control triggers the second unit for setting intervals, the output of the first element And which is connected to the second input of the thirteenth element And and the first input of the second group of inputs of the comparison unit, the output of the synchronous start mode of the task unit I mode connected to the second inputs of the fourth and fifth elements AND, the output of the thirteenth, fourteenth and fifteenth elements AND and the ninth element OR are connected respectively to the inputs of the gating, start, clock and reset the timer, the second output of the synchronization unit is connected to the first inputs of the first and second elements AND and with the inputs of the second control trigger of the first interval setting unit, the output of the first element OR of which is connected to the counter reset input of the first interval setting unit, the first input of the ninth element OR and the second input of the first group of inputs of the comparison unit, the third output of the synchronization unit is connected to the C-input of the first trigger, the third input of the fourth element And the second input of the eleventh element And, the output of which is connected to the first input of the fifteenth element Y and to the first inputs of the third of the fourth AND element of the first interval setting unit, the fourth output of the synchronization unit is connected to the first inputs of the first and second AND elements and with the inputs of the second control trigger of the second interval setting unit, the output is not the first OR element which is connected to the reset counter input of the interval interval second unit, the second input of the ninth OR element and the second input of the second group of inputs of the comparison unit, the fifth output of the synchronization unit is connected to the fifth input of the fourth element And and the second input of the tenth element And, the output of which is connected with the second input of the fifteenth AND element and the first inputs of the third and fourth elements AND of the second interval setting unit, the sixth output of the synchronization unit is connected to the second input of the sixth AND element, edmoy output connected to the synchronization block 7-input trigger end of the program and 7-input of the first control trigger of the first and second blocks of the interval setting, the outputs of the second OR elements of which are connected respectively to the first and second inputs of the fourteenth element AND, the output of the second element of the first block of the interval setting is connected to J- and inverse K-input No. 1 of the second control trigger of this unit, a group of sync inputs of the first register and the third input of the first group of inputs of the comparison unit, the non-comparison output of which is connected to the 7-input of the control trigger, the eighth output One synchronization unit is connected to the C-inputs of the first and second response triggers, the output of the second OR element of the second interval setting unit is connected to the J- and inverse K inputs of the second control trigger of the second interval setting unit, the second input is synchronized 1156074 histra and the third input of the second group of inputs of the comparison unit, the information outputs of the first and second registers are connected to the information inputs of the first and second groups of the comparison unit, the reaction input of the device control object is connected to the information input of the comparison unit, the information output of which is connected to the third input of the seventh element And, with the R-input of the second response trigger, 7- and R inputs of the first response trigger, the zero output of which is connected to the R input of the second response trigger, the output of the seventh element And is connected to the first output of the second OR element of each of the interval setting blocks, the K-inputs of the first and second start triggers, the end trigger of the program, the first response trigger, the control trigger and the first control trigger of each interval setting block are connected to the zero potential bus, the trigger output control is connected to the third input of the display unit and the fifth input of the eighth element. OR, the output of the second control trigger of each of the interval setting units is connected to the second inputs of the first and second elements And so of the corresponding interval setting unit, the output of the second AND element of each of the interval setting units is connected to the third input of the first OR element of the corresponding interval setting unit, the output of the third AND element of each of the interval setting units is connected to the C-input of the first control trigger and the second input of the second OR element of the corresponding interval setting unit, the single and zero outputs of the first control trigger of each of the interval setting units are connected to the second inputs of the fourth and third of the elements AND of the corresponding interval setting blocks, the output of the fourth element of each of the interval setting blocks is connected to the clock input of the interval counter and the first input of the fifth element AND of the corresponding interval setting block, the output of the interval counter of each of the interval setting blocks is connected to the second input. the house of the fifth element AND of the corresponding interval setting unit, you1156074, the output of the fifth element And of each of the third input of the second element OR of the interval setting units is connected to the corresponding interval setting unit.