SU1661820A2 - Operatorъs trainer - Google Patents

Abstract

The invention relates to devices for training operators. The purpose of the invention is the expansion of didactic possibilities by preventing the students from forming erroneous actions that contribute to the occurrence of emergency, irreversible situations. The device additionally contains the fourth 29 and fifth 30 elements OR, the third group of elements AND 31, the sixth element OR 32, the second trigger 33, the third element AND 34, the fourth delay element 36 and the third comparison block 35. 1 il.

Description

The invention relates to technical training devices, can be used in simulators for training ACS operators, and is an improvement to the invention in accordance with the author. St. Ms 1492366. The purpose of the invention is to expand the didactic capabilities of the device for training operators.

The drawing shows the functional diagram of the device.

The device contains the address register 1 (micro-commands), memory block 2 (firmware), micro-command register 3, the second element OR 4, the group of elements OR 5, the information board 6, the operator response input block 7, the comparison block 8, the first AND 9 element , second element 10, first trigger 11, first counter 12, second comparison block 13, register 14, first element OR 15, second group of elements AND 16, group of address registers 17 (microcommand), group of memory blocks 18 (microprograms) , the third element OR 19, the first element 20 of the delay, the first group of elements 21, the decoder 22, the second counter 23, the third delay element 24, the generator 25, the button 26, the second delay element 27, the trigger group 28, the fourth element OR 29, the fifth element OR 30, the third group of elements AND 31, the sixth element OR 32 , the second trigger 33, the third element And 34, the third block 35 comparison, the fourth element 36 delay. Position 37 marks the device’s external trigger input. Registers 1 and 17 are designed to specify the control components of the main and emergency operator activity algorithms, respectively. It contains as many cells as there are elementary operations in the corresponding algorithms of activity. Outputs 1 and 17 are the control inputs of blocks 2 and 18,

Unit 2 is used to store in the form of chips data on each operation of the main control algorithm, and a group of blocks 18 to store data on troubleshooting operations on the relevant operator actions that occur during the development of the main (regular) control algorithm. Each microinstruction of the firmware of block 2 contains two microoperations, and a group of blocks 18 contains three microcommands. In the first micro-operation

the code of the display indicator body 6 is stored, which changes its state in this operation of the control algorithm, and in the second, the code of the control body of the display board b,

which operator is required to act on this operation of the algorithm. In the third micro-operation, micro-commands of blocks 18 store for each operation the code of the control body of block 7, the erroneous activation of which in the course of executing the troubleshooting algorithm will lead to an accident. The outputs of blocks 2 and 18 are connected to the inputs of the register 3 through the elements OR 5.

Register 3 stores a microinstruction corresponding to the current operation of the algorithm performed by the operator.

Table 6 and block 7 are the physical model of the operator’s console of a real automated control system, with

by means of which he performs management tasks.

Unit 8 is designed to assess the accuracy of operator actions performed using the controls of unit 7.

Elements 9 and 10 perform the functions of switching devices at the choice of blocks 2 or 18, respectively, for issuing data to the operator either on the main control algorithm or on the emergency algorithm.

The trigger 11 controls the selection of the regular or emergency algorithms, respectively. Counter 12 is for counting.

the number of operations performed by the regular control algorithm before the occurrence of a malfunction.

Block 13 is used to determine the time at which a malfunction occurs, after

which the operator is concerned to proceed to the execution of the emergency algorithm.

Register 14 is for storing the operation number of the main algorithm on which the fault will occur.

The element IL AND 15 combines the outputs of the registers 17 and the outputs of block 8, element AND 9 with the shift input of register 1.

Elements 16 allow you to commute the required fault elimination algorithm — to work it out by the operator depending on the operation number of the main algorithm on which the malfunction occurred.

The elements OR 19 and 32 and the delay elements 20 and 36 synchronize the reading processes of the second and third micro-operations from register 3 to the comparison blocks 8 and 25 and the moments of comparison of the received codes in them.

Elements And 21 commute the outputs of the register 14 to the inputs of the decoder 22.

The decoder 22 makes it possible to unambiguously match the operation number of the main algorithm on which the malfunction occurred to the required algorithm for its elimination. neither

The counter 23 together with the generator 25 is designed to randomly set the operation number on which a malfunction should occur. The capacity of counter 23 is determined by the number of operations of the main algorithm.

Triggers 28 provide stable operation of the device during the student’s transitions from the basic algorithm to the emergency one and vice versa.

Element And 29 combines the direct outputs of the flip-flops 28 for enabling the reading of the contents of the third micro-operation of the micro-instructions from register 3 to block 35 through the elements 31.

The OR element 30 combines the outputs of the comparison units 8 and 35 to select the addresses of the following operations when the current operation is carried out without error.

Elements And 31 perform the functions of key elements in managing the reading of information from the third micro-operation of a micro-instruction.

The trigger 33 controls the activation of the control input of the comparator unit 35 through the AND 34 element.

Block 35 is designed to detect erroneous actions of the operator, allowed by him in the development of troubleshooting algorithms that can cause an emergency situation.

The device operates as follows.

With the simulator turned on, a signal appears at the external input 37 of the device. This signal triggers the generator 25, arriving at the input of register 1, emits the address of the first microcommand in block 2 and rewrites its contents to register 3 through the elements OR 5. At the first outputs of register 3, a signal appears that goes to board 6, and In accordance with the code recorded in the first micro-operation of the micro-command, the required organ of the board 6 changes its state. The operator, perceiving this information, acts on the appropriate governing body of block 7. Code

the involved body enters the inputs of the comparison unit 8 and, via the OR element 19, a command is received to the input of the register 3 to read the contents of the second micro-operation of the code of the required organ of the unit 7 to the inputs of the comparison unit 8. The comparison command comes from the output of the element OR 19 through the element 20 of the input delay of the comparison unit 8. This command makes 10 comparisons of the codes of the involved and the required governing body of the unit 4, received at the inputs of the unit 8 of the comparison. If the received codes are not the same, there will be no signal at the output of block 8. It appears 15 only after the coincidence of the codes and arrives at the same inputs of the elements AND 9 and 10 through the element OR 30. The signals at their other inputs come from the direct and inverse outputs of the trigger 11, respectively. The trigger 0 11 in the process of executing the main algorithm is in the single state due to the signal at its input, which comes from the output of the element OR 4, whose inputs combine the outputs of register 1. The signal from

5 direct trigger output 11 will open element 9, from the output of which the comparison signal of block 8 is fed to the input of counter 12 to count the number of operations performed, through delay 27

0 control inputs, as well as the input of register 1 through the OR element 15. The shift to the next cell of register 1 is made and the address of the next microcommand in block 2 is selected. Next, the operation process

5, the device repeats in the order described until the number of operations in which the malfunction occurs. It’s the next task. From the moment the device is turned on, generator 25 starts up and

0 generates clock pulses, which from its output are fed to the input of counter 23, the capacity of which is determined by the number of operations of the main control algorithm. In case of counter overflow, 23 counts

5 pulses start from the first operation. The training instructor, by pressing the button 26, stops the generator 25 by applying a signal to its other input and, through the delay element 24, by a signal to the control input

0 counter 23 rewrites its contents into register 14. Thus, the main algorithm will be executed until the number of operations performed by the operator matches (it is counted by the counter

5 12), and the number of the operation in which the malfunction occurs, i.e. code stored by the register 14. The fact of coincidence of these numbers

is checked with an increase in the content of the counter 12 per unit and is fixed by a signal at the output of the comparison unit 13. The signal from its output is fed to the input of the trigger 11, transferring it to the zero state, and to the inputs of the And 21 elements. The And 21 elements are given signals from the output of the register 14, i.e. The code of the operation number in which the fault should occur. This code goes to the decoder 22, and a signal appears at the output that corresponds to the code of the input signal, which will ensure an unambiguous selection of the corresponding register 17 and block 18. storing the algorithm for eliminating this fault. The signal from the inverse output of the trigger 11 enters the element 10 and opens it, and the element 9 closes due to the loss of the signal at the direct output of the trigger 11. During further work of the operator, the signal from the output of the comparison block 8 enters the element OR 30, the element 10 and the inputs of the And 16 elements. An element 16 And 16 will be open, the input of which will receive a signal from the output of one of the flip-flops 28, which is translated into one state by the arrival of a signal from the output of the decoder 22 to its input.

A call to the registers 17 selected in the group and block 18 will be made until the operator completes (the algorithm) the elimination of the malfunction. After this algorithm is executed without error, the operator returns to the basic algorithm. For this, the signal from the last cell of register 17 is fed to the input of the corresponding trigger 28, returning it to the zero state and closing the AND 16 element, as well as through the OR 15 element - to the shift input of the register 1, the signal from the output of which through the OR 4 element transfers the trigger 11 into a single state and reopens the element 9. And the device continues to operate in the described order, ensuring that the operator continues the basic control algorithm.

In order to fix operator errors that could lead to a crash or cause irreversible consequences when working out the troubleshooting algorithm, in block 35 comparison, the action codes on block 7 are checked with the emergency code that should not be performed on this algorithm operation. Its code is stored in the third micro-operation of micro-commands of microprogram block 18.

The code of the performed action goes to some inputs of block 35, and to others - the contents of the third micro-operation of register 3 through public keys - elements And 31, the signal to one of which inputs is fed through

the element OR 29 from the direct output of the trigger 28. The same signal is fed to the input of the trigger 33 and the signal from its direct output opens the element AND 34. The command through the element

OR 32 is fed to the input of register 3 and the contents of the third micro-operation is fed to the inputs of comparison unit 35, and through the delay element 36 to the control input of block 35. In case of the codes that did not match, the signal is output at the output of comparison unit 36 and enters the OR element 30 and to the input of the board 6 to report information to the operator about the error. This error is not gross.

5 i.e. will not lead to severe consequences, but in the case of incoming codes, it is precisely such an error that is recorded by the appearance of the signal at the output of block 35 and its supply to the input of the scoreboard 6, or rather to its transport driver Avari.

In this way, the device allows you to expand the didactic capabilities and to provide an increase in the level of preparedness of operators to perform 5 control algorithms, taking into account the occurrence of possible malfunctions in any operation of the control algorithm, and to focus operators' attention on errors that may be irreversible if you perform troubleshooting algorithms

Claims (1)

Formula of the Invention A device for training operators in 5 author. St. Ms 1492366, distinguished by the fact that, in order to expand the didactic capabilities of the device, the third comparison block, the second trigger, the third and fourth elements of AND, the fourth, fifth and sixth elements of OR, the fourth delay element, and elements of the third group are introduced , one inputs of which are connected to the corresponding outputs of the third group of the micro-register register, other inputs 5 with the output of the fourth OR element and one input of the second trigger, and outputs with the corresponding information inputs of the first group of the third comparison unit The informational inputs of the second The 0 groups of which are connected to the corresponding inputs of the third and seventh OR elements, the control input to the output of the third element AND, and the first and second outputs to the corresponding inputs of the information board, the first output of the third comparison unit and the output of the first comparison unit are connected to the first inputs the first and second elements AND through the fifth element OR, the output of the sixth element OR is connected to the control input of the register about microinstructions and the input of the fourth elementarygger, the other input of which is connected to delays, the output of which is connected to the single output of the first control unit, the inputs The input of the third element is And, the other of the fourth element OR is connected to the output of which is connected to the output of the second inlets of the corresponding group triggers.