SU1727145A1 - Operator trainer - Google Patents

Abstract

The invention relates to technical means for training control system operators and can be used for practical training of operators. The purpose of the invention is to expand the didactic capabilities of the device. Introduction to the device of the second memory block, the second, third and fourth groups of elements And, the second, third and fourth blocks in the course of time allows to evaluate the success of the training activity of the operator in terms of the number of attempts at the exercise stage, spent for transition to the training session. 1 il.

Description

The invention relates to the technical means for training control system operators and can be used for practical training of operators on simulators.

The purpose of the invention is to expand the didactic capabilities of the device,

The goal is achieved by the fact that a device for training operators, containing sequentially connected microcommand address register, microprogram memory block and microcommand register, the first output group of which is connected to the information board inputs, the second to the second inputs of the first comparison unit, the first group of inputs it is connected directly with the operator response input block, and through the first delay element to the control input of the micro-command register and the input of the delay element whose output connected to the control input of the first comparison unit, the first output of which is connected to the shift input of the address register, the control input of which is connected

with the counter input of the counter and the output of the second OR element, the first input of which is connected to the second output of the first comparison unit, and the second is the external input of the device and is connected to the installation input of the counter, the outputs of which are connected to the first inputs of the AND elements, the second inputs of which are connected to the overflow output of the microcommand address register, and the outputs of the AND elements via the decoder are associated with the indicator, further comprises a memory block, second, third and fourth groups of AND elements, second, third and fourth blocks and comparison, the second, third, fourth and fifth indicators, which are connected to the second output of the fourth comparison unit, the first inputs of which are connected to the outputs of elements of the fourth group, and the second to the third outputs of the memory block, the third control input of which is connected to the first inputs of the elements of the fourth group and the second output of the third unit of comparison, the first group of inputs of which is connected to the outputs of the third group ele00

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I. And the second - to the second output of the memory block, the second control input of which is connected to the first inputs of elements AND of the third group and the second output of the second comparison unit, the group of first inputs of which is connected to the outputs of elements AND of the second group, and the group of second inputs - to the first outputs of the memory unit, the first control input of which is connected with the output of the address register overflow and the first. the inputs of elements AND of the second group, the second inputs of which are combined with the second inputs of elements AND of the third and fourth groups and connected to the outputs of elements AND of the first group, the first outputs of the second, third and fourth comparison blocks are connected to the second, third and fourth indicators, respectively.

The drawing shows a block diagram of the operator training device.

The device contains micro-command address register 1, microprogram memory block 2, micro-command register 3, display panel 4, operator response input block 5, first comparison block 6, delay element 7, first element OR 8, first group 9 elements AND, block 10 memory, counter 11, second element OR 12, second group 13 elements AND, third group 14 elements AND, fourth group 15 AND elements, decoder 16. second 17, third 18 and fourth 19 comparison blocks, indicator 20 of the number of attempts in exercise, the second indicator 21 excellent marks, the third a good indicator 22, a fourth indicator 23 of a satisfactory assessment, and a fifth indicator 24 of an unsatisfactory rating. Panel 4 .and indicators 20-24 are scoreboard elements (not shown). Position 25 marks the device’s external trigger input. :

Register 1 of the microcommand address is intended to specify the control component of the operator's mastered algorithm. The register T contains as many cells as there are operations in the control algorithm, plus one cell to record the end of the algorithm. With the arrival of the signal, the first input of register 1 of the address is used to select the address of the microcommand in block 2 of the microprogram memory corresponding to the first operation of the algorithm, i.e. The situation of the start of control tasks is simulated. When a signal is applied to the second input of the register 1 address, the right shift is made and the address of the micro-command corresponding to the next algorithm operation is selected. Outputs The address register 1 is associated with the inputs of the microprogram memory unit 2. .

Firmware memory block 2 serves to store, in the form of microcommands, data about each operation of the control algorithm. The amount of firmware is determined by the number of operations in the control algorithm. When a signal appears at the address inputs of the microprogram memory unit 2, the microcommand of the current operation of the algorithm is read into the register 3 microcommand.

Register 3 microcommands stores briefly. time data on the current operation of the algorithm at the time of its execution. This register consists of two zones for micro-surgeries. In the first zone is stored the code of the display unit of the panel 4, which changes its state in this operation, and in the second zone, the code of the control panel body 5, on which the operator is responsible for

0 of the same operation algorithm.

The panel 4 of the display elements and the control body 5 are the physical model of the operator’s console of the real (studied) automatic control system and are used to work out the studied algorithm of activity.

Comparison unit 6 is designed to assess the accuracy of the operator’s control action on the panel body 5 by comparing codes

0 involved and required organs that go to the first and second inputs from block 5 and the second output register 3 microcommands, respectively. In case of coincidence of the received operation codes

5 is considered completed without error and the signal appears at the first output of block 6, otherwise, i.e. in case of an erroneous operator’s action, the comparison of incoming codes does not occur and the signal appears on

0 second output of block 6.

The delay element 7 and the first element OR 8 are used to synchronize the moments of reading the second micro-operation from register 3 microcommands and output a signal to

5 control input of unit 6.

The first 9, the second 13, the third 14 and the fourth 15 groups of elements And perform the functions of key elements.

Memory block 1.0 is designed to store statistics on the results — torture numbers that have passed from the exercise phase to the training phase by groups of the best, middle, and worst groups of predecessors of training. This data is stored in the first, second and third zones of memory unit 10, respectively.

Counter 11 counts the number of attempts spent by the student before the first error-free execution of the control algorithm.

The second element OR 12 combines the signals at the beginning of a new attempt when the device turns on the error and the student makes an error during the current attempt to correctly work out the algorithm.

The decoder 16 converts the binary code of the contents of the counter 11 into the decimal to represent the number to be trained by the first indicator 20.

The second 17, third 18 and fourth 19 comparison blocks serve to check the student’s result, i.e. the contents of counter 11 with statistics of the results of the predecessor groups and the corresponding evaluation with one of the indicators: the second 21 is excellent, the third 22 is good, the fourth 23 is satisfactory and the fifth 24 is unsatisfactory.

The device works as follows.

When the device is turned on, the signal from external input-25 goes to the installation input of counter 11 for zeroing and to the second element OR 12, from the output of which it is fed to the counting input of counter 11, recording. In it 1. and to the first input of register 1 of the microcommand address. This command selects the microcommand address in block 2 of the firmware memory corresponding to the first operation of the control algorithm. The selected microinstruction is copied from memory block 2 to register 3 microcommands. From the first outputs of register 3, the contents of the first micro-operation are rewritten on the display 4, where the corresponding authority changes its state in this operation of the control algorithm.

The operator, perceiving this information, makes the corresponding impact on the control panel body 5.

The code of the involved authority is. It goes to the first inputs of the comparison unit 6 and to the first element OR 8, from the output of which it is fed to the control input of the register 3 micro-commands and the contents of the second micro-operation are rewritten into the comparison unit 6 by its second inputs. The comparison signal is sent to the control input of block 6 through the delay element 7 from the output of the first element OR 8. If the received codes match, the signal appears at the first output of comparison block 6 and enters the second input of the address 1 register. In this case, a shift occurs to the next cell of the register 1 address, where the address of the microcommand corresponding to the next

operations of the algorithm, and the cycle of operation of the device is repeated in the order described.

In the event of an error, the signal appears at the second output of block 6 and compares to the second element OR 12. From the output of this element, the signal goes to the counting input of counter 11, increasing its content by G. and the first input of register 1 of address , thereby starting a new one

0 attempt for a trainee at the exercise stage.

When the operator correctly executes the entire control algorithm, the signal is received at the output of the register 1 overflow

5 addresses and go to the second inputs of the elements And 9 of the first group. From the outputs of the latter, it is fed i to the decoder 16. where it is converted into a decimal code and displayed to the learner using the first

0 indicator 20 in the form of the number of attempts it took to move to a new stage of training. In addition, the signal from the outputs of the elements And 9 of the first group is supplied to the second inputs of the elements And the second 13.

5 of the third 14 and fourth 15 groups, and the signal from the output of register 1 of the address is fed to the first input of the memory block 10 and to the first inputs of the second group of 13 AND elements, thus providing the supply to the second block 17 of comparable codes of numbers: attempts of a group of excellent operators - predecessors and this operator, respectively. If a

the first number is greater than or equal to the contents of counter 11, the student is exposed

5 is excellent in the evaluation of the signal at the first output of the second comparator block 17. Otherwise, i.e. if the learner has spent more attempts than the group, the signal is on the second output

0 of the second comparison block. This signal is fed to the second control input of the memory unit 10 and to the first assemblies of the AND elements of the third group. On the third block 14, the codes of the number of attempts of the group are not given.

5 good operators and this student respectively. If the first number is greater than or equal to the second, then the signal appears — on the first output of the third block 18, the operator is set to good

0, the illumination estimate of the third indicator 22, otherwise, the signal appears at the second output of block 18 and goes to the third control input of memory block 10 and to the first inputs of elements AND of the fourth group 15. At the final stage, the number of attempts of a satisfactory group and training operator accordingly. If the first number is greater than or equal to the second, the operator is given a satisfactory assessment and the signal appears at the first output of the fourth comparison unit 15 and goes to the fourth indicator 23, and if the second number is greater than the first, the learner is not satisfied with the illumination of the fifth indicator 24.

The proposed device allows to expand the didactic possibilities by means of an individualized assessment of the actions of the trained operator during the transition from the exercise phase to the training phase. This allows one to automate the assessment of the student, as well as to increase the efficiency of the practical training process by maintaining a high level of operator motivation in the initial stages of his training.

Claims (1)

Claims An apparatus for training operators comprising a response input unit, a first comparison unit, a first group of AND elements, two OR elements, a counter, a delay element, a scoreboard, two registers and a first memory block whose output is connected to the information inputs of the first register, the outputs of the first and second groups of which are connected respectively to the information inputs of the first group of the scoreboard and information inputs of the first group of the first comparison unit, the information inputs of the second group of which are connected from the output and block input response and inputs of said first OR gate; the output of which is connected to the control input of the first register and, through a delay element, the control input of the first comparison unit, the first and second outputs of which are connected respectively to the shift input of the second register and the first input of the second OR element, the second input which is connected to the installation input of the counter and is the input of the device, and the output is connected to the control input of the second register and the counting input of the counter, the outputs of which are connected respectively to the first inputs of elements AND of the first group, the outputs of which are connected to the inputs of the decoder, and the second inputs are connected to one of the outputs of the second register, the other outputs of which are connected to the inputs of the first memory block, the outputs are decoded. tori are connected to the information inputs of the second panel group, characterized in that, in order to expand the didactic capabilities of the device, the second, third and fourth blocks of comparison, the second, third and fourth groups of elements And and the second memory block are entered into it, the first reading input of which is connected to one of the outputs of the second register and the first inputs of elements AND of the second group, the second reading the input is connected to the first output of the second unit of comparison and the first inputs of the elements AND The third group, the third reading input is connected to the first output of the third comparison unit and the second inputs of the elements AND of the fourth group, and the outputs are connected respectively to the information inputs the first groups of the second, third and fourth comparison blocks, the information inputs of the second groups of which are connected to the outputs of the And elements, respectively, the second, third and fourth groups of And elements, the second inputs of which are connected to the outputs of the corresponding And elements of the first group, the second outputs of the second and third comparison blocks the outputs of the fourth comparison block are connected to information the inputs of the third group of scoreboard.