SU1425762A1 - Operator training apparatus - Google Patents

Abstract

The invention relates to the technical means of training the operators of the automated control system and can be used to train the control system operators. The aim of the invention is the expansion of didactic opportunities.

Description

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devices. The device additionally contains the first 12, second 14, third 26 and fourth 29 groups of registers, first 11 and second 27 groups of comparison blocks, quarter 20, fifth 5, sixth 10 and seventh 33 elements OR, four indicators 22-25, decoder 18, adder 17, fourth 28 and fifth 32 delay elements, counter 30. The proposed device expands the didactic capabilities of the simulator and increases the efficiency of operator training by increasing their motivation level and objectifying the ratings. The device also contains a 1.address register, microprogram memory block 2, microcommand register 3, information board 4, operator response input block 5, comparison block 6, element OR 7, delay element 8, delay meter 9, delay element 13, element OR 15, delay element 16, element OR 19, generator 31. I Il.

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The invention relates to the technical means of training the ACS operator and can be used to train the operators of control systems.

The purpose of the invention is to expand the didactic capabilities of the device.

The drawing shows a block diagram of a device for training operators.

The device contains the address register, microprogram memory block 2, micro-command register 3, information board 4, block 5 of input responses. operator actions, block 6 compare, element OR 7, element 8 delay counter 9, element OR 10, group of comparison blocks 11, group, registers 12, element 13 of delay, group of registers 14, element OR 15, element 16 of delay, adder 17 , decoder 18, element OR 19, element ШШ 20, element И, ПИ 21, indicators 22-25, group of registers 26, group of comparison blocks 27, element 28 of delay, group of registers 29, counter 30, generator 31, element 32 of delay element OR 33, device launch input 34.

Register 1 is intended to specify the control component of the operator's activity algorithm. It contains as many cells as there are elementary operations in the control algorithm, plus one more to indicate the end of the algorithm. The setup input of register 1 is associated with the device start input. When a signal appears on it, the address of the first microcommand in block 2 is read. Information input of the address register

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five

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designed for addressing addresses of subsequent micro-operations. When po--; When the signal is sent to it, the next cell is shifted to and the address of the next microcommand from block 2 is read,

Block 2 is used for storing data on each operation of the algorithm as a flash card: .1a control. When signals appear at the inputs of block 2, the microcommand reads the current operation of the algorithm in register 3.

Register 3 is intended for storing data of the current (practiced) operation of the algorithm. This register consists of two micro-operations: in the first one the code of the display organ of the board 4 is stored, which changes its state in this operation of the algorithm, and the second is the code of the control body of block 5, which the operator must influence in the same operation of the algorithm . From the first outputs of register 3 micro., The manda code of the required display unit enters the input of the board 4, and from the second outputs of the register 3 the code of the required control element enters the inputs of block 6.

Table 4 and block 5 are the physical model of the real operator's control panel.

Unit 6 is designed to evaluate the accuracy of the operator’s effect on the control unit of unit 5 by comparing the corresponding codes received from unit 5 and register 3,

Element OR 7 and delay element 8 synchronize read processes.

information of the second register operation 3 and the comparison instructions in block 6.

Counter 9 is intended to count the number of operator errors. When a signal arrives at its second input, the contents of counter 9 are copied to blocks 1I.

Registers 12 are designed to store the number of errors that are consistent with obtaining excellent, good, satisfactory, and unsatisfactory ratings.

Registers 14 are used to store binary valuation codes, in particular Excellent - 101, Good - 100, Satisfactory - 011, Unsatisfactory - 010.

Adder 17 is designed to summarize the evaluation codes from registers 14 and 26,

The decoder 18 allows for the sum of the estimates for the accuracy and timeliness of determining the overall assessment of the student.

Indicators 22-25 provide the operator with an assessment of its performance.

Registers 26 are stored, evaluation codes for the timeliness of operator actions. Their information is similar to the contents of the registers 14.

Blocks 27 are hearings for comparing the time spent by the operator when performing a given algorithm with the standard time values corresponding to setting excellent, good, satisfactory, and unsatisfactory ratings.

The registers 29 are intended to store the respective time standards.

The counter 30, using generator 3, calculates the time spent by the operator on execution of the control algorithm.

The device works as follows

When the simulator is turned on by the occurrence of a signal at the device input 34, register 1 reads the address of the first microcommand in block 2, and starts the rener 31, the pulses from the output of which go to the input of counter 30, the contents of the first microcommand enters register 3. From its first The exit code of the indication body enters the board 4, where the three

The organ being changed is changing its stock. The human operator, perceived by this change in the state of the display organ, performs a corresponding action on the control unit of block 5, the code of the affected organ enters the input of block 6 and through the OR element 7 the signal enters the input of register 3, by this command the contents of the second micro-operation (code of the required indication body) will be read from register 3 to block 6. The signal from the output of delay element 8 in block 6 compares incoming codes. If the codes match, which corresponds to an operator-free error-CTBi-no, the signal from the second output of the comparison unit 6 is fed to the input of register 1, where the shift to its second cell occurs, the address of the second micro-operation in block 2, is read and the device continues to function in the described above order with

If the codes do not match, an operator error is recorded, and the signal from the first output of block 6 is fed to the input of counter 9. Each time there is an error, the contents of counter 9 are incremented by one. Upon completion of the algorithm, the signal from the last register cell is fed to the input of the counter 9 and the delay element 13, to the input of the generator 31 to stop it and to the delay element 28. By this command, the contents of counter 9 are copied to all blocks 11, and through the OR element, the signal at the input of counter 9 is zeroed.

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of the delay element 13, the contents of register 12 are rewritten into the first block 11, where the number of errors made by the operator is compared with the number 5 which corresponds to the corresponding mark. If a coincidence occurs, the signal from one output of the comparator unit 11 is fed to the control input of the register} 4, and the excellent evaluation code

50 is rewritten to adder 17. If no matches occur, the signal from the other output of block 1 1 goes to the control input of another register 12, which stores a valid number of errors 55 flank sufficient to make a good estimate. Its contents are rewritten into the second block, I1 maturity, where the possibility is estimated for the operator to give a good mark by

shade infallibility, etc. to the fourth registers 12 and 1.4 with an unsatisfactory assessment of the actions of the student.

The signal from the output of the delay element 28 is fed to the input of the counter 30: At this command, its contents are rewritten into blocks 27, and the counter 30: is inserted through the OR element 33. The signal from the output of the delay element 32 rises to the input of the register 29. With this command, its contents (time information for excellent evaluation) are written to the first block 27. If the codes of the required and elapsed time coincide with the alignment, then the signal from the output of the first block 27 goes to JDerncTp 26, and from its output the code excellent evaluation (in time) is sent to the corresponding 7. od adder; In adder 17, a complex of estimation codes for inerrancy and Timeliness of the student's actions occurs. If the sum is 10, then the signal r (o is at the corresponding output of the decoder 18 and arrives at the organ of indicator 22, illuminating it, which corresponds to getting the fflex excellent assessment by the operator. If qyMMH points is eight. Or fv, then the operator is a good estimate; if six or seven, then

, ovately good, and if less than she

t | and - unsatisfactory.

 The proposed device expands the d-tactical possibilities of the simulator and increases the efficiency of operator training by increasing the level of motivation and objectification of the exhibited scores.

Forms in the invention

A device for training operators containing an address register whose setup input is an input, a device whose overflow output is connected to the generator's stop input, and information outputs are connected to the corresponding address inputs of the microprogram memory unit, whose outputs are connected to the corresponding information inputs the microcommand register, the control input of the microcommand register is connected to the output of the first OR element and the input of the first el: delay time, the outputs of the first group: - to the corresponding inputs NPR

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the second panel - rj to the corresponding inputs of the second group of the first comparison unit, the control input of which is connected to the output of the first delay element, and the inputs of the first group to the corresponding outputs of the operator response input block connected to the corresponding inputs of the first element OR, the second OR element, the output of which is connected to the input of the second delay element, the third OR element, the third delay element and the first counter, differing in that in order to expand the didactic possibilities the second device, the fourth and fifth delay elements, the fourth to the seventh elements OR, the adder, the decoder, the first - the fourth indicators, from the first to the fourth groups of registers, the first and second groups of comparison blocks, and the outputs of the first counter connected to the corresponding inputs of the sixth OR element and to the corresponding inputs of the first group of comparison blocks of the first group, the inputs of the second group of which are 0 Looded are connected to the outputs of the corresponding registers of the first group, the first outputs are with the inputs the corresponding registers of the first group, and the second outputs with the inputs of the corresponding: registers of the second group, the input of the first register of the first group is connected to the output of the third delay element, whose input is connected to the overflow output of the address register connected to the input of the fourth delay element and the read input of the first counter, whose setup input is connected to the output of the sixth OR element, and the information input is connected to the first output of the first comparison unit, the second output of which is connected to the information input p Registry of address; one of the information outputs of which is connected to the start input of the generator, the information input of the second counter is connected to the output of the generator, the read input to the output of the fourth delay element and the input of the fifth delay element, the setup input to the output of the seventh OR element, and the outputs to the corresponding inputs of the seventh OR element and to the corresponding inputs of the first group of comparison blocks of the second group, the inputs of the second group of which are connected to the outputs of the corresponding registers of the fourth group, the first outputs are from the input and the fourth group corresponds a register, and the second output -; with the inputs of the corresponding registers of the third group, the input of the first register of the fourth group is connected to the output of the fifth delay element, the outputs of the registers of the second and third groups are connected to the corresponding inputs of the first and second groups respectively of the adder and the corresponding inputs of the second OR element, exit

The second delay element, and the outputs - to the corresponding-f inputs of the depuser, the first output of which is connected to the input of the first indicator, the second and third outputs to the first and second inputs of the third OR element, respectively, the fourth and fifth outputs to the first and second inputs of the fourth element OR, respectively, and the sixth and seventh outputs - with the first and second inputs, respectively, of the fifth element SH, outputs of the third, fourth and fifth elements of the OIG are connected to the inputs of the second, third, and fourth indicators, respectively.

Claims (1)

Operator Forms, ₄₅ setpoint input A learning device containing an address register, the input of which is a device, the overflow output is connected to the generator stop input, and the information outputs are connected to the corresponding address inputs of the microprogram memory block, the outputs of which are connected to the corresponding information inputs of the micro command register, the control input of the micro command register is connected to the output of the first OR element and the input of the first delay element, the outputs of the first group; - to the corresponding inputs 1425762 6 displays, and the outputs of the second group to the corresponding inputs of the second group of the first comparison unit, the control input of which is connected to the output of the first delay element, and the inputs of the first group to the corresponding outputs of the operator response input unit connected to the corresponding inputs of the first OR element, the second OR element, the output of which is connected to the input of the second delay element, the third OR element, the third delay element and the first counter, characterized in that, in order to expand the didactic the rest of the device, the second counter, the fourth and fifth delay elements, the fourth to seventh OR elements, the adder, the decoder, the first and fourth indicators, the first to fourth groups of registers, the first and second groups of comparison blocks, the outputs of the first counter connected to the corresponding inputs of the sixth OR element and to the corresponding inputs of the first group of comparison blocks of the first group, the inputs of the second group of which are connected to the outputs of the corresponding registers of the first group, the first outputs to the inputs of the corresponding registers of the first group, and the second outputs with the inputs of the corresponding registers of the second group, the input of the first register of the first group is connected to the output of the third delay element, the input of which is connected to the overflow output of the address register connected to the input of the fourth delay element and the read input of the first a counter, the installation input of which is connected to the output of the sixth OR element, and the information input - with the first, the output of the first comparison unit, the second output of which is connected to the information input address, one of the information outputs of which is connected to the start input of the generator, the information input of the second counter is connected to the output of the generator, the read input to the output of the fourth delay element and the input of the fifth delay element, the setting j input to the output of the seventh element OR, and the outputs to the corresponding inputs of the seventh OR element and to the corresponding inputs of the first group of comparison blocks of the second group, the inputs of the second group of which are 1425762 connected to the second delay element, and the outputs are the outputs of the corresponding registers of the fourth group, the first outputs are to the corresponding inputs a decoder, the first output of which is connected to the inputs of the corresponding registers of the fourth group, and the second outputs 5 the house of the first indicator, the second and third outputs - with the first and second inputs with inputs of the corresponding registers of the third group, the input of the first register of the fourth group is connected to the output of the fifth delay element, the outputs of the registers of the second and third groups are connected to the corresponding inputs of the first and second groups, respectively, of the adder and with the corresponding inputs of the second OR element, the control input of the adder is connected to the outputs of the third OR element, respectively, the fourth and fifth outputs are with the first and second inputs of the fourth element ent OR, respectively, and the sixth and seventh outputs - with the first and second inputs, respectively, of the fifth OR element, the outputs of the third, fourth and fifth OR elements are connected 15 to the inputs of the second, third, and fourth indicators, respectively.