SU1661819A1 - Operators trainer - Google Patents

Abstract

The invention relates to the technical means of training control system operators. The purpose of the invention is to increase the didactic capabilities of the device. The device contains a micro-command address register, a micro-command memory block, a micro-command register, an information board, a response input block, a comparison block, a delay element, two OR elements, a counter, a decoder. Introduction to the device elements And and the trigger allows you to assess the level of preparedness of the students at the exercise stage in terms of the number of attempts before the first error-free execution of the algorithm and the individual transfer of the operator to the next stage of training on this indicator automatically. 1 il.

Description

The invention relates to the technical means for training control system operators and can be used for practical training of operators on simulators.

The purpose of the invention is to expand the didactic capabilities of the device.

The drawing shows a diagram of the device.

The device contains a micro-command address register 1, a micro-command memory block 2, a micro-command register 3, a display panel 4, a response input block 5, a comparison block 6, a delay element 7, an OR element 8, a trigger 9, an AND element 10, a counter 11, decoder 12, element OR 13, transparency 14 Exercise, transparency 15 Training and the workout number indicator 16, in which the trainee executed the control algorithm without errors for the first time.

Elements 4,14,15 and 16 schemes are combined in the scoreboard 17.

Position 18 on the diagram marked the external input start device.

Register 1 of the microcommand address is intended to set the control component of the operator's activity algorithm. Register 1 contains as many cells as there are operations in the control algorithm. With the arrival of a signal at the first input of register 1 of the address, the address of the microcommand is selected in block 2 of the microcommand memory corresponding to the first operation of the algorithm, i.e. The situation of starting the control task is simulated. When a signal is applied to the second input of register 1 of the address, the shift to the right is performed and the address of the microcommand corresponding to the next algorithm operation is selected.

The outputs of the address register 1 are associated with the inputs of the microcomputer memory block 2.

Block 2 of the micro-command memory serves to store in the form of micro-commands data about each operation of the control algorithm. The amount of firmware is determined by

ABOUT

about

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the number of operations in the control algorithm. When signals appear at the address inputs of the microcommand memory 2, the microcommand of the current operation of the algorithm is read into the register 3 of the microcommand,

Register 3 of microcommands is intended for short-term, for the time the operator has been working, the storage of data on the current operation of the control algorithm. This register consists of two zones for microoperations: the first one contains the code of the display organ of the panel 4, which changes its state in this operation, and the second the code of the organ of block 5, which the operator has to influence in the same operation of the algorithm.

Comparison unit 6 is designed to assess the accuracy of the control action performed by the operator in block 5 by comparing the codes of the involved and required organs, which enters block 6 through the second inputs from the second micro-operation of the register 3 microcommands. In the case of coincidence of the received codes, the operation is considered completed without error and the signal appears at the first output of block 6, otherwise, i.e. in case of an erroneous operator action, the comparison of the received codes will not occur, and the error signal will be fixed at the second output of the blocks 6.

The delay element 7 and the first element OR 8 are used to synchronize the moments of reading the second micro-operation from the register 3 microcommands and output a comparison signal in block 6.

Trigger 9 controls the illumination of the banners Exercise 14 or Training 15 of the information board 17 in the appropriate training mode.

A group of 10 elements and performs key functions when reading information from counter 11.

Counter 11 counts the number of workouts spent by the trainee before the first error-free execution of the algorithm.

The decoder 12 converts the binary code of the contents of counter 11 to the tenth to represent the workout number using the indicator 16 of the information board 17.

The second element OR 13 combines the first input of the register 1 address with the device start input and the second output of the comparator unit 6 to start a new workout after the device is turned on or the student has made an error.

Panel 4 display organs, banners 14 and 1b Exercise and Training

accordingly, the indicator 16 of the attempt number, on which the student managed to accomplish the control algorithm without errors, is combined into a scoreboard 17.

Device for training operators

operates as follows.

With the device turned on, the signal from the external input 18 goes to the installation input of the counter 11 and to the second element

0 OR 13, from the output of which it is fed to the counting input of the counter 11, writing 1 therein and the first input of the register 1 of the microcommand address. This command selects the microcommand address in memory block 2.

5 microinstructions corresponding to the first operation of the control algorithm. The selected microinstruction is copied from memory block 2 to register 3 microcommands. From the first outputs of register 3, the contents of the first micro-operation go to the display panel 4, where the corresponding authority changes its state in the given operation of the control algorithm.

The operator, perceiving this information, makes the appropriate impact.

- The code of the body involved by the operator is fed to the first inputs of the comparison unit 6 and to the first element OR 8, with

0 of the output of which it is fed to the control input of the register 3 micro-instructions, and the contents of the second micro-operation are rewritten into block 6 of the comparison. The signal from the output of the first element OR 8 through

5, the delay element 7 is fed to the control input of block 6, where the incoming codes are compared. If the received codes match, the signal on Vits at the first output of unit 6 of the comparison and will go to

0 second entry of the register 1 address.

In this case, a shift will occur to the next cell of register 1, where the code of the microcommand address corresponding to the next operation of the algorithm is written, and the device operation cycle repeats in the described order.

If the operator correctly completes the entire algorithm of the register of the 1 address, it will go to the first inputs of the elements And 8 and 10 and the contents of the counter 11, i.e. the unit will go through the fourth inputs of the information board 17 to the W indicator for display to the operator, In addition, the signal from the register 1 output is fed to the R input of the trigger 9 and

5 the team from its inverse exit transfers the student from the Exercise mode to the Training mode, illuminating the corresponding banner to the student 15.

In case of an operator making an error in performing the next operation, the signal is scanned at the second output of block 6 of the comparison.

This signal will go to the second element OR 13 and then from its output - to the counting input of counter 11, adding one more to its content. In addition, this signal arrives at the first input of register 1 of the micro-command address, returning the learner in a new training session to the first operation of the algorithm. At the same time, the illuminated transparency Exercise will remain, thereby signaling to the operator that he has not been transferred to a new training calculation.

The process will continue until the learner completes the entire control algorithm correctly and the signal does not appear on the last output of register 1 of the address.

Claims (1)

Invention Formula A device for training operators containing a response input block, a scoreboard, two OR elements, a comparison block, a delay element, a decoder, a microcommand address register, a microcommand memory block, a microcommand register, and a counter whose count input is connected to the output of the first OR element and the control input of the microcommand address register, the shift input of which is connected to the first output of the comparison unit, and the outputs connected to the address inputs of the microcommand memory block, the outputs of which are connected to the information inputs of the microcommand register, the control input of which is connected to the output of the second OR element, and the outputs of the first and second groups are connected respectively to the first groups of inputs of the scoreboard and the comparison unit, the second group of information inputs which is connected to the outputs of the response input block and the inputs of the second OR element, the output of which is connected to the control input of the comparator through a delay element, the decrypt outputs The ora are connected to the information inputs of the second group of panels, the first input of the first element OR is the device input, characterized in that, in order to expand the didactic capabilities of the device, a trigger and AND elements are entered into it, the outputs of which are connected to the decoder inputs, the first inputs are connected to the counter outputs, and the second inputs are connected to the R-input of the trigger and one of the outputs of the microcommand address register, the outputs of the trigger are connected respectively to the first and second information inputs of the board, and the S-input is connected to the The main input of the counter and the first input of the first OR element, the second input of which is connected to the second output of the comparison unit.