SU1686470A1 - Device for teaching operators - Google Patents

Abstract

The invention relates to practical training techniques and can be used in simulators to train control system operators. The purpose of the invention is to expand the didactic capabilities of the device. The device contains a micro-command address register 1, a micro-command register 3, an indication unit 4, an answer input block 5, a comparison block 6 and 7, a group of elements AND 8, a memory block 9, a trigger 10, an element OR 11, a group of elements OR 12, a group of elements And 13 and 14, trigger 15, element AND 16, element OR 17, trigger 18, pulse generator 19, registers 20 and 21, trigger 22, element AND 2 goigger 24. groups of elements AND 25 and 26 and element OR 27 1 Il.

Description

The invention relates to technical means for training operators and can be used in simulators for training operators of control systems.

The purpose of the invention is the expansion of the didactic capabilities of the device.

The drawing shows a structural diagram of a device for training operators.

The device contains a register 1 (microcommand addresses), a memory unit 2 (microprograms), a register 3 (microcommands), an indication unit 4, a response input unit 5, comparison units 6 and 7, a group of elements AND 8, a memory unit 9, a trigger 10, OR element 11, group of elements OR 12, group of elements AND 13 and 14, trigger 15, element 16, element OR 17, trigger 18, pulse generator 19, register 20, register 21 (microcommands), trigger 22, element 23, trigger 24, the group of elements And 25 and 26, the element OR 27 and the external input 28 of the launch device.

Register 1 (addresses) is intended for setting the control component of the operator activity algorithm.

The memory unit 2 is used to store microprograms in the form of microcommands of data on each operation of the control algorithm. When signals appear at the inputs of block 2, the microcommands of the current operation of the algorithm are read into register 3, which is designed to store data from the current operation of the algorithm. This register consists of two zones for microoperations, the first one stores the code of the display unit 4, which changes its state in this operation of the algorithm. and in the second microoperation, the code of the organ of block 5, 'on which the operator must act in the same operation of the activity algorithm.

Blocks 4 and 5 are a physical model of the operator’s console of a real ACS.

The first comparison unit 6 is designed to assess the accuracy of the operator’s impact on the organ of unit 5. If the incoming codes match, i.e. correctly performed by the operator, the signal appears on the first output of block 5. If the operator used the wrong organ of block 5, then the codes do not match and the signal appears on the second output of block 6.

The second block 7 serves to verify the fact that the operator detected an error in the management of this object before it proceeds to control the next object. If the operator has detected a mistake made earlier and resumed control of the same object, then in block 7 the codes coming from the output of block 5 and memory block 9 are compared, and the signal appears at the second output of block 7. The signal at its first output appears in the case if the operator started managing the next object without detecting or eliminating the error in managing the previous object.

The memory unit 9 stores the code of the control element, which should be used by the operator in the current operation, for the duration of the next operation to verify the fact of detection by the operator of a mistake.

The trigger 10 stores the fact of an error by the operator in the control process.

The OR element 11 combines the outputs of the first comparison unit to supply a signal to the shifting input of address register 1 to select the address of the next microcommand regardless of the error-free operation of the operator of the current operation.

The group of elements IL AND 12 allows you to rewrite the micro-command to register 3 both from the memory unit 2 in the normal learning mode, and from the second register 21 when the operator returns to the error if he did not find it or did not eliminate it.

Groups of elements And 13,14,25 and 26 perform the functions of key elements.

The trigger 15 is designed to organize the reading of information in the mode of testing the algorithm from block 2 of the memory and in the mode of eliminating errors from the register 21.

Element And 16 serves to supply a signal to the installation input of register 1 (micro command address) when the learning device starts.

The OR element 17, together with the trigger 18, organize the start of the generator 19 to highlight the desired organ of the response actions input unit 5, to prompt the studied action to the operator as a hint.

Register 20 stores the code of the current operation, which made a mistake, if it is not detected by the student, then this information is overwritten for long-term storage.

The trigger 22 provides the selection of the desired organ unit 5 for highlighting using a generator 19.

The And 23 element, together with the trigger 24, controls the process of reading information from the microcommand register 21 in the mode of presenting the student with the mistakes made at any stage of the control algorithm execution.

The device operates as follows.

Before turning on the device, its triggers 10 and 22 are in zero, and the triggers 15,18 and 24 are in single states.

With the inclusion of the device, the signal from external input 28 through the open element And 16 is fed to the installation input of register 1 (address). Based on this signal, the address code of the first microcommand in memory block 2 is selected from its first cell. This micro-command through the second group of open elements And 13 and the group of elements OR 12 is transferred to the registers 3 and 20. From the first outputs of the register 3, the contents of the first micro-command microoperation goes to the panel of the display unit 4, where the corresponding body changes its state. The operator, having received this information, performs the corresponding action with the help of the unit 5. The code of the involved control goes through the group of open elements And 26 to the first inputs of the comparison unit 6, the second inputs of which the contents of the second microoperation of the microcommand from register 3 are fed, i.e. code of the required authority. When the received codes match, the signal appears at the first output of block 6 and goes to the R-input of flip-flop 22 and the S-input of flip-flop 18, without changing their state, and also through the first element OR 11 to the second (shifting) input of register 1 (address). In this case, there is a shift to the right by one cell and the reading of the code of the next micro-command. With the error-free operation of the trained operator, the described cycle is pa-. device bots repeated. Moreover, the methodology provides for the possibility of the operator moving to the next operation, within the control of one object, even if an error is made on the current operation. To this end, the signal from the second output of the first comparison unit 6, which appears when the operator commits an error, also goes through the OR 11 element to the second input of register 1 (micro command address).

If the operator makes an error in the execution of the current control action, the signal appears on the second output of the comparison unit 6 and puts the trigger 10 in a single state and prepares the groups of elements And 8 and 25 for opening. In this case, the memory unit 9 stores the code of the required control unit 5, which was supposed to be involved in the last operation. In the process of fulfilling the task of managing the trainee, two options are possible: the operator has detected a mistake and is trying to eliminate it, or he has not found it.

In the first case, he performs the action corresponding to the previous operation, in this case, the code of the involved organ of block 5 through the group of elements And 25 is fed to the second inputs of the block 7 of comparison, the first inputs of which through the group of elements And 8 the code of the required authority is received. If they match, i.e. the operator eliminated the error, the signal appears on the second output of the comparison unit 7 and, through the OR element 27, enters the R input of trigger 10, returning the device to its original state, i.e. in the mode of testing the main algorithm.

If the operator does not find the error, then the signal appears on the first output of the comparison unit 7 and, in addition to returning the device to its original state via the described circuit, it also goes to the second input of the register 20 and the micro command corresponding to the operation on which the error was made and the error is not eliminated is rewritten for long-term storage in register 21 (microcommands). Similarly, all erroneous actions of the operator committed during the development of the training algorithm are recorded and stored.

After the operator completes the process of executing the algorithm, the signal appears at the output of register 1 overflow (addresses). This signal puts the trigger 15 in the zero state, thereby closing the group of elements And 13, and the trigger 24 sets to zero. In this case, a signal appears at the output of the And 23 element, it transfers the trigger 22 to a single state and goes to the second input of the microcontrol register 21. This command reads the code of the microcommand corresponding to the first error made through the group of elements OR 12 into register 3. At the same time, the signal through element OR 17 transfers trigger 18 to the zero state, the output signal of which goes to the start of generator 19. From the first outputs of register 3 the contents of the first microoperation are copied to the display unit 4, and the required organ changes its state, thereby restoring the indication of the algorithm operation on which the error was made, and from the group of the second outputs of the register 3 micro desired body technological command code through an open group of AND gates 14 is supplied to the input unit 5, the response, and the selected body is illuminated with flash illumination frequency oscillator 19. The operator acts on the body in the first block 6 compares incoming codes. In this case, the signal appears at its first output. He puts the trigger 11 in a single state and stops the generator 19, and the trigger 22 in the zero state. The signal from the single output of the trigger 18 goes to the input of the And 23 element and from its output to the second input 5 of the register 21 for reading the code of the next operation, on which the operator made a mistake. The operation cycle of the device to eliminate the next error is repeated in the described order for 10 given and all errors made until the signal appears at the output of register 21, which corresponds to the absence of errors. This signal translates the triggers 15 and 24 into a single state and prepares the And 16 element to receive a new trigger signal corresponding to a new workout.

Claims (1)

Acquisition Formulas 20 A device for training operators, comprising a response input input unit, two registers, two comparison units, three groups of AND elements, three OR elements, two triggers, an indication unit, the first and second memory blocks, the outputs of which are connected to the first inputs of the AND elements of the first group, the outputs of which are connected to the information inputs of the first comparison unit, and the second inputs are connected to the 30 direct output of the first trigger, the S-input of which is connected to the first output of the second comparison unit, the outputs of which are connected to the inputs of the first element OR, the output of which is connected to a shift input 35 of the first register, the outputs of which are connected to the inputs of the first memory block, the first group of outputs of the second register is connected to the inputs of the display unit, and the second group of outputs is connected to the first 40 group of inputs of the second comparison unit, characterized in that , in order to expand the didactic capabilities of the device, it introduced the third, fourth and fifth triggers, a pulse generator, 45 third and fourth registers, the fourth and fifth groups of AND elements, the group of OR elements, the first and second oh elements AND, the first input of which is the input of the device, and the output is connected to the installation input 50 of the first register, one of the outputs of which is connected to the S-inputs of the second and third triggers, the output of which is connected to the first inputs of the elements AND of the second group, the second inputs which are connected to the outputs of the first memory block, and the outputs are connected to the inputs of the second memory block, information inputs of the third register and the first inputs of the OR elements of the group, the second inputs of which are connected to the inputs of the second OR element and the outputs of the group of the fourth register, and the outputs are connected to the inputs of the second register, the second group of outputs of which is connected to the first inputs of the AND elements of the third group, the second inputs of which are connected to the output of the fourth trigger, and the outputs are connected to the information inputs of the response input block, the control input of which is connected to pulse generator input, and the outputs are connected to the first inputs of the AND elements of the fourth and fifth groups, the second inputs of which are connected respectively to the forward and reverse outputs 25 of the first trigger, and the outputs are connected the information inputs of the second groups, respectively, of the first and second comparison units, the outputs of the second comparison unit are connected to the inputs of the third OR element, the output of which is connected to the R-input of the first trigger, one of the outputs of the second comparison unit is connected to the input of the third register record, the outputs of which are connected with information inputs of the fourth register, one of the outputs of which is connected to the R-input of the second trigger, the direct output of which is connected to the second input of the first element And and the R-input of the third trigger, reverse the output of which is connected to the first input of the second element And, the second input of which is connected to the direct output of the fifth trigger, and the output is connected to the recording input of the fourth register and the S-input of the fourth trigger, the P-input of which is connected to the first output of the first comparison unit and S- the input of the fifth trigger, the R-input of which is connected to the output of the second OR element, and the return output is connected to the control input of the pulse generator.