SU1587560A1 - Device for teaching operators - Google Patents

Abstract

FIELD: engineering. The purpose of the invention is to expand the didactic capabilities of the device by giving the learner an assessment of the quality of his activity after the execution of each algorithm operation. Providing the learner with additional information about the results of previous groups of "best", "medium" and "worst" operators contributes to an increase in the level of student motivation. In the device containing the register 1 microcommand addresses, microprogram memory block 2, microcommand register 3, operator response input block 4, delay elements 7, 10, 18, decoder 9, counter 14, 15, information board 17, counter 8 entered, a learning results memory unit 11 and a decoder unit 13 with corresponding links. 1 il.

Description

WITH

with

1sl, with

Teaching the learner additional information about the results of the best, medium and worst operators npeflmecteyrouinx groups improves the motivation level of the trainees. The device containing the microcommand address register 1, the microprogram memory unit 2, the microregistration register 3 is an operator training tool and can be used in simulators for training control system operators.

The purpose of the invention is to expand the didactic capabilities of the device.

The drawing shows the structure of the device for training operators.

The device contains micro-command address register 1, microprogram memory block 2, micro-command register 3, operator response input block 4, comparison block 5, element OR 6, delay element 7, counter 8, decoder 9, delay element 10, memory block 11 learning outcomes, unit 12 comparisons, unit 13 decoders, counters 14. And 15, element OR 16, information board 17 and element 18 delay. In addition, in the drawing marked external input 19 launch device.

Register 1 is intended to specify the control component of the activity algorithm for the execution of the control task. It contains as many cells as elementary operations include an algorithm of activity, plus one. When a signal appears at one input of register 1, the microcommand address is selected in block 2 corresponding to the first operation of the algorithm. When the signal arrives at the other input of register 1, the next cell is shifted to and the microcommand address corresponding to the next operation of the control algorithm is read. 1 are connected to the inputs of block 2, the output of the last register cell 1 being connected to the counting input of counter 15,

Unit 2 is used for storing data in the form of micro-commands, for each operation of the algorithm, about the organs of the board 17 and the panel of block 4 involved. The number of micro-commands of the microprogram corresponds to the number of operations of the control algorithm. The outputs of block 2 are connected to the information inputs of the register 3,

Register 3 contains data on the current operation of the algorithm of activity and consists of an area for storing the organ code of the scoreboard.

the mandates, the operator response input unit 4, delay elements 7, 10, 18, the decoder 9, the counters 14, 15, the information board 17, the counter 8, the learning results memory unit 11 and the decoder unit 13 with the corresponding connections, 1 are entered silt

17, which changes its state in a given operation of the algorithm and the code area of the control body of block 4, on which the operator is required to act in the same operation

control algorithm.

Unit 5 is designed to assess the error-free operation of the operator by comparing the codes supplied to its first and second inputs, i.e. involved

and the required controls, respectively.

The OR 6 and 7 delay elements are used to synchronize the processes of reading the contents of the second micro-operation of register 3 into comparison block 5, as well as the moment of commencement of comparison of incoming codes in it. Counter 8 is designed to count the number of operations performed by the operator without error. The decoder 9 serves to control the reading of information from block 11. Element 10 allows spaced out the processes of recording and reading information in counter 8, Block 11 stores the training results of statistically reliable groups of previously trained best, average and worst predecessor operators. As such results, in block 11, for each operation of the algorithm, the number of errors allowed

Before the given operation of the algorithm, in the process of working out the control problems, the best, average and worst operators.

Block 12 is used to quantify the quality of the error free training of the operator. Block 12 contains three comparison blocks. The first inputs of block 12 receive the number of errors that were made before the current operation of the control algorithm of previously trained excellent operators, the second ones were allowed before the current operation of the control algorithm of previously trained average operators, and the third inputs are the results of the worst operators. The fourth, fifth and sixth inputs of block 12 receive the number of errors received before the current operation by the trained operator.

The comparison is made after the arrival of the signal from the output of the delay element 18, on the basis of which an estimate is made. The other input of block 12 is installation.

Block 13 is intended to convert the binary code of the number of errors, allowed by the best, average, worst, and learning by the operator, as well as the number of the current information into the decimal code. This information enters block 13. and then on board 17.

Counter 14 counts the number of errors made by the learning operator from the first to the last operation of the algorithm. Counter 15 counts the number of trainings for the trained operator to present this information to him using the scoreboard 17.

Element OR 16. managed by returning to the initial state of the board 17 blocks 11 and 12. Table 17 serves to provide the operator with information: on the course of the management process, educational information, assessment of the student, number of errors made by the best, average, worst, own errors and the number of the current workout. Element 18 synchronizes the start of the comparison in block 12. after the information arrives at its inputs.

The device works as follows.

With the device turned on, the signal enters the installation inputs of counters 8, 14, and 15 and zeroes them. In addition, this signal is fed to the input of register 1, where the address of the microcommand corresponding to the first operation of the control algorithm is selected. The selected micromagnet from block 2 is written to register 3. From the first outputs of register 3, the contents of the first micro-operation, i.e. The display unit, which changes its state in this operation of the algorithm, enters the first inputs on the display 17.

The human operator, perceiving this information, acts on the corresponding body of the control panel of block 4. The code of the body involved enters the block

5 and through the element OR 6 - to the control input of the register 3.

By this command, in block 5, the contents of the second micro-operation of the command are rewritten. those. the code required to operate the control panel organ. In addition, the signal from the output element OR

6 through the delay element 7 is fed to the control input of the unit 5, where the incoming codes are compared.

If the received codes match, i.e. If the operation is recognized to be completed without error, then the signal is received at the second output of the comparison unit 5. This signal will go to the input of register 1 and translate it to the micro-command address corresponding to the next operation of the algorithm. In addition, this signal will go to the information input of the counter 8, through the delay element 10 10 to the control input of the same counter 8 and to the control inputs of the counters 14 and 15.

From the output of counter 8 through the decoder 9, information from block 11 was selected on the number of errors made at the first operation of the algorithm by the best, average and worst groups of operators, and copied to block 12 and through the same inputs of block 13 of decoders to groups 20 of the third, fourth and fifth inputs of the board 17. In addition, from the output of the counter 14, the code of the number of errors made by the students in the first operation (error information comes from the first output, block 5, in 5 cases of received codes do not match), comes through block 13 of the decoders on board 17 and block 12 of the comparison. The comparison in it will begin with the appearance of a signal at its control input from the output of the 18 0 delay element.

In this case, i.e. error-free completion of the first operation of the algorithm, the operator is given an excellent assessment.

The device operates in the same way 5 times before the last operation of the control algorithm. At the same time, after each of its operations, the operator is given one of the possible estimates. As a result of the comparison, in block 12 of the codes 0 received at its inputs, an appropriate evaluation is made. The scoreboard 17 will provide the operator with an appropriate rating.

In addition, the signal through the element OR 16 will go to the installation inputs of the blocks 5 11 and 12 and the board 17 and bring them to their initial state.

 After the last operation of the algorithm is completed, the contents of counter 15 are increased by one due to the arrival of a signal at its information input from the output of the last cell of register 1.

The proposed device expands didactic possibilities and allows

to increase the efficiency of training of operators due to a reliable qualitative assessment of the accuracy of its actions during the development of the control algorithm after performing each of its operations, which helps to maintain a high level

(motivations of trainees throughout the workout,

The form of the invention. A device for training operators, containing a microcommand address register, the installation input of which is the device input, and the outputs are connected to the corresponding address inputs of the microprogram memory unit, the microcommand register, whose first group bypasses are connected to the corresponding inputs of the first information board group, input to the output of the first OR element and the input of the first delay element, and the outputs of the second group to the corresponding information inputs of the first group of the first block The comparison, the control input of which is connected to the output of the first delay element, and the information inputs of the second group - with the corresponding outputs of the operator response input block connected to the corresponding inputs of the first OR element, the second OR element, the second comparison block, the first group of which inputs are connected with the corresponding outputs of the first counter, and the first control input with the output of the second delay element, the second counter, the third delay element, the decoder, and the second OR element, from it, that for the purpose of teaching the expansion capabilities of the device, it introduced a third counter unit and the block decoders memory learning results, the address inputs of which are connected to

the output of the decoder, the control input, with the output of the second OR element, and the outputs with the corresponding inputs of the first group of the decoder block and the corresponding inputs of the second group of the second comparison unit, the second control input of which is connected to the output of the second OR element, and the outputs to the corresponding inputs The second element OR to the corresponding inputs of the second group of the information board, the inputs of the second group of the decoder unit are connected to the corresponding outputs of the first counter, the inputs of the third group to the corresponding the outputs of the second Counter, and the outputs with the corresponding inputs of the third group of information board, whose input is connected to the output of the second OR element, the inputs of the second and third delay elements, the control inputs of the first and second counters, and the information inputs of the third counter and the microcommand address register one output of the first comparison unit, the other output of which is connected to the information input of the first counter, the installation inputs of the first, second and third counters are connected to the input of devices An information input of the second counter connected to one of the address microinstruction register outputs, a control input of the third schetchika.- to the output of the third delay element and the data inputs of the register microinstruction - to the corresponding outputs of the memory unit firmware.

Claims (1)

Claim A device for training operators, which contains a micro-command address register, the installation input of which is the device input, and the outputs are connected to the corresponding address inputs of the microprogram memory block, micro-command register, the outputs of the first group of which are connected to the corresponding inputs of the first group of information boards, the control input is to the output of the first OR element and the input of the first delay element, and the outputs of the second group to the corresponding information inputs of the first group of the first comparison unit, I control the input of which is connected to the output of the first delay element, and the information inputs of the second group - with the corresponding outputs of the operator response input block connected to the corresponding inputs of the first OR element, the second element, or the second · comparison unit, the inputs of the first group of which are connected to the corresponding outputs of the first counter, and the first control input with the output of the second delay element, the second counter, the third delay element, the decoder and the second OR element, characterized in that, in order to expand d of the device’s tactical capabilities, a third counter, a block of decoders and a learning results memory block are introduced into it, the address inputs of which are connected to the decoder output, controlling the input of the output of the second OR element, and the outputs - with the corresponding inputs of the first group of decoders block and the corresponding inputs of the second group of the second block comparison, the second control input of which is connected to the output of the second OR element, and the outputs to the corresponding inputs of the second OR element and to the corresponding inputs of the second group of formation board, the inputs of the second group of the decoder block are connected to the corresponding outputs of the first counter, the inputs of the third group to the corresponding outputs of the second Counter, and the outputs to the corresponding inputs of the third group of the information board, the input of which is connected to the output of the second OR element, the inputs of the second and third elements delays, control inputs of the first and second counters and information inputs of the third counter and register of the address of the micro command are connected to one output of the first block of comparison, the other you the course of which is connected to the information input of the first counter, the installation inputs of the first, second and third counters are connected to the input of the device, the information input of the second counter is connected to one of the outputs of the micro command address register, the control input of the third counter is connected to the output of the third delay element, and the information inputs microcommand register - to the corresponding outputs of the firmware memory block. •