SU1320833A1 - Device for teaching operators - Google Patents

Abstract

The invention relates to a simulator and can be used to train control system operators. The purpose of the invention is to expand the didactic capabilities of the device. The invention is based on the creation of the ability of the operator to perform both the troubleshooting algorithm (subsystem reservation, etc.) and the basic control algorithm in the process of learning. The goal is achieved by the fact that the device containing the address register 1, memory block 2, microcommand register 3, comparison block 8, operator console 19, element OR 15, counter 12, entered the group of elements OR 5, elements AND 9, 10, elements OR 4, 16, trigger 11, pressure block 13, number register 14, address register 17, memory block 18. 1 il. S (L o u about 00 to 00

Description

The invention relates to simulators of control system operators and can be used to train control system operators.

The purpose of the invention is to expand the didactic capabilities of the simulator.

The drawing shows a functional cxeivra device for training control system operators.

The device contains the address register 1, the memory block 2, the microcommand register 3, the second element OR 4, the group of elements OR 5, the display panel 6 and the control panel 7, the comparison block 8, the first 9 and second 10 elements AND, the trigger P, the counter 12, comparison unit 13, number register 14, first element OR 15, third element OR 16, address register 17, memory block 18, operator panel 19.

Registers 1 and 17 are used to specify the control components of the main and emergency algorithms of the operator, respectively. They contain as many cells as there are elementary operations in the corresponding algorithms of activity. The outputs of the registers 1 and G / are the address inputs of memory blocks 2 and 18.

Unit 2 is designed to store in the form of microcommands data on each operation of the main control algorithm, block 18 - to store data on the operations of the troubleshooting algorithm that occurred during the execution of the main control algorithm. Each microprogram microprogram contains two microoperations. The first one contains the organ code of the panel 6, which changes its state in this operation of the control algorithm, and the second, the organ code of the panel 7, which the operator has to influence in this operation of the algorithm.

Register 3 stores a microinstruction corresponding to the current operation of the algorithm performed by the operator.

Panels 6 and 7 are the physical model of the operator console 19, the more real ACS on which it runs the control algorithm. Unit 8 is designed to assess the accuracy of the operator's actions performed using the organs of the panel 7.

Elements 9 and 10 perform the functions of switching devices at the choice of memory blocks 2 and 18, respectively, for issuing data to the operator either on the basic control algorithm or on the alarm algorithm.

The trigger 11 controls the selection of the corresponding, its algorithm operator activity.

Counter 12 is designed to count the number of operations performed by the main control algorithm.

Block 13 is used to determine the time of the malfunction, after which

five

the operator is concerned to proceed with the execution of the emergency algorithm.

Register 14 is intended to set the instructor to learn the operation number on which the "fault" occurs.

The device works as follows.

Before turning on the device, the designer records in the register the 14th number corresponding to the operation number of the main algorithm, on which the “inoperability occurs, after which the training operator should proceed to the algorithm of its elimination. When the device is turned on, register 1 selects the microcommand address in block 2, which corresponds to the first operation of the algorithm of activity being studied. This microcommand is rewritten through elements 5 into register 3, from where the contents of the first micro-op enters the bib panel according to the organ code recorded 0 in the first micro op, it changes its state. The operator perceived this change in the state of the display panel 6, generates an appropriate control action using the panel 7 organ, the output of which is fed to the input of block 8, and in case of coincidence with the code of the required organ received from the second microoperation of the microcommand the inputs of block 8, generates a signal at its output. This signal is fed to the inputs of the first 9 and second 10 elements And, the first of which is opened by the signal from the output of the AND trigger, since it is transferred to the signal state from the register output through the element 4. The signal from the output of element 9 goes to the counter 12 and to the input of element 15. The described process is repeated in all subsequent operations of the control algorithm until the number of operations counted by counter 12 coincides with the number recorded in register 14. In the case of coincidence of the codes of the indicated numbers, the output of block 13 is si The drive that triggers the trigger 11 to the zero state and through element 16 and the register 17 selects in block 18 micro commands that correspond to the occurrence of a malfunction of the control object. This micro-command through the elements 5 enters the register 3 and makes a change in the operation of the organs of panel 6, corresponding to the situation that has arisen. In case of a correct decision on this situation, the operator acts on the required control and, from the output of block 8, the signal goes through element 10 to the input of element 16 and selects the address of the microcommand corresponding to the following operation of the emergency algorithm.

This process continues until the operator successfully completes the entire "emergency algorithm, in which case the signal from the last (right) cell of the register 17

0

five

0

0

five

enters the input of element 15. From the output of this element, through register 1, the microcommand address is selected corresponding to the operation that follows the main algorithm after the operation on which the malfunction occurred.

The signal from the output of register 1 triggers 11 again to the one state, and the signal from its output opens element 9 to continue to issue information to the operator about the basic control algorithm. The device operates until successful completion by the operator of the main control algorithm.

 The use of the invention allows to expand the didactic possibilities by improving the quality of training of operators to perform control algorithms taking into account the occurrence of possible malfunctions in control objects at any predetermined operation of the activity algorithm.

Claims (1)

Invention Formula A device for training operators containing the first address register, the input of which is connected to the output of the first OR element, and the outputs with the corresponding address inputs of the first memory block, the first comparison block, the inputs of the first group of which are connected to the corresponding outputs of the operator console, and the inputs of the second group - to the outputs of the first group of the micro-command register, the outputs of the second group of which are connected to the corresponding inputs of the operator’s console. 0 a counter whose inputs are connected to the corresponding inputs of the first group of the second comparison unit, characterized in that, in order to expand the didactic capabilities of the device, a group of OR elements are entered into it, the first inputs and outputs of which are connected to the corresponding inputs of the first memory block and the corresponding inputs of the register microcommands, respectively, the second memory block, the outputs of which are connected to the second inputs of the corresponding OR elements of the group, the second OR element, whose inputs are connected to the corresponding the outputs of the first address register, register 5 numbers, the outputs of which are connected to the corresponding inputs of the second group of the second comparison unit, the third OR element, the first input of which is connected to the output of the second comparison unit, the trigger, the / input and the P input of which are connected to the outputs 0, respectively, of the second OR element and the second comparison unit, the first and second AND elements, the first inputs of which are connected to the output of the first comparison unit, and the second inputs to the forward and inverse outputs of the trigger, respectively, and the second address register, whose input is connected to the output of the inverse OR element, the outputs to the corresponding inputs of the second memory block, and one of the outputs to the first input of the first OR element, the second input of which is connected to the output of the first AND element connected to the counter input, the second input of the third el ment OR connected to the output of the second member I.