SU1730651A1 - Device for training operators - Google Patents

Abstract

The invention relates to the technical means of training control system operators. The purpose of the invention is to expand the didactic capabilities of the device. The device contains a response input block, two OR elements, a delay element, a first comparison block, a display, a first counter, the first group of AND elements, a decoder, a microcommand address register, a memory block, a microcommand register and a trigger. . The introduction of a second group of elements AND, the second and third delay elements, the third OR element, the second counter, the second comparison unit, the pulse generator and the data register into the device allows the student to automate the transfer from stage to stage. 1 il.

Description

The invention relates to the technical means for training control system operators and can be used for practical training of operators on simulators.

The purpose of the invention is to expand the didactic capabilities of the device.

The drawing shows a functional diagram of the device for training operators.

The device contains micro-command address register 1, microprogram memory block 2, micro-command register 3, display panel 4, response input block 5, first comparison block 6, delay element 7, element OR 8, trigger 9, group of elements AND 10, first counter 11, decoder 12, element OR 13, transparency 14 EXERCISE, transparency 15 EXERCISE, indicator 16, board 17, pulse generator 18, delay element 19, second counter 20, group 21 And, second comparison block 22, element 23

delays, data register 24, element OR 25.

Position 26 marks the inputs of the initial number setting to register 24, and position 27 denotes the external launch input of the device.

The address register 1, designed to specify the control component of the algorithm for performing the control task, contains as many cells as the elementary operations includes the algorithm of activity. When a signal appears at the first input of register 1, the microcommand address is selected in memory block 2 corresponding to the first operation of the algorithm. With the arrival of a signal at the second input of register 1 of the address, a shift is made to its next cell and the address of the microcommand corresponding to the next operation of the control algorithm is read. The outputs of register 1 are connected to the inputs of the microprogram memory unit 2, the output of the first cell of register 1 of the address is connected to the start input, and the output

h

yo

m

GJ O O SL

the last cell - with the input of the stoppage of the generator 18 clock pulses.

The microprogram memory unit 2 is used to store data in the form of micro-instructions for each operation of the algorithm on the display panel's 4 display panel 4 and block 5, the number of microprograms of the microprogram corresponds to the number of operations of the control algorithm. The outputs of block 2 of the firmware memory are connected to the inputs of the register of 3 microcommands.

The micro-command register 3 contains data about the current operation of the algorithm of activity and consists of two zones for micro-operations: the first is for storing the code of the organ of the control panel 1, which changes its state in this operation of the algorithm; in the second, the organ code of block 5 is stored, on which the operator is required to act in the same operation of the control algorithm.

The display organs 4 panels and block 5 are the physical model of the real workplace of the operator, with the help of which he masters the execution of control tasks for objects included in the ACS.

Comparison unit 6 makes it possible to assess the degree of accuracy of the operator’s actions by comparing the codes of the organs of the involved and the required organs of block 5. These codes are sent: to the first inputs of block 6 — directly from block 5, to the second — from the contents of the second micro-operation of register 3 microcommands. If the received codes match, i.e. recognition of the accuracy of the operator's action, the signal appears at the first output of the first comparison unit 6. Otherwise, i.e. if the received codes do not match, the signal is generated at the second output of block 6.

The first delay elements 7 and OR 8 are used to synchronize the reading of the contents of the second micro-operation from register 3 of micro-instructions to block 6, as well as the moment of commencement of comparison of incoming codes in it.

The trigger 9 controls the illumination of the banners 14 and 15 of the information board 17.

The first 10 and the second 21 groups of elements And perform the functions of key elements when reading the contents of the first 20 and second 11 counters.

The second counter 11 is designed to count the number of attempts that were required by the operator to train in the EXERCISE step, before the first timely execution of the algorithm and transferring it to the TRAINING step.

The decoder 12 converts the binary code of the contents of the first counter 11 to decimal to display to the student on the display 16 of the information board 17

the number of the attempt at which it is transferred to the TRAINING stage.

The second element OR 13 combines the external launch input 27 of the device, the second output of the first block 6 and the first output

0 of the second comparison unit 22 to return the learner to a new attempt in the event of an error or delay in completing the current attempt to work out the control algorithm. Banners

5 14 EXERCISE and 15 TRAINING show the operator the current stage of his practical training, which is especially important when it is automatically transferred from stage to stage.

0 Indicator 16 represents the student simultaneously with the transfer to another stage, the number of the attempt at which he performed the algorithm in a timely manner.

Panel 4, transparencies 14, 15 and indi5 kator 16 are combined into a display board 17, for which the display screen can be used for automated practical training of operators. A clock pulse generator 18 serves to convert an operator’s operating time into a binary numeric code expressed by the number of pulses generated by the generator. The required accuracy of measurement of time intervals depends on

5 clock frequency. The signal at the first input starts the generator 18, and at the second it stops.

The second delay element 19 synchronizes the order of reading the contents.

0 register 24 and the first counter 20, which counts the number of generated generators 18 pulses, i.e. time

The third delay element 23 synchronizes the operation of the second block 22

5 comparisons, in which the value of the required (permissible) and actual time is compared, i.e. the contents of the register 24 and the first counter 20.

The third element OR 25 combines inputs for resetting the first counter 20 in the following cases: switching on the device; making a mistake by the student and exceeding the allowable time for performing the control task.

5 The external inputs 26 are used for the initial recording in the register 24 of the time code allocated by the learner to the error-free execution of the algorithm.

The device operates as follows.

With the inclusion of the device, i.e. With the appearance of a signal at external input 27, it arrives at the installation inputs of counters 11 and 20, wrapped them, at the S input of the 9G trigger, a signal from the direct output of which will illuminate the banner 14 EXERCISE of the information board 17, and at the input of the second element OR 13. From the output of this element, the signal goes to the counting input of the counter 11, writing 1 to it, and to the first input of the register 1 of the address, where the address code of the microcommand corresponding to the first operation of the control algorithm is selected. This code enters microprogram memory block 2, and the selected micro-command is written to micro-command register 3, In addition, the signal from the first output of register 3 goes to the first input of the generator 18 and starts it, to the counter 20 the sequence of generated pulses begins to arrive. to count them. From the register 3, according to the first outputs, the code of the organs enters the panel 4 of the display organs, which changes its state in this operation of the algorithm. The operator, perceiving this information, acts on the corresponding unit of unit 5. The code of this unit goes to the first inputs of the first comparison unit 6 and through the first element OR 8 to the control input of register 3 microcommands, then the code of the required control from the second zone register 3 microcommands are fed to the second inputs to block b of the comparison. The signal from the output of the first element OR 8 through the first element 7 of the delay is fed to the control input of the comparator unit 6, where the operator makes an assessment of the error-free operation of the operator.

If the operator is recognized to be erroneous, i.e. mismatch codes in the first block 6 of the comparison, the signal from its second output is fed through the third element OR 25 to the installation input of the counter 20 to zero it, as well as to the input of the second element OR 13. From the output of the element 13, the signal goes to the counting input of the counter 11, increasing its contents are one, and the first input of the register is 1 address. This command selects the code of the microcommand address corresponding to the first operation of the algorithm, which corresponds to the beginning of the new attempt by the students to perform the controls in a timely and error-free manner.

In case of incoming codes, the operation is recognized as completed without error, and the signal from the first output of the first comparison unit 6 goes to the second input of the address register 1, where it is shifted to the right to the next cell and the address of the microcommand corresponding to the next control algorithm is selected. The device operates in the order described before the last operation of the algorithm. After an error-free completion of the algorithm, the signal from the output of the last cell of the register 1 of the micro-command address is fed to the second input of the generator 18, stopped, and simultaneously through the second delay element 19 to the register 24, to the third delay element 23 and to the second inputs of the second group of elements 21. The elements 21 will be opened, and the contents of the counter 20, as well as the register 24 will go to the second and first inputs of the second comparison unit 22, respectively. The signal delayed by the third delay element 23 will go to the control input of the second block 22, where the allowable execution time of the algorithm will be compared with the actual time spent.

In the event that the elapsed time is longer than the allotted time, the signal appears at the first output of the second comparison unit 22 and goes through the third element OR 25 to the installation input of the counter 20, wrapped it, and also to the input of the second element OR 13. From the output of this element the signal is fed to the counting input of counter 11, the contents of which will increase by one and reach two, as well as to the first input of register 1 of the microcommand address, which will lead to the choice of the address of the first operation of the algorithm, i.e. A new student attempt. In this case, the state of the information boards (14-16) will not change, i.e. The EXERCISE mode will remain.

If the elapsed time has not exceeded the allowable one, the signal goes to the second output of the second comparison unit 22 and goes to the R-input of the trigger 9. The signal goes to its inverse output and lights up the 15 TRAINING banner, simultaneously turning off the banner 14 EXERCISE of the information board 17. In addition The signal from the second output of the second comparison unit 22 is fed to the first inputs of the first group I 10, which will open the output of the counter 11. Its contents, i.e. the number of the attempt, or rather its binary code, in which the student switched to the new preparation mode, through the decoder 12 is presented to the operator using the indicator 16 of the board 17.

Claims (1)

An apparatus for training operators, comprising a response input block, two OR elements, a delay element, a first comparison block, a scoreboard, a first counter, a first group of AND elements, a decoder, a microcommand address register, a memory block, a microcommand register, and a trigger, S - whose input is connected to the installation input of the first counter and the first input of the first OR element, the first input of which is the device input, the second input is connected to the first output of the first comparison unit, and the output is connected to the counting input p The first counter and the control input of the microcommand address register, whose shift input is connected to the second input of the first comparison unit, and the outputs are connected to the address inputs of the microcommand memory block, the outputs of which are connected to the information inputs of the microcommand register, the control input of which is connected to the output of the second element OR, the outputs of the first group are connected to the first group of information inputs of the board, and the outputs of the second group are connected to the inputs of the first group of the first comparison unit, the inputs of the second group of which are are united with the outputs of the response input block and the inputs of the second OR element, whose output is connected via a delay element to the control input of the first comparison block, the outputs of the first counter are connected to the first inputs of the AND elements of the first group, the outputs of which are connected to the decoder inputs, which outputs are connected to information inputs of the second group of boards, the first and second inputs of which are connected to the trigger outputs, characterized in that In order to expand the didactic capabilities of the device, the second group of elements AND, the second and third delay elements, the third element OR, the second counter, the second comparison block, the pulse generator and the data register, whose outputs are connected to the inputs of the first group of the second comparison block, are entered into it. the second group of which is connected to the outputs of the elements AND the second group, the first inputs of which are connected to the outputs of the second counter, the installation input of which is connected to the output of the third element OR, the first input of which is connected The second input is connected to the first input of the first OR element, and the third input is connected to the third input of the first OR element and the first output of the second comparison unit, the second output of which is connected to the R input of the trigger and the second inputs of the AND first element. group, one output register address microcommand connected to the start input of the pulse generator, and the other output is connected to the stop input of the pulse generator and through the second delay element connected to the second inputs of the elements And the second group, ravl yuschemu input data and the delay element input of the third register, whose output is connected to the control input of the second comparator unit, the inputs of the data register are input group device.