SU1711220A1 - Device for training operators - Google Patents

Abstract

The invention relates to the technical means of training operators and can be used in simulators for training control system operators. The aim of the invention is to expand the didactic capabilities of the device. The goal is achieved by those. that the device for training operators additionally contains two groups of AND elements, an OR element and a second counter. The proposed device has enhanced didactic possibilities and allows to increase the efficiency of operator training due to a reliable qualitative assessment of the timeliness of its actions in each training and its quantitative confirmation by presenting its results to the operator and the results of groups of the best, average, worst predecessors of the same algorithm training. same training, which increases the level of motivation of the student. 1 il.

Description

The invention relates to the technical means of training operators and can. be used in simulators to train control system operators.

The purpose of the invention is to expand the didactic capabilities of the device,

The drawing shows a functional diagram of the device for training operators.

The device contains micro-command address register 1, microprogram memory block 2, micro-command register 3, operator response input block 4, comparison block 5, item OR 6. external input 7, delay element 8, delay element 9, pulse generator 10, counter 11 , block 12 of the memory of learning results, block 13 of comparison, block AND decoders, element OR 15, block 16 of displaying information, counter 17, first group 18-20 of elements AND, second group 21 elements I.

Register 1 of the microcommand address is intended to specify the control component of the algorithm for performing the control task. It contains as many cells as elementary operations includes an activity algorithm. When a signal appears at the first input of register 1, the microcommand address is selected in block 2 of the microprogram memory corresponding to the first operation of the algorithm. With the arrival of a signal at the second input of register 1, a shift occurs to its next cell and reading the address of the microcommand corresponding to the next operation of the control algorithm. The outputs of register 1 are connected to the inputs of microprogram memory unit 2, the output of the first cell of register 1 being connected to the start input, and the output of the last cell to the input of the generator 10.

The microprogram memory unit 2 is intended for storing microscopic type data.

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WITH

Mand for each operation of the algorithm on the active organs of the information display unit 1B and the 4 panels of controls. The number of microprograms of the microprogram corresponds to the number of operations of the control algorithm. The outputs of block 2 of the firmware memory are connected to the inputs of register 3 microcommands.

Micro-command register 3 contains data about the current operation of the algorithm of activity and consists of two zones for micro-operations: the first zone is for storing the organ code of the information display unit 16, which replaces its state in this algorithm operation, the second zone is for the organ code panels and controls, on which the operator is required to act in the same operation of the control algorithm.

. Unit 4, together with a group of display units of unit 16, is the physical model of the operator’s console of a real automated control system designed to control objects.

Comparison unit 5 is designed to assess the accuracy of the operator's actions by comparing the codes received at his first and second inputs, i.e. involved and required controls respectively.

The OR 6 element combines the external and internal start inputs of the device for training operators, and its output is connected to the first input of register 1 of the micro-command address, to the installation input of the first counter 11, and to the counting input of the second counter 17.

Position 7 marks the external launch input of the device, it is connected, except for the first element OR 6, to the installation input of the second counter 17.

The delay element 8 serves to synchronize the operation of the comparison unit 13.

The delay element 9 makes it possible to synchronize the moments of arrival at the inputs of the block 13 of the comparison of the corresponding codes.

The pulse generator 10 is designed to convert the operator’s operating time into a binary numerical code, expressed by the number of generator pulses. The signal at the first input of the generator 10 starts, and at the second input it stops.

The memory unit 12 is designed to store statistically reliable data on the time spent on the execution of the algorithm by groups of best, average, and worst operators. in the first, second, etc. workouts. The initial data for storage in memory block 12 is taken from the results of mastering this algorithm by groups of predecessor operators. Codes of time spent by the specified groups

operators are rewritten into block 13 of the comparison according to the signal at the control input of block 12, which appears from the last output of register 1 of the microcommand address. The selection of data in memory block 12 in accordance with the number of the current workout is made using the group of control inputs of block 12 connected to the fifth outputs of block 14 of decoders.

Comparison unit 13 is used for a quantitative assessment of the quality of timeliness of actions of the training operator. Block 13 contains three comparison nodes. The first inputs of block 13 receive the time code (T5), spent in this training by the best, the second inputs - time code (T4), spent by the average, and the third inputs - the time code (T), spent by the worst previously trained groups. In groups of fourth, fifth and sixth

5 inputs of block 13 receives a time code (T °); spent by the training operator. The comparison of the codes in block 13 starts at a signal at its control input, which is associated with the output of the first element 8

0 delay, and is performed in the following sequence: g T5 T4; T ° T3 and finally T ° T3. The operator is given one of the possible ratings corresponding to the results of the match,

5 is excellent - the first output of block 13 is activated. Well - the second exit, satisfactory - the third and unsatisfactory - the fourth exit. These outputs are associated with the second group of inputs of block 16.

0 information displays for presenting quality results to the operator; his training activities. The set input of the comparison unit 13 is associated with the output of the element OR 15,

5 Block 14 of decoders is designed to convert the binary time code spent by groups of the best, average, worst and training operator who previously mastered this algorithm into a decimal code for displaying this information to the operator using the display elements of the information display unit 16.

The element OR 15 is designed to set the illumination of the display organs of the information display unit 16, bring the comparison unit 13 to the initial state and prepare the entire operator training device for a new training session.

The information display unit 16 is used to present information to the operator: on the progress of the control process — a group of first inputs of the block 16; about the assessment received - a group of second inputs; about the time spent in this training by previously trained groups of worst, medium and best operators - a group of third, fourth and fifth inputs of block 16; the information on the time spent by the training operator is the sixth inputs of the block and, finally, the information on the number of the current workout is the seventh inputs of the block 16 of the information representation.

Counter 17 is used to count the number of workouts and the corresponding correction of the initial data: 5, T4 and T3 when comparing. them in block 13 to determine the evaluation of the training operator.

The device operates in the following way.

When the device is turned on, the signal enters its input 7, which is the first input of the first element OR 6 ". The signal from the external input goes to the installation input of the counter 17 and zeroes it. From the output of the element OR 6, the signal is fed to the installation input of the counter 11, to the counting input of the counter 17 and to the input of the register 1 of the microcommand address. Register 1 selects the address code of the microcommand corresponding to the first operation of the control algorithm. This code goes to block 2 of the microprogram memory, and the selected micro-command is rewritten into register 3 of the micro-command. In addition, the signal from the first cell of the register 1 is fed to the first input of the generator, the rator 10 and starts it, and the counter 11 begins to count the number of generated pulses. From the register 3 micro-instructions, the first output of the group of the first inputs of the information display unit 16 receives the code of the display unit, which changes its state in this operation of the algorithm.

The human operator, perceiving this information, acts on the corresponding organ of block 4. The code of this organ enters the first inputs of comparison unit 5, the second inputs of which receive the contents of the second micro-operation, i.e. the code required for the operation of the organ (control) of block 4. In case of a mismatch of the codes received in block 5, no signal will be output at its output, the operation will be considered completed with an error, while the execution time of the algorithm continues to be counted. When the codes coincide, the signal is shown at the output of the comparison unit 5, since the operation is recognized

made unmistakably. This signal arrives at the second input of register 1 of the address, where the shift to the right to the next cell is made and the address of the micro-command is selected, 5 corresponding to the next regular operation of the control algorithm.

The device operates in the order previously described before the last operation of the algorithm. In this case, the signal with. output

0 the last cell of the register 1 of the micro-command address is fed to the second input of the generator 10 and stops it at the control input of the learning results memory unit 12 and at the inputs of elements 8 and 9

5 delays. From block 12 of the memory of results, the time codes spent on the execution of this algorithm in the first training are supplied to the groups of the first, second and third inputs of the comparison block 13.

0 the best, average and worst groups of predecessor operators.

The signal from the output of the delay element 9 is fed to the second inputs of the elements AND 18-21, the contents of the counter 1.1 is fed to

5 is a fourth group of inputs of a block of 14 decoders and into groups of fourth, fifth and sixth inputs of a block 13 of comparison.

The check of the matching of the codes begins after the arrival of the signal at the control input of the output unit 13c of the delay element 8 and is carried out in the following order. The time code spent by the training operator (T °) is compared with the time code spent on this algorithm in the first training session by the best (T5) operators. If T ° T, then the signal appears at the first output of comparison unit 13 and is fed to the corresponding input of the second

0 groups of block 16 for displaying Ј an excellent assessment to the student. Otherwise, i.e. T ° T5, a comparison is made of the results of the average operators (T4) with the results of the training operator, If

5 T T4, then the operator is given and displayed a good estimate due to the occurrence of a signal at the second output of the comparator unit 13. In case T is T, then the results of the student are compared with the results of the worst operators, i.e. T T When this condition is fulfilled, the signal is shown at the third output of the comparison unit 13 and the student will be given a satisfactory assessment.

5 And finally, in the case of T ° T3, the operator is given an unsatisfactory rating, which is displayed with the help of block 16 due to the signal from the fourth output of block 13 of comparison. Outputs of block 13.

The comparisons constitute the second group of inputs of the information display unit 16, with the help of which the operator is presented with: his estimate, time spent on the execution of this algorithm: worst, average and best groups of operators.

The outputs of the comparison unit 13 are combined with the second element OR 15, the signal from the output of which brings the blocks 13 and 16 to a similar state and prepares the device for the next training session. So the signal goes to the second input of the element OR b, from the output of which it passes to the installation input of the first satellite 11 and embraces it, as well as to the counting input of the counter 17, increasing its content by one. From the output of the counter 17, the code of the workout number goes to the group of inputs of the block 14 of decoders, and from the group of outputs the signal goes to the group of inputs of the memory block 12, thereby selecting data for comparison in the second training session.

For the rest, the operation cycle of the device is repeated in the order described.

Claims (1)

Invention Formula A device for training operators containing a microprogram memory unit whose outputs are connected to the corresponding inputs of the micro-register register, and inputs are connected to the corresponding outputs of the micro-command address register whose first output is connected to the pulse generator stop input, the first delay element input and the memory block read input learning results and through the second delay element is connected to the control input of the first comparison unit, and the second output is connected to the start input of the pulse generator, d which is connected to the counting input of the first counter, the outputs of the first group microinstruction register connected to inputs of the first group of display unit information, and the outputs of the second group - with the information inputs of the first group of the second comparison unit, the information inputs of the second group of which connected to the outputs of the operator response input block, and the output is connected to the information input of the microcommand address register, the outputs of the learning results memory block are connected to information inputs of the first group of the first comparison unit, the outputs of which are connected to the inputs of the first OR element and information inputs of the second group of the information display unit, the information inputs of the third group of which are connected to the outputs of the first group of the decoder unit, and the control input with the output of the first IL element, characterized by the fact that expanding the didactic capabilities of the device, two groups of AND elements are introduced into it, the second OR element and the second counter, the outputs of which are connected to the inputs of the first group of the decoder unit, the setup input is with the first input of the second OR element and is the device input, the counting input is with the installation input of the first counter, the installation input of the microcommand address register and the output of the second element OR, the second input of which is connected to the output of the first element OR, the first inputs of the elements AND of the first and second groups are connected to the output of the first delay element, and the outputs connected respectively to the inputs of the second group of the decoder unit, the outputs of the second group of which are connected to the inputs of the fourth group of the information display unit and the address inputs of the unit memory learning results, the outputs of which are connected respectively to the second inputs of the elements And the first group, the second inputs of the elements And the second group are connected respectively to the outputs the first counter.