RU2248610C2 - Device for controlling knowledge quality estimation process in remote education system - Google Patents

Abstract

FIELD: computers.

SUBSTANCE: device has registers, comparators, signs input block, counters, adder, decoder, memory block, means for determining support test address, triggers, AND elements, groups of AND elements, OR elements, delay elements.

EFFECT: higher precision.

4 dwg

Description

The invention relates to computing, in particular to devices for controlling the receipt of an assessment of the quality of knowledge in a distance learning system, and can be used to control the knowledge of students.

Known devices that could be used to solve the problem [1, 2].

The first known device comprises a computing unit connected to functional input and logical processing input units, the outputs of which are connected to a memory unit, a display unit connected to the computing unit and to the decision unit [1].

A significant drawback of this device is its limited functionality, due to the fact that the description of input situations during training and quality control of knowledge is possible only in the space of a limited number of signs, which leads to low efficiency of its use.

Another device is known that contains memory blocks, comparators, counters, registers, triggers, groups of AND, OR elements, delay elements [2].

The last of the above technical solutions is closest to the described.

Its disadvantage is its low accuracy, due to the lack of the ability to control knowledge using the multicriteria parameters used to describe input situations in the space of functional features.

The purpose of the invention is to improve the accuracy of the device by using multicriteria parameters to identify and correct errors.

This goal is achieved in that in the device containing the first register, the information input of which is the first information input of the device, and the synchronizing input is the first synchronizing input of the device, the second register, the information input of which is connected to the output of the memory block, which is the first information output of the device, is the third register, the information input of which is the second information input of the device, the synchronizing input is the second synchronizing input of the device, and the output connected to one input of the first comparator, the other input of which is connected to the output of the second register, and the outputs are connected to one of the inputs of the first and second elements And, accordingly, the second comparator, one input of which is connected to the output of the first counter, and the outputs are connected to one of the inputs of the third and fourth AND elements, respectively, the first OR element, one input of which is connected to the output of the third AND element, and the output of the first OR element is connected to the input of the first delay element, the output of which is connected to the input of the second the delay ment, the output of which is connected to the reading input of the memory unit and to the input of the third delay element, the pulse from the third element And goes to the counting input of the first counter, the clock pulse from the fourth element And goes to the installation input of the first counter, the clock synchronizing pulse delayed by the fourth delay element while the code is being written to the third register, the output of the fifth delay element receives the first and second elements AND, the first trigger, the single input of which is the first control input devices, the second OR element, one input of which is the second control input of the device, and the output is connected to the installation input of the first trigger, the fourth delay element, the input of which is connected to the second synchronizing input of the device, and the output is connected to the synchronizing input of the first comparator, while the synchronizing pulse , delayed by the fourth delay element for the time the code is written in the third register, comes from the output of the fifth delay element to the first and second elements AND, the second trigger, a single input cat The first one is connected to the output of the second AND element connected to the counting input of the second counter, the first group of And elements, one of whose inputs are connected to the output of the fourth And element, the second group of And elements, one of which inputs are connected to the outputs of the second register, the third OR element, one input which is connected to the output of the first element And, the fifth and sixth elements And, one of whose inputs are connected to a single output of the first trigger, the seventh element And, one input of which is connected to the inverse output of the first trigger, synchronizing imp ls from the fourth element And goes to the synchronizing output of the device as a signal about the end of the presentation of test tasks, the output of the third delay element receives a synchronizing pulse to the input of the fourth element And to the input of the second register, the signal “True” from the fifth appears on the first signal output of the device AND element, the correct answer code from the second group of AND elements is displayed on the display screen, from the sixth AND element, an impulse is sent to the second signal output of the device as an “Error” signal, a synchronizing pulse from the fourth element AND arrives at the installation input of the second counter and the second element OR, the determinant of the test reference address is entered, the information input of which is connected to the output of the first register, the synchronization input is connected to the first synchronizing input of the device, the information output is connected to another input of the second comparator, and the synchronizing output is connected to another input of the first OR element, an adder, one information input of which is connected to the information output, determine For the reference address of the test, another information input is connected to the output of the first counter, the synchronization input is connected to the output of the first delay element, the installation input is connected to the output of the fourth element And, and the output of the adder is connected to the address output of the memory unit, the decoder whose input is connected to the output of the second counter, and the outputs are connected to other inputs of the AND elements of the first group, while the other input of the fifth AND element is connected to the output of the first AND element, the other input of the sixth AND element is connected to the output of the second element And, the other inputs of the elements AND of the second group are connected to the unit outputs of the first and second triggers, the other input of the seventh element And is connected to the output of the second element And, and the output of the seventh element And is connected to another input of the third element OR, the output of which is connected to another input of the third of the And element, from the outputs of the And elements of the first group, the “Estimates” signal is issued to the second information outputs of the device.

The invention is illustrated by drawings, in which Fig. 1 shows a block diagram of a device, Fig. 2 shows an example of a particular structural embodiment of a test reference address determinant, Fig. 3 shows a structure of a code message representation of a test reference address determinant, and Fig. 4 shows a structure code messages stored in the device’s memory block.

The device (figure 1) contains the first 1, second 2 and third 3 registers, first 4 and second 5 comparators, first 6 and second 7 counters, adder 8, decoder 9, memory unit 10, determinant 11 of the test reference address, the first 12 and second 13 triggers, first 14, second 15, third 16, fourth 17, fifth 18, sixth 19 and seventh 20 AND elements, first 21-23 and second 24 groups of AND elements, first 25, second 26 and third 27 OR elements, first 28, second 29, third 30, fourth 31 and fifth 32 delay elements.

1 also shows the first 33 and second 34 information inputs of the device, the first 35 and second 36 clock inputs of the device, the first 37 and second 38 control inputs of the device, as well as the first 39, second 40, third 41 information outputs of the device, the first 42 and a second 43 signal outputs and a synchronizing 44 output.

The determinant 11 of the reference address of the test (Fig. 2) contains a decoder 45, a memory unit 46, made in the form of read-only memory, register 47, elements 48 to 50 AND, elements 51 and 52 of the delay. The drawing also shows the synchronizing input of the determinant 33, the information input 53, the information output 54 and the synchronizing output 55.

All nodes and elements of the device are made on standard potential-pulse elements.

The basis of the device for obtaining an assessment of knowledge is the task for self-monitoring and control, implemented in these two different modes of operation. The methodology for constructing tests (i.e., a series of test tasks) for self-monitoring and control of mastering the knowledge of students in any subject area is generally similar. However, there are differences. So, the direct and only purpose of control tests is to check the assimilation of knowledge in the discipline under study, while tasks for self-control include training elements, because in this case, the correct answers are reported during the control [3].

Based on this, the requirements for the correctness of the compilation of control tests are more stringent, since the studied level of knowledge should be adequately reflected by some quantitative indicators. In order for the prepared tests to really make it possible to assess the degree of assimilation of educational material, they must be compiled in accordance with the specific requirements of the classical theory of testing [4].

The device operates as follows.

The client workplace of knowledge control consists of a terminal having a screen for playing test tasks, examples of which are given in the mentioned source [3], and a keyboard of a personal computer. Management of knowledge control in the distance learning system is carried out from a server (not shown).

Before the start of the next cycle of work, the code of the test number is written to the register 1 from the server, the tasks of which must be presented to control knowledge. To do this, the server gives an input code 33 to the test number code, which is entered into register 1 by the server clock signal received at input 35.

In addition, one of two device operation modes is set from the server: control mode or self-control mode, implemented using trigger 12 controlled from inputs 35 and 36. If trigger 12 is in the initial (“zero”) state, then it implements control mode , in which it blocks the chain of issuing "tips" through the elements 18, 19 and 24 I. If the trigger 12 is transferred to a single state, this will mean the device is in self-monitoring mode. At the same time, elements 18, 19 and 24 And will be open for issuing prompts on the display screen with a high potential from a single trigger output.

The code of the test number from the output of register 1 goes to the input 53 of the determinant 11 of the test reference address, from where it is fed to the input of the decoder 45 (see Fig. 2), which decrypts this code and one of its outputs generates a high potential that opens one of the corresponding elements 48-50 I.

In parallel, the server clock signal from the input 35 is delayed by the delay element 51 (for the duration of the decoder 45 operation and the code is installed on the address input of the read-only memory 46) and from the output of the delay element 51, having passed through one of the 48-50 AND elements open at the second input , is fed to the read input of a fixed memory cell of read-only memory 46.

In a fixed cell of this memory block, a code message is stored, the structure of which is shown in Fig. 3, where the initial address of the first test task is stored in the first K1 digits, and the total number of tasks in this test is stored in the second K2 digits.

The contents of the fixed cell of the ROM 46 are read into the input of the register 47, where it is entered by the synchronizing pulse coming from the output of the delay element 52 to the synchronizing input of the register 47. The contents of the first K1-bits from the output of the register 47 through the output 54 of the determinant 11 goes to one of the inputs of the adder 8, and the contents of the second K2-bits on one input of the comparator 5.

The synchronizing pulse from the output of the delay element 52 after entering the code in the register 47 through the output 55 of the determinant 11 passes through the element 25 OR to the input of the delay element 28, where it is delayed by the response time of the register 47 and setting the code at the input of the adder 8. Considering that at this point counter 6, the output of which is connected to another input of the adder 8, is in the initial “zeroed” state, then at one input of the adder there will be the contents of K1-bits, and at the second input a code corresponding to a zero value.

The synchronizing pulse supplied to the synchronizing input of the adder 8 from the output of the delay element 28, at the output of the adder 8 will be fixed the starting address of the first test task, which should be displayed on the display screen. The same pulse delayed by the delay element 29 during transients in the adder 8, is fed to the read input of the memory unit 10 and reads the contents of the initial address to the output of the unit 10.

The structure of the readable code message is presented in figure 4, where the first K3-bits allocated for the test task, and the second K4-bits contain the code of the correct answer.

After reading the first K3-bits in the form of a test task are displayed on the display screen through the output 39 of the device, and the second K4-bits containing the correct answer code are fed to the information input of register 2, where they are entered by the synchronizing pulse from the output of the delay element 30 (delaying the incoming an impulse to its input during the reading of the code from the memory unit and its installation at the inputs of the register 2).

According to the classical theory of testing [4], the optimal number (4-6) of answer options should have only one correct answer and this answer will be in register 2.

The student of the proposed answer chooses the one that he considers preferable, and types on the keyboard the corresponding sign or symbol. The response code is fed to the information input 34 of register 3, where it is entered by a synchronizing pulse from input 36.

At the same time, the same clock from input 36 is delayed by a delay element 31 while the code is being written to register 3 and then fed to the synchronizing input of the comparator 4, the information inputs of which are sent to the codes of registers 2 and 3. If the codes of the registers match, then the direct output the comparator 4 will be a high potential, which will open the element 14 And, to the other input of which a synchronizing pulse is received from the output of the delay element 32, delayed by the time the comparator is activated.

The pulse from the output of the delay element 32 passes element 14 And and then goes, firstly, to the input of the element 18 And, open at the second input by trigger 12 in the self-monitoring mode. As a result, the signal “True” appears on the signal output of the device 42.

Secondly, the pulse from the output of element 14 AND through element 27 OR enters one input of element 16 AND, the state of which is determined by the potential from the inverse output of comparator 5. Given the fact that there will be a code on one input of the comparator that fixes the number of tasks in the test, and on the other - counter code 6, currently corresponding to a zero value, then the direct output of the comparator 5 will have a low potential, and on the inverse - a high, supporting element 16 AND in the open state.

As a result, the pulse from the output of the OR element 27 passes through the element 16 AND and then goes both to the counting input of the counter 6, increasing its readings by one, and through the OR element 25 and the delay element 28 to the synchronizing input of the adder 8, fixing the fact of increasing the code by address input of the memory block per unit.

Next, the following test task and the corresponding code of the correct answer are read into the register 2 in the manner described above.

If, in the process of selecting the answer to the next test task, the wrong answer is entered into register 3, then this fact will be fixed by comparator 4, by issuing a high potential at its inverse output. As a result of this, the element 14 And will be closed, and the element 15 And is open. The pulse from the output of delay element 32 passes through element 15 AND and, firstly, arrives at the single input of trigger 13, which fixes the fact of error and opens elements 24 I through one input. The trigger 13 is returned to its initial state by the initial setting signal from the device control panel (not shown) before typing the correct answer.

Secondly, it will pass through element 19 AND, opened by the high potential of trigger 12 in self-monitoring mode, to output 43 as a “Error” signal. Considering that in the self-control mode, trigger 12 also opens the 24 And elements on the second input, then from the output of register 2 the correct answer code through the 20 And elements will be displayed on the display screen in the form of “Correct answer” information.

Thirdly, the pulse from the output of the element 15 And enters the counting input of the counter 7, counting the number of errors. The readings of the counter 7 go to the input of the decoder 9, which, depending on the readings of the counter, opens one of the elements 21-23 I. The outputs of the corresponding elements 21-23 And are matched with possible knowledge assessments that are issued to the outputs 40.

Fourth, the same pulse is fed to one input of the 20 And element, the state of which is determined by the potential from the inverse output of the trigger 12. If at the moment the trigger 12 is in self-monitoring mode, then the low potential from the inverse output of the trigger 12 will be closed and the continuation of the cycle of presenting the next test task is possible only after re-entering the now correct prompted answer in register 3.

In this case, the comparator 4 will record the fact of comparing the codes of the registers 2 and 3 and with a high potential will open the element 14 AND, through which the synchronizing pulse from the output of the delay element 32 passes through the element 27 OR and element 16 And both to the counting input of the counter 6 and through the element 25 OR and a delay element 28 to the synchronizing input of the adder 8. Next, the next test task and the corresponding code of the correct answer are recorded in register 2 as described above.

If trigger 12 was in the initial state, which corresponds to the device operating mode in the control mode, then the high potential from the inverse output will open the 20 AND element and the pulse from the output of the 15 And element will go through the 20 AND element, the 27 OR element, the 16 AND element then to the counting input of the counter 6 and through the OR element 25 and the delay element 28 to the synchronizing input of the adder 8.

The described process will continue until the comparator fixes the equality of codes in register 47 of determinant 11 and counter 6. As soon as comparator 5 fixes the equality of codes of counter 6 and register 47, a high potential will appear at the direct output of the comparator, which opens up one input element 17 And, to the other input of which a synchronizing pulse is received from the output of the delay element 30. A synchronizing pulse passes through element 17 And and arrives, firstly, as output 44 as a signal to the server about the end of presentation test tasks, and to the installation inputs of the counter 6 and adder 8, returning them to their original state.

Secondly, the same pulse arrives at the inputs of elements 21-23 And and passes to the output of one of them, which will be opened by the corresponding output of the decoder 9, which determines the type of assessment that the tested student deserves according to the results of work.

Thirdly, the same pulse is supplied to the installation input of the counter 7 and through the OR element 26 to the installation input of the trigger 12, setting it to its initial state, which corresponds to the knowledge control mode.

Thus, the introduction of new nodes and constructive relationships has significantly improved the accuracy of assessing the knowledge of students in all sections of the studied subject areas.

Sources of information

1. Japanese Published Application No. 60-19540, cl. G 06 F 15/16, 1985.

2. Description to the copyright certificate No. 1550528, class. G 06 F 15/20, 15/40, 1990 (prototype).

3. Romanov A.N. et al. Distance learning technology in the system of correspondence economic education. - M.: UNITY-DANA, 2000.

4. Kline P. Reference design test. Kiev: PAN-LTD, 1994.

Claims (1)

A device for controlling the receipt of an assessment of the quality of knowledge in a distance learning system containing a first register, the information input of which is the first information input of the device, and the synchronizing input is the first synchronizing input of the device, the second register, the information input of which is connected to the output of the memory block, which is the first information output device, the third register, the information input of which is the second information input of the device, the synchronizing input is the second the device’s synchronizing input, and the output is connected to one input of the first comparator, the other input of which is connected to the output of the second register, and the outputs are connected to one of the inputs of the first and second elements And, accordingly, the second comparator, one input of which is connected to the output of the first counter, and the outputs are connected to one of the inputs of the third and fourth AND elements, respectively, the first OR element, one input of which is connected to the output of the third AND element, and the output of the first OR element is connected to the input of the first delay element, the output of which is connected to the input of the second delay element, the output of which is connected to the reading input of the memory unit and the input of the third delay element, the pulse from the third element And goes to the counting input of the first counter, the clock pulse from the fourth element And goes to the installation input of the first counter, the first a trigger, a single input of which is the first control input of the device, a second OR element, one input of which is the second control input of the device, and the output is connected to the installation input the first trigger, the fourth delay element, the input of which is connected to the second synchronizing input of the device, and the output is connected to the synchronizing input of the first comparator, while the synchronizing pulse delayed by the fourth delay element for the time the code is written to the third register comes from the output of the fifth delay element to the first and the second element And, the second trigger, a single input of which is connected to the output of the second element And, connected to the counting input of the second counter, the first group of elements And, one of which inputs connected to the output of the fourth AND element, the second group of AND elements, one input of which is connected to the outputs of the second register, the third OR element, one input of which is connected to the output of the first AND element, the fifth and sixth AND elements, one of whose inputs are connected to the unit output of the first trigger , the seventh element And, one input of which is connected to the inverse output of the first trigger, the synchronizing pulse from the fourth element And goes to the synchronizing output of the device as a signal about the end of the presentation of test d, the output of the third delay element receives a synchronizing pulse to the input of the fourth element And to the input of the second register, the signal “True” from the fifth element And appears on the first signal output of the device, the correct answer code from the second group of elements And is displayed on the display screen, with of the sixth element AND, a pulse is supplied to the second signal output of the device as a “Error” signal, the clock pulse from the fourth element AND is supplied to the installation input of the second counter and the second OR element, characterized in that it contains a determinant of the test reference address, the information input of which is connected to the output of the first register, the synchronization input is connected to the first synchronization input of the device, the information output is connected to the other input of the second comparator, and the synchronization output is connected to the other input of the first OR element, adder, one the information input of which is connected to the information output of the determinant of the test reference address, another information input is connected to the output of the first counter, synchronizing d is connected to the output of the first delay element, the installation input is connected to the output of the fourth AND element, and the adder output is connected to the address output of the memory block, a decoder whose input is connected to the output of the second counter, and the outputs are connected to other inputs of the AND elements of the first group, while another input of the fifth element And is connected to the output of the first element And, another input of the sixth element And is connected to the output of the second element And, other inputs of the elements And of the second group are connected to the unit outputs of the first and second triggers, d the other input of the seventh AND element is connected to the output of the second AND element, and the output of the seventh AND element is connected to another input of the third OR element, the output of which is connected to another input of the third AND element, from the outputs of the AND elements of the first group the “Estimates” signal is issued to the second information outputs devices.

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