RU2315364C1 - System for remote teaching of students - Google Patents

Abstract

FIELD: computer engineering, in particular, remote training system, used for teaching students.

SUBSTANCE: system contains five registers, block for selecting base address of training test, block for checking completion of test tasks, block for determining correctness of trainee response, block for generating test reading signals, block for evaluating trainee responses, block for selecting base address of control test, block for selecting address of time period, adder, comparison block, block for counting number of transactions.

EFFECT: increased speed of system operation due to prevented search of data of control test of trainees across whole volume of server database and localization of search only across support addresses of database, corresponding to given parameters of control test.

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Description

The invention relates to computer technology, in particular to a distance learning system for students based on the use of new information technologies in the learning process.

As a rule, any educational course contains a significant array of theoretical content, divided into so-called "frames", that is, individual pieces of information for this course, compiled according to a certain technique. In addition, the educational course of higher education also includes some interactive array in the form of tests and practical tasks, which are offered at the end of the sections of the course.

Studies by Alan Carter and Colston Senger [4] showed that a person, mastering some new discipline, most often perceives the knowledge presented in the form of knowledge packages, otherwise ideoplasts (from the English Idea - idea, concept and [plast] ic - flexible, plastic).

Ideoplasts are a persistent individual concept of a person about a particular fragment of knowledge, which he considers to be true. A person uses each ideoplast as a definite axiom, the “black box”, rarely delving into its essence. So, for example, trigonometric relationships or other mathematical formulas that are perceived by a person as uniquely true and that can be immediately used in practice are a classic example of ideoplasts. Human thinking can be conditionally reduced to a combination of ideoplasts and the formation of new ones, and therefore the main task of any training is to give the student a basic set of ideoplasts and teach him to independently form new ones.

The most important element in this case is the creation of a common distance learning format that takes into account all the features of distance learning and an individual approach to each student. You can get such a model by creating scripts (styles) that would turn the training modules to a specific general view, having the following architecture:

- a diagram of the type (form) of the document;

- a set of documents of this type;

- Letters of DSSSL styles that would specify the transformation.

A similar architecture offers a modern, more advanced in terms of capabilities and flexibility XML architecture. It is this architecture that is used as the basis for the design of courses.

When creating distance learning courses, each frame (the frame will be considered the smallest part of the distance learning course, not taking into account the similar concept in the markup language of HTML documents, and which contains a logically complete and easily understandable information package), in essence, is a document that needs to be displayed according to the requirements user (or the hardware requirements of his computer), turn according to the viewing mode (as a reference, or a lecture, or a test), separate the control from the frames ny questions and form the final examinations.

To do this, you can take a similar approach by creating a general document-frame diagram ", and then create a set of scripting styles for it, after which a presentation of the document will be formed, etc. The" course difficulty levels "mentioned above will thus be formed not actually a teacher, but programmatically.

Such a technological solution allows the teacher to concentrate on developing the course itself, and not on purely technical nuances. If you think over the structure of the course and write it in the form of UML diagrams, then using special software tools (for example, Rational Rose) the structure of the distance learning site is automatically created, and when using C ++ or Java, a ready-made model for the software product is created.

In practice, the teacher, while reading the course, is always immersed in the learning environment. The intuitive assessments that he makes as he works help him adjust the learning process in real time.

Distance learning courses do not allow the teacher to implement such actions, so the learning environment for him must be created artificially using technological means.

Indeed, in the learning process, the student first reads the material and tries to understand it. There is a simple assessment - the longer a student works on a text, the more difficult it is for him to learn.

However, how to distinguish the severity of perception from slow reading. For this, an additional indirect assessment is used - correction for reading speed. Its essence is that a student is given a simple, preferably even very simple text (or several) before completing the course, at the end of which several simple, but not trivial questions are given, designed in such a way that they reflect the essence of the text.

A student can go to questions only by pressing the "complete" button. The time that has passed from the moment the text was opened to the click of a button is the approximate reading time, which can serve as a basis for adjusting for reading speed.

If the student answers the whole question correctly, time is recorded. Several iterations of this test give the dependence of the reading speed on the volume of the text, and thus, when assessing the student’s perception of a topic, you can make a correction and determine exactly whether it is "hard" for him to perceive the text or he just reads slowly. The severity of the perception of the text is, by the way, an assessment, which the teacher usually does intuitively.

After reading the text and its more or less mastery, the student proceeds to a practical example. This example can be designed as a module with arbitrary parameters.

If a student, not just scrolling through an example, performs a certain set of typical tasks, but checks how parameter changes affect the result, then this is the first indirect signal that he is interested in the topic and understands it.

After the practical task, the student proceeds to the test (conditionally). There may be two or more questions in this test. Here you can also apply some indirect estimates to determine the question of the test that causes the greatest difficulties.

The simplest such estimate is the focus time estimate. A student, reading and solving problems, spends a certain amount of time. The longer this time, the greater the “gravity” of the student’s subject. By adjusting for the reading speed (see above), you can determine how much time he focused on solving a specific problem.

Thus, the teacher receives not only information about the correctness or incorrectness of the answer, but also how difficult this or that question was for the student. And this grade in academic learning is called intuitive.

In the end, the last of the more or less simple indirect assessments is the assessment of the consistency of the student's work. It can be determined from an analysis of the course. To do this, you need to slightly modify the classical layout of the material breakdown and introduce several levels of complexity.

Each frame should not just repel a certain ideoplast, but be designed for a certain level of perception. These levels can be determined experimentally, the criterion is the form of supply of the material.

Known systems that could be used to solve the problem [1, 2].

The first of the known systems comprises a computing unit connected to functional input and logical processing input units, the outputs of which are connected to a memory unit, a display unit connected to the computing unit and to the decision unit [1].

A significant drawback of this technical solution is its limited functionality, due to the fact that the description of input situations during training and quality control of knowledge is possible only in the space of a limited number of attributes, which leads to low efficiency of its use.

Another system is known that contains student data receiving units, the outputs of which are connected to a memory unit and to a data processing unit, a time interval selection unit, the outputs of which are connected to a student responses evaluation unit, to a memory unit and to a data processing unit, the outputs of which are connected to one of the inputs of the switching unit of the data output channels, the other inputs of which are connected to the time interval selection unit, and the outputs are the outputs of the system [2].

The last of the above technical solutions is closest to the described.

Its disadvantage is the low speed of the system, due to the fact that when starting the control test of the student, the search for the requested data is carried out throughout the system database, which leads to unreasonable loss of time and the inability to implement the training mode in real time.

The purpose of the invention is to increase the system performance by eliminating the search for test control data of students trained throughout the server database and localizing the search only at the reference addresses of the database corresponding to the specified parameters of the control test.

This goal is achieved by the fact that in the system containing the first register, the information and synchronizing inputs of which are the first information and synchronizing inputs of the system, respectively, the second register, the information and synchronizing inputs of which are the second information and synchronizing inputs of the system, respectively, the third register, information and synchronizing the inputs of which are the third information and synchronizing inputs of the system, respectively, the detection unit is correct response student, one information input of which is connected to the output of the second register, another information input is connected to the output of the third register, the synchronization input is connected to the second synchronization input of the system, and the information output is the first information output of the system, the fourth register, the information and synchronization inputs of which are the fourth information and synchronizing inputs of the system, respectively, the student’s knowledge assessment unit, the first and second counting inputs of which are connected are connected with the first and second counting outputs of the unit for determining the correctness of the learner's answer, respectively, and the information outputs are the second and third information outputs of the system, the fifth register, the information and synchronizing inputs of which are the fifth information and synchronizing inputs of the system, respectively, and the block for generating the signals for reading test tasks, the information output of which is the address output of the system, and the synchronizing output is the first synchronizing output of the system, under assigned to the installation input of the unit for determining the correctness of the student’s answer, a selection block for the base address of the learning test is introduced, the information input of which is connected to the output of the first register, the synchronizing input is connected to the first synchronizing input of the system, one information output is connected to the first information input of the unit for generating test read signals , the first synchronizing input of which is connected to the synchronizing output of the selection block of the base address of the training test, the verification unit o the end of the test tasks, the information input of which is connected to the other information output of the selection block of the base address of the training test, the first synchronizing input is connected to the synchronizing output of the selection block of the base address of the training test, the second synchronizing input is connected to the first synchronizing output of the unit for determining the correctness of the student’s answer, and the counting input connected to the first synchronizing output of the system, while one output of the test task completion block is connected to the first counting input a unit for generating signals for reading test tasks, and the other output is a signal output of the system, a selection block for the base address of the control test, the information input of which is connected to the first information output of the fourth register, and the synchronizing input is connected to the fourth synchronizing input of the system, the selection block for the address of the time period, information the input of which is connected to the second information output of the fourth register, the synchronizing input is connected to the synchronizing output of the selection block the base address of the control test, and the synchronizing output is connected to the second synchronizing input of the test task reading signal generation unit, the second counting input of which is connected to the second synchronizing output of the learner’s answer determining unit, the comparison unit, one information input of which is connected to the output of the fifth register, another information the input is the sixth information input of the system, and the synchronizing input is connected to the fifth synchronizing input of the system, the counting unit isla of transactions, the information input of which is connected to one information output of the selection block of the base address of the control test, and the synchronizing inputs are connected to the corresponding outputs of the comparison unit, while the information output of the unit for counting the number of transactions found is the fourth information output of the system, one synchronizing output is the second synchronizing output system, and the other is connected to the third counting input of the unit for generating test read signals, and the adder, one information the input is connected to the second information output of the selection block of the base address of the control test, the other information input is connected to the information output of the selection block of the address of the time period, the synchronizing input is connected to the synchronizing output of the selection block of the address of the time period, and the output of the adder is connected to the second information input of the forming unit test read signals.

The invention is illustrated by drawings, where Fig. 1 shows a structural diagram of a system, Fig. 2 shows an example of a specific structural implementation of a selection block of a base address of a training test, Fig. 3 shows an example of a specific constructive implementation of a block for checking the completion of test tasks, in Fig. 4 an example of a specific constructive implementation of a unit for checking the correctness of a student’s response is given, FIG. 5 shows an example of a specific constructive implementation of a unit for generating test read signals, FIG. an example of a specific constructive implementation of a selection block of a base address of a control test is given, Fig. 7 shows an example of a specific constructive implementation of a selection block of a time period address, Fig. 8 shows an example of a specific constructive implementation of a comparison unit, Fig. 9 shows an example of a specific constructive implementation of a counting unit the number of transactions, figure 10 shows an example of a specific constructive implementation of the unit for evaluating student responses.

The system (Fig. 1) contains the first 1, second 2, third 3, fourth 4 and fifth 5 registers, block 6 for selecting the base address of the training test, block 7 for verifying the completion of test tasks, block 8 for determining the correctness of the learner's response, block 9 for generating read signals tasks of the test, block 10 evaluating student responses, block 11 of the selection of the base address of the control test, block 12 of the selection of the address of the time period, adder 13, block 14 comparison, block 15 counting the number of transactions.

Figure 1 shows the first 21, second 22, third 23, fourth 24, fifth 25 and sixth 26 information inputs of the system, the first 27, second 28, third 29, fourth 30 and fifth 31 synchronization inputs of the system, as well as address 32 system output , the first 33, the second 34, the third 35 and the fourth 36 information outputs of the system, the first 38 and second 39 synchronizing outputs, and the signal 40 system output.

Block 6 selection of the base address of the training test (figure 2) contains a memory unit 41, made in the form of read-only memory, a decoder 42, elements 43-45 And, elements 46, 47 delay. The drawing shows the synchronizing 49 and information 50 inputs, as well as the first 51 and second 52 information and synchronizing 53 outputs.

Block 7 checking the end of the test tasks (figure 3) contains a comparator 55, register 56 and counter 57. The drawing shows information 58, first 59 and second 60 clock inputs, counting 61 input, as well as first 62 and second 63 outputs.

Block 8 determining the correctness of the answers of the learner (figure 4) contains a comparator 66, trigger 67, elements 68, 69 AND, elements 70 AND groups and element 71 delays. The drawing also shows the first 72 and second 73 information inputs, synchronizing 74 and installation 75 inputs, as well as information output 76, the first 77 and second 78 synchronizing, the first 79 and second 80 counting outputs.

Block 9 for generating signals for reading test tasks (Fig. 5) contains a counter 81, trigger 82, groups 83-84 AND elements, elements 85 OR groups, elements 86-88 OR, and delay elements 89, 90. The drawing shows the first 91 and second 92 information inputs, the first 93 and second 94 synchronization inputs, the first 95, second 96 and third 97 counting inputs, as well as synchronizing 98 and information 99 outputs.

Block 11 selection of the base address of the control test (Fig.6) contains a memory block 101 made in the form of read-only memory (ROM), registers 102 and 103, a decoder 104, elements 105-107 And, elements 108-110 delay. The drawing shows the information 111 and synchronizing 112 inputs, the first 113 and second 114 information and synchronizing 115 outputs.

Block 12 of the selection of the address of the time period (Fig.7) contains a memory unit 121, made in the form of read-only memory, register 122, decoder 123, elements 124-126 And, elements 127, 128 delay. The drawing shows the synchronizing 129 and information 130 inputs, as well as information 131 and synchronizing 132 outputs.

The comparison unit 14 (FIG. 8) comprises a comparator 141 and a delay element 142. The drawing shows the first 143 and second 144 information and synchronizing 145 inputs, as well as outputs 146, 147 of the block.

Block 15 counting the number of transactions (Fig.9) contains a comparator 151, counters 152, 153, OR element 154, delay element 155. The drawing shows the information 156, the first 157 and second 158 clock inputs, as well as the first 159 and second 160 clock and information 161 outputs of the block.

Block 10 evaluating the responses of the trained user (figure 10) contains counters 139 and 140. The drawing shows the first 137 and second 138 counting inputs, as well as the first 34 and second 35 information outputs of the block.

All nodes and elements of the system are made on standard potential-impulse elements.

The system of distance learning for students is based on tasks for self-monitoring and control, implemented in these two different modes of operation. The methodology for constructing tests (i.e., a series of test tasks) for self-monitoring and control of mastering the knowledge of students in any subject area is generally similar.

However, there are differences. So, the direct and only purpose of control tests is to check the assimilation of knowledge in the discipline under study, while tasks for self-control include training elements, because in this case, the correct answers are reported during the control [3].

Based on this, the requirements for the correctness of the compilation of control tests are more stringent, since the studied level of knowledge should be adequately reflected by some quantitative indicators. In order for the prepared tests to really make it possible to assess the degree of assimilation of educational material, they must be compiled in accordance with the specific requirements of the classical theory of testing [4].

A remote workstation (AWP) of a trained user consists of a terminal having a screen for playing test tasks, examples of which are given in the mentioned source [3], and a keyboard of a personal computer. Presentation of test tasks in the distance learning system is controlled from the server (not shown in the drawing).

The system operates as follows.

In the process of distance learning students to the information input 21 of the system receives the identifier code of the trained user, which from the information input 21 of the system is entered in register 1 by a synchronizing pulse received at the synchronizing input 27 of the system.

From the output of register 1, the learner’s identifier code goes to the information input 50 of block 6, from where it is fed to the input of the decoder 42, which decrypts the identifier code and gives one of its outputs a high potential, which goes to the corresponding inputs of elements 43-45 I.

For definiteness, let us assume that element 44I will be open from the first output of decoder 42 with a high potential. The synchronizing pulse from system input 27 through input 49 of block 6 is delayed by element 46 for the duration of decoder 42 operation and is transmitted through element 44 AND to the input of a fixed cell of read-only memory (ROM) 41.

In a fixed cell of this memory block, a code message is stored, the structure of which in the first K1 bits stores the starting address of the first test task, and in the second K2 bits stores the total number of tasks in this test:

INITIAL ADDRESS OF FIRST TEST TASK TOTAL NUMBER OF TASKS IN THIS TEST (K1 bits) (K2 bits)

The contents of the K1 bits of the fixed cell ROM 41 are read to the output 51 of the block 6, and the contents of the K2 bits of the fixed cell ROM 41 are read to the output 52 of the block 6.

From the output 51 of block 6, the code of the initial address of the first test task through the input 91 of block 9 is fed to the inputs of the And elements 84, which are open at the second input with high potential from the inverse output of the trigger 82, which is in the initial state. The initial address code of the first test task passes through elements 84 AND groups and elements 85 OR groups to the information input of the counter 81.

In parallel with this process, the synchronizing pulse from the output of the delay element 46 of the block 6, delayed by the element 47 while reading the contents of the fixed cell ROM 41, from the output 53 of the block 6 is supplied to the synchronizing input 93 of the block 9 and then, firstly, to the installation input of the trigger 82, confirming or resetting it.

Secondly, the same pulse passes through the OR element 86, is delayed by the element 89 for the duration of the trigger 82 and then goes to the clock input of the counter 81, writing down the code of the starting address of the first test task, which must be presented to the trained user.

Thirdly, the same synchronizing pulse from the output of element 89 goes through the OR element 87, is delayed by element 90 while the start address code is entered into counter 81, and then from output 98 it is output to system output 38, from where it goes to the input of the first server interrupt channel distance learning systems.

With the arrival of this impulse, the server switches to a subprogram for interrogating the contents of the memory cell, the address of which is generated at the output 99 of the counter 81, which is output to the address output 32 of the system, and issuing the code of the first job of the learning test to the remote workstation of the trained user, and the correct answer code through the input 23 to the information input of register 3, where it is entered by the server synchronizing pulse coming through the input 29 of the system.

The structure of the codogram stored in the cell with the starting address of the first task of the training test has the following form:

THE CODE THE CODE first job test learning the correct answer to the task of the training test

In parallel with the process of issuing the first test task to the trained user, the code for the total number of tasks in the learning test from the output 52 of block 6 is received through the input 58 of block 7 to the information input of the register 56 of block 7, into which it is entered by the synchronizing pulse from the output 53 of block 6 through the input of 59 blocks 7.

In addition, from the output 98 of block 9, the read pulse of the learning test assignment through the input 61 of block 7 is supplied to the counting input of the counter 57, recording in the counter 57 the fact of issuing the first test assignment to the trained user.

Codes from the outputs of the register 56 and counter 57 are fed to the information inputs of the comparator 55, which compares the input codes for the signal received at the input 60 of block 7 from the output 77 of block 8.

After receiving the first test task, the trained user thinks over it at his workstation, generates and sends a response, the code of which comes through the input 22 of the system to the information input of register 2, where it is entered by the synchronizing pulse from the input 28 of the system.

The response code generated by the trainee, from the output of register 2 through the input 73 of block 8, is sent to one information input of the comparator 66, to the other information input of which the code of the correct answer to this test task is supplied from the output of register 3 through the input 72 of block 8, which also goes to one inputs of elements 70 And groups.

The synchronizing pulse from the input 28 of the system through the input 74 of block 8 is delayed by the element 71 for the time of entering the learner's response code into register 2 and then goes to the synchronizing input of the comparator 66, which compares the learner's response code and the correct answer code. If the response codes match, i.e. the user being trained correctly answered the first task of the test, then an impulse is generated at the output 170 of the comparator 66, which, firstly, from the output 80 of the block 8 through the input 138 of the block 10 goes to the counting input of the counter 140, counting the number of correct answers to all tasks of the training test .

Secondly, the same pulse passes through the element 69 And, open at the second input with high potential from the inverse output of the trigger 67, which is in the initial state, to the output 77 of block 8 and then through the input 60 of block 7 to the synchronizing input of the comparator 55, which compares the number tasks in the test learning register 56 with the number of tasks already presented to the trained user in the counter 57.

Given that only the first task was presented to the student at this point in time, the readings of register 56 will be much larger than the readings of counter 57, and a signal is generated at the output 172 of comparator 55. This signal from the output 62 of block 7 is fed to the input 95 of block 9 and then passes through the element 88 OR to the counting input of the counter 81, forming the read address of the next (next) test task, which is issued to the output 99 of block 9 and then to the address output 32 of the system .

In addition, the same pulse passes through the OR element 87 to the input of the element 90, where it is delayed by the response time of the counter 81, and then through the output 98 of the block 9 it is output to the output 38 of the system, from where it again enters the input of the first channel of the server interrupt. With the arrival of this impulse, the server again switches to the subroutine for polling the contents of the next memory cell, the address of which is generated at the output 99 of the counter 81, issued to the address output 32 of the system, and issuing the code for the next training test task to the remote workstation of the trained user, and the correct answer code through input 23 to the information input of register 3, where it is entered by the server synchronizing pulse coming through the input 29 of the system.

If the response codes in registers 2 and 3 did not match, i.e. the student incorrectly answered the first task presented to him, the signal appears on the output 171 of the comparator, which, firstly, through the output 79 of block 8 and the input 137 of block 10 immediately goes to the counting input of the counter 139, fixing the number of incorrect answers to all tasks of the test learning.

Secondly, the same pulse is supplied to the second inputs of the elements of the 70 AND group and rewrites the correct answer code from the output of the register 3 through the elements 70 of the And group to the output 76 of block 8 and then through the output 33 of the system to the workstation of the student.

Thirdly, the same pulse arrives at the single input of trigger 67 and sets it to a single state, in which trigger 67 opens one input of element 68 And, preparing a chain for the pulse from output 170 of the comparator through element 68 And to output 78 of block 8.

Having received the correct answer code after an incorrect answer to the test task, the student repeats the entry in register 2 now of the correct answer code, which is entered into register 2 with a synchronizing pulse from system input 28.

The synchronizing pulse from the input 28 of the system through the input 74 of block 8 is delayed by the element 71 for the time of entering the learner's response code into register 2 and then goes to the synchronizing input of the comparator 66, which compares the learner's response code and the correct answer code. Since in this case the response codes will necessarily coincide, an impulse is generated at the output 170 of the comparator 66, which, firstly, from the output 80 of the block 8 through the input 138 of the block 10 goes to the counting input of the counter 140, counting the number of correct answers to all tasks of the training test .

Secondly, the same pulse passes through the And element 68, open at the second input with a high potential from the direct output of the trigger 67, which is in a single state, to the output 78 of the block 8 and then through the input 96 of the block 9 and through the element 88 OR to the counting input counter 81, preparing the read address of the next training test assignment.

In addition, the same pulse from the output of the OR element 88 passes through the OR element 87 to the input of the element 90, where it is delayed by the response time of the counter 81, and then, through the output 98 of the block 9, it is output to the output 38 of the system, from where it again enters the input of the first interrupt channel server. With the arrival of this impulse, the server again switches to the subroutine for polling the contents of the next memory cell, the address of which is generated at the output 99 of the counter 81, issued to the address output 32 of the system, and issuing the code for the next training test to the remote workstation of the trained user, and the correct answer code through the input 23 to the information input of register 3, where it is entered by the server synchronizing pulse coming through the input 29 of the system.

The described user training process will continue until the comparator 55 of block 7 fixes the equality of codes in the register 56 and counter 57 by issuing a signal to the output 173 of the comparator 55 and then through the output 63 of the block 7 to the output 40 of the system. By this signal, which is input to the second channel of the server interrupt, the server switches to the subroutine for interrogating the readings of the counters 139 and 140 of block 10 from the outputs 34 and 35 of the system, respectively, and determining the degree of readiness of the student to perform the control test.

If the number of incorrect answers exceeds a predetermined threshold, then the described training procedure is repeated until the number of incorrect answers is reduced to the required level, which will indicate the readiness of the student to perform the control test.

In contrast to the well-known systems, the described distance learning system implements verification of the degree of preparedness of students for work on a control database. The control test involves conducting specific marketing research on the electronic trading market for each of the students on various issues. As an example of the control test used to verify the student’s readiness for real work, consider a test in the process of which the student should give an answer to the question: for which goods from a given group are transactions with the highest trading volume.

To solve this problem, the learner should formulate a corresponding request at his workstation, the codogram of which has the following structure:

PRODUCT CODE CODE OF THE YEAR TRANSACTION SPECIFIED CODE marketing research (threshold) in the current year

In this case, the code of the selected product and the digital value of the code of the year from the information input 24 of the system go to the information input of the register 4, and the code of a given volume of transactions from the information input 26 of the system goes to the input 143 of the comparison unit 14.

The receipt of the request codogram from the student’s workstation is accompanied by a synchronizing pulse arriving at the input 30 of the system and then at the synchronizing input of register 4, recording the digital value of the year code and the code of the selected product.

The product code from the second output of the register 4 goes to the input 111 of the block 11, from where it is fed to the input of the decoder 104, which decrypts the product code, giving one of its outputs a high potential and thereby opening one of the elements 105-107 I.

The same clock pulse from the input 30 of the system goes to the input 112 of the block 11 and then after a delay by the element 108 for the time the code is entered into register 4 and the response time of the decoder 104 goes to the polling of the state of the elements 105-107 I.

Given the fact that only one of the elements 105-107 I will be open at one input, then, having passed the corresponding element And, the clock pulse is fed to the read input of a fixed memory cell of a read-only memory device (ROM) 101, where the base (initial) address of the section is stored server memory (not shown in the drawing), which stores all records of transactions with the selected product.

The structure of the read code from a fixed memory cell ROM 101 has the following form:

The code The code The base address of the database server memory partition The total number of transaction records for the selected product

The code of the base address of the memory section for a given product and the code of the total number of records of transactions with the selected product from the outputs of the ROM 101 are transmitted to the information inputs of the registers 102 and 103, respectively, where they are entered by the synchronizing pulse from the output of the element 109, which delays the synchronizing pulse from the output of the delay element 108 by read time codes from ROM.

The code of the base address of the memory section of the database server from the output of the register 102 through the output 113 of the block 11 is output to the input 135 of the adder 13, and the code of the total number of records of all transactions for a given product from the output of the register 103 through the output 114 of the block 11 is issued to the information input 156 of the block 15 . The issuance of codes from the outputs of the registers 102 and 103 is allowed by the clock from the output of the element 110, which delays the synchronizing pulse by the response time of the registers 102 and 103.

The synchronizing pulse from the output of the delay element 110, through the output 115 of the block 11, is supplied to the synchronizing input 129 of the block 12, the information input 130 of which is supplied with the year code from the first output of the register 4, then fed to the input of the decoder 123.

The decoder 123 decodes the code of the sign of the year, giving one of the inputs of the elements 124-126 And high potential. As a result of this, the synchronizing pulse from the input 129 of block 12, firstly, passes the corresponding element And, opened by the decoder 123, to the read input of the fixed memory cell ROM 121, from which it reads the reference address of the year in register 122, where it is entered by the synchronizing pulse with input 129, the delayed element 127 at the time of reading the code from the ROM 121.

From the output of the register 122, the reference address of the year through the output 131 of the block 12 is supplied to the information input 134 of the adder 13, the other input of which is the code of the base address of the section of the specified product from the output 113 of the block 11.

In parallel with this, the synchronizing pulse from the output of the element 127 of the block 12 is delayed by the element 128 for the duration of the operation of the register 122 and the output 132 enters both the synchronizing input of the adder 13 and the synchronizing input 94 of the block 9.

On a synchronizing pulse, the adder 13 generates the resulting address for reading the data of the control test for a given product in the current year from the server database (the base address of the page of the current year in the section of the specified product), which from the output 136 of the adder 13 through the input 92 of block 9 goes to the inputs of the elements 83 And groups.

At the same time, the pulse from the input 94 of block 9 immediately arrives at the single input of the trigger 82 and sets it to the single state, in which the elements of the 83 AND group are opened and the code of the base address of the page of the current year passes through the elements of 85 OR of the group and goes to the information input of the counter 81.

In addition, the same pulse from input 94 passes through the OR element 86, is delayed by the element 89 for the duration of the trigger 82, and, firstly, it goes to the synchronizing input of the counter 81, entering the code of the base address of the current year’s page in the specified product section.

Secondly, the same synchronizing pulse from the output of the delay element 89 passes through the OR element 87 and after the delay by the element 90 while the code of the base address of the current year’s page is entered into the counter 81, it passes to the output 98 of block 9 and then to the output 32 of the system, from where it arrives at input of the first channel of the database server interrupt.

With the arrival of this signal, the server switches to the subroutine for reading the contents of the database page at the address generated at the output of the system 32 and writing, firstly, the readings of the database into the receiving register of the student's workstation (not shown), and, secondly, recording the value of the volume of the first transaction for a given product in the current year from input 25 to register 5 by the server synchronizing signal from input 31 to the synchronizing input of register 5.

From the output of register 5, the read value of the volume of the first transaction for a given product in the current year goes to the input 144 of block 14, to the other input 143 of which from the input 26 the threshold value of the volume of the transaction set by the student in the current year comes out, set in his request in the control test. By a synchronizing pulse from input 31, which is input to input 145 of block 14 and delayed by element 142 while the code is in register 5, comparator 141 compares the input transaction codes.

If the value of the transaction volume for this product in the current year, recorded in register 5, is less than the threshold value set by the trainee, then an output is generated at the output 146 of block 14, which goes to the input 157 of block 15 and then through the 154 OR element directly to the synchronizing input of the comparator 151, on one information input of which input 156 receives the code of the number of transactions for this product from the output 114 of block 11, and to another input - the code of the readings of the counter 152, fixing the number of read transaction records from the server database memory.

Considering that by now the counter 152 was in its initial state, its readings were equal to zero, and when comparing the input codes, the comparator 151 produces a signal less, which from the output 159 goes to the input 97 of the block 9 and then through the element 88 OR is fed to the counting counter input 81, increasing the read address by one. In addition, the same pulse passes through the OR element 87, is delayed by the element 90 for the duration of the counter 81 operation, and then through the output 38 of the system it enters the input of the first channel of the database server interrupt.

With the arrival of this signal, the server again switches to the subroutine for reading the contents of the database at the address generated at the output of the system 32 and recording, firstly, the readings of the next codogram of the database into the receiving register of the student’s workstation (not shown), and, secondly, recording the value of the transaction volume from input 25 to register 5 by the server synchronizing signal from input 31 to the synchronizing input of register 5.

If the value of the read transaction volume exceeds the threshold level set by the trainee, then an output is generated at the output 147 of block 14, which is fed to the input 158 of block 15 and then fed to the counting input of the counter 153, fixing the number of transactions whose volume exceeded the threshold level, so and through the OR element 154 to the synchronizing input of the comparator 151 comparing the number of transaction records for a given product that took place in the current year with the total number of transaction records for a given product read.

The described process of reading transaction records from the server database will continue until the comparator 151 of block 15 fixes the equality of codes at its inputs by issuing a signal to output 160 of the block and then to output 39 of the system, indicating that the selection of transactions exceeding a given level (threshold), completed, and the number of such transactions is recorded in the counter 153 of block 15.

The synchronizing signal from the output of the system 39 is fed to the input of the third interrupt channel, through which the server switches to a program for comparing the received answer with the correct answer to the question of the control test and informing the learner of the results of the control test.

If the result obtained by the student in completing the task of the control test is correct, then the student is informed of the successful completion of the training.

If the execution of the control test on a real database gives the wrong result, then the training procedure is repeated, starting with the presentation of the training test.

Thus, the introduction of new nodes, blocks, and new structural connections has significantly improved system performance by eliminating data retrieval across the entire system database.

Information sources

1. US Patent No. 0,005,651, M. cl. G06F 13/40, 13/38, 1992.

2. US Patent No. 5129083, M. cl. G06F 12/00, 15/40, 1992 (prototype).

3. Romanov A.N. et al. Distance learning technology. M .: UNITY-DANA, 2000.

4. Alan Carter, Colston Sanger Programmer's Stone - NY, Addison-Wesley, 1996.

Claims (1)

A distance learning system for students, containing the first register, the information and synchronizing inputs of which are the first information and synchronizing inputs of the system, respectively, the second register, the information and synchronizing inputs of which are the second information and synchronizing inputs of the system, respectively, the third register, the information and synchronizing inputs of which are third information and synchronizing system inputs, respectively, the unit for determining the correctness of the student’s answer, one information input of which is connected to the output of the second register, another information input is connected to the output of the third register, the first synchronizing input is connected to the second synchronizing input of the system, and the information output is the first information output of the system, the fourth register, the information and synchronizing inputs of which are the fourth information and synchronizing inputs of the system, respectively, the student’s knowledge assessment unit, the first and second counting inputs of which are connected are not connected with the first and second counting outputs of the unit for determining the correctness of the learner’s response, respectively, and the information outputs are the second and third information outputs of the system, the fifth register, the information and synchronizing inputs of which are the fifth information and synchronizing inputs of the system, respectively, and the block for generating test read signals, the information output of which is the address output of the system, and the synchronizing output is the first synchronizing output of the system, according to connected to the installation input of the unit for determining the correctness of the student’s response, characterized in that it contains a selection block for the base address of the training test, the information input of which is connected to the output of the first register, the synchronization input is connected to the first synchronizing input of the system, one information output is connected to the first information input of the block generating signals for reading test tasks, the first synchronizing input of which is connected to the synchronizing output of the selection block of the base address of the test the training unit, the test completion test block, the information input of which is connected to the other information output of the training test base address selection unit, the first synchronization input is connected to the synchronization output of the training test base address selection block, the second synchronization input is connected to the first synchronization output of the response correctness determination unit learner, and the counting input is connected to the first synchronizing output of the system, while one output of the test completion block of the test tasks is connected is connected to the first counting input of the unit for generating readings of test tasks, and the other output is the signal output of the system, the selection block of the base address of the control test, the information input of which is connected to the first information output of the fourth register, and the synchronization input is connected to the fourth synchronizing input of the system, the selection block addresses of the time period, the information input of which is connected to the second information output of the fourth register, the synchronization input is connected to the synchronizer the output of the selection block of the base address of the control test, and the synchronizing output is connected to the second synchronizing input of the signal generation unit for reading test tasks, the second counting input of which is connected to the second synchronizing output of the unit for determining the correct answer of the student, the comparison unit, one information input of which is connected to the output of the fifth register, another information input is the sixth information input of the system, and the clock input is connected to the fifth clock in the system, the unit for counting the number of transactions, the information input of which is connected to one information output of the selection unit of the base address of the control test, and the synchronizing inputs are connected to the corresponding outputs of the comparison unit, while the information output of the unit for counting the number of transactions is the fourth information output of the system, one synchronizing output is the second synchronizing output of the system, and the other is connected to the third counting input of the block for generating test read signals, and the adder, one information input of which is connected to the second information output of the selection block of the base address of the control test, the other information input is connected to the information output of the selection block of the time period address, the synchronizing input is connected to the synchronizing output of the selection block of the time period address, and the output of the adder is connected to the second information input of the block generating test read signals.

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