SU1425760A1 - Apparatus for training operators - Google Patents

Abstract

The invention relates to a simulator and can be used to train operators. The purpose of the invention is to expand the didactic capabilities of the device. At the same time, the effectiveness of training of operators at the stage of developing the skills of timeliness of execution of control algorithms is repeated. Generator II, delay elements 8, 155 19, prohibition element 12, trigger 17, and an audible alarm unit 18 are introduced into the device. The device also contains the address register 1, memory block 2, microcommand register 3, information board 4, operator response input block 5, comparison blocks 6, 16, elements 7, 9, 14 OR, trigger 10, counting 13. I lin.

Description

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The invention relates to the technical means of training operators and can be used in simulators for training control system operators,

The purpose of the invention is the expansion of the didactic capabilities of the device, which provides an increase in the efficiency of operator training in timely actions when executing control algorithms.

The drawing shows the proposed device.

The device contains an address register, memory block 2, microcommand register 3, information board 4, operator response input block 5, comparison block 6, element OR 7, delay element 8, element OR 9, trigger 10, generator 11, prohibition element 12 , a counter 13, an element OR 14, a delay element 15, a comparison block 16, a trigger 17, a sound alarm block 18 and a delay element 19.

Register 1 is intended for storing data about the control component of the operator's operation algorithm. Register 1 stores the addresses of micro-instructions in block 2, corresponding to the letharized operations of the algorithm. Register 1 has as many cells as there are operations containing an activity algorithm, plus one cell that records the time when the algorithm terminates. The output of this cell is the output of the register 1 overflow. When a signal appears at the setup input of register 1, the first micro-operation of the microprogram corresponding to the first algorithm operation is selected. With the arrival of signals at the information input of the register, the next microcommand of the corresponding regular operation of the algorithm is shifted and matched.

Block 2 is used to store the parameters of the algorithm of activity. In block 2, microinstructions microprograms are stored in the form of microprograms corresponding to the operations of the operator's operation algorithm.

Register 3 is intended for short-term storage of the parameters of the current operation of the operator's activity algorithm. Each microinstruction consists of three microoperations, in the first of which the display organ code of the display 4 is stored, which changes its state in this operation. In the second

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The micro-operation has the code of the governing body of block 5, and the third is the code of the time allotted for the operator to perform all the previous, and this Operation, activity algorithm.

Table 4 and block 5 are the physical model of the real operator console, being studied by the automated control system, in terms of the appearance and location of the corresponding organs.

Unit 6 is designed to assess the accuracy of the operator’s actions by comparing the codes of the required control unit of unit 5, which is activated by the operator arriving at the corresponding inputs of unit 6.

The trigger 10 serves to organize an interruption in the operation of the counter 13 for the time of reading information from it.

The generator 11 is intended to represent the time value of the operator's actions to perform the operation of the algorithm in the code.

The counter 13 is designed to count the number of pulses produced by the generator 11 in the time elapsed since the beginning of the workout (device startup) to; perform the current operation algorithm.-ma.

Block 16 is designed to compare the time spent by the operator on all operations, including the current one, from the beginning of the workout with the reference value of time allotted for performing these operations in accordance with the time standard.

The trigger 17 controls the starting and stopping of the block 18.

The device operates as follows.

When the device is turned on, the input of the register receives a signal from the external input 20 of the device when it starts. This signal is used to start the generator and select the microcommand in block 2, corresponding to the implementation of the first operation of the activity algorithm. The contents of this microcommand from block 2 are rewritten into register 3, which results in the appearance of signals at its inputs. This signal npoiifj- leads the change of state of the corresponding organs of the display board 4.

The human operator, perceiving this information, acts on the governing body of block 5. The code of the involved governing body goes to the inputs of block 6, and through the OR element 7 the signal goes to the input of register 3.

According to this signal, the contents of the second micro-operation are fed to the inputs of block 6, and the comparison resolution signal comes from the output of element 8 for-; - handles.

In case of an operator error, the comparison of the codes received at the inputs of block 6 does not occur and there is no signal at its output. If the operator performs the required action correctly, then a signal appears at the output of block 6, which, arriving at the input of register 3, results in matching the code of the time allotted for fulfilling the data and all previous operations and arriving at the inputs of block 16. The pulses produced generator 11, through element 12 enters counter 13, since element 12 is opened with a zero signal at its control input from a single output of trigger 10. A single signal from an output of trigger 10, is sent to the inverse input of prohibition element 12, hitting it one of the counter 13 and the zero input of the first trigger 10, remove the signal from its single output and thereby uncover element 12. The signal at the input of the counter 13 reads its content in block 16, and the signal from the output of the element OR 14 through the element The 15 delays are fed to the input of block 16, allowing permission for the comparison of the operator’s difficulty and the time allotted for him to perform this part of the control algorithm.

If the elapsed time is less than the allowable one, then the signal appears at the zero input tfr: gage 1, otherwise, i.e. if this time is more than acceptable, the signal is present at the second output of block 16 and it causes the trigger 17 to be in one state, which leads to the block 18. which leads to a shift to its next cell and the choice of the address of the next microcommand in block 2, i.e. The following operation is the operation algorithm.

In the following, the process is repeated cyclically in the described order until the completion of the algorithm.

After execution by the operator nor. the last operation of the algorithm the signal appears at the output of the register overflow and enters the generator input

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And to turn it off, and through item 10 and to the input of the counter 1-3 to take into account the time spent on the algorithm in its last operation.

Block 18 is launched on the first operation in which the operator exceeds the allowable time to perform it and all the previous operations, and can be disabled later, if any, the operator lost time to reach any of the remaining operations. .

The proposed device expands the didactic capabilities by developing a rhythm for the operator that ensures the timely completion of the control algorithm in this time standard. Providing the operator with information on exceeding the allowable time allows him to take timely measures during the control to eliminate the backlog. The methodical use of the proposed mode during training should be used after the operator has developed the skills of operational timeliness of the actions performed.

Claims (1)

Invention Formula A device for training operators that contains an address register whose information outputs are connected to the corresponding address inputs of a memory block whose outputs. connected to the corresponding information inputs of the micro-register register, the outputs of the first group of which are connected to the corresponding inputs of the information board, and the outputs of the second group - to the corresponding inputs of the first group of the first comparison unit, the inputs of the second group of which. connected to the corresponding; by the outputs of the input block of the operator’s response, the first, second and third elements OR, the first trigger and the counter, the outputs of which are connected to the corresponding inputs of the first group of the second comparison block, that, in order to expand the didactic capabilities of the device, a generator, a prohibition element, first, second and third delay elements, a sound alarm unit and a second trigger, whose output is connected to the sound signal block input, and S and R inputs are entered into itthe first and second outputs, respectively, of the second comparison unit, the outputs of the second group of which are connected to the corresponding outputs of the third group of the microconnect register connected to the output of the second OR element, whose input nepBbtfi is connected to the address register overflow output and the generator stop input connected to the first input of the micro register register read and the input of the third delay element The control inputs, and the control input, are connected to the information of the third delay element, the counter outputs are connected to the corresponding inputs of the third OR element, the output of which is connected to the input of the second delay element, the output of the inhibit element is connected to the information the input of the counter, the information input is with the output of the generator, and the control input is with the read input of the counter and a single output and 20 R input of the trigger, whose S input The address input of the address register, the setup input of which and the generator start input are the device input, the output of the first delay element is connected to the control input of the first comparison unit, and the input is connected to the second input of the microcommand register and the output of the first OR element, whose inputs are connected to the corresponding by the inputs of the operator response input block. ki, the output of which is connected to the information The address input of the address register, the setup input of which and the generator start input are the device input, the output of the first delay element is connected to the control input of the first comparison unit, and the input is connected to the second input of the microcommand register and the output of the first OR element, whose inputs are connected to the corresponding by the inputs of the operator response input block.