SU1492366A1 - Operatorъs training device - Google Patents

Abstract

The invention relates to a simulator tech nique and can be used in devices for training operators. The purpose of the invention is to expand the didactic capabilities of the device by training the operators to work in the ACS, taking into account the failures of its technical part and control objects, which increases the level of preparedness of the trainees to work in actual working conditions. The device additionally contains a group of memory blocks 18 (firmware), a group of address registers 17, groups of 16 and 21 elements AND, decoder 22, counter 23, group of trigger 28, a pushbutton switch representing the stop pulse generator 26, group of elements OR 5, elements And 9 and 10, the register of 14 operations. The device also contains the address register 1, memory block 2, microcommand register 3, information board 6, operator response input block 7, delay elements OR 4, 15, 19, delay elements 20, 24, 27, generator 25, counter 12, trigger 11, blocks 8, 13 comparisons. 1 il.

Description

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The invention relates to technical training devices and can be used in simulators for training ACS operators,

The purpose of the invention is to expand the didactic capabilities of the device.

The drawing shows a block diagram of the proposed operator training device,

The device contains the address register t (microcommand), memory block 2 (firmware), microcommand register 3, the element OR A, the group of elements OR 5, the information board 6, the operator response input block 7, the comparison block 8, the element AND 9, the element And 10, trigger II, counter 12, comparison block 13, register of 14 operations, element OR 15, group of elements AND 16, group of address registers 17 (microcommand), group of memory blocks 18 (microprogram), element OR 19 element 20 delay, a group of elements And 21, a decoder 22, a counter 23, a delay element 24, a generator 25, forming a stop pulse generator 26, a delay element 27, a group of trigger 28 and a device input (start) 29.

Registers 1 and 17 are designed to specify the control components of the main and emergency operator activity algorithms, respectively. They contain as many cells as there are elementary operations in the corresponding algorithms of activity.

Block 2 is designed to store data on each operation of the main control algorithm as micro-commands, and blocks 18 to store data on troubleshooting algorithm operations on the corresponding operations that occur during the development of the main control algorithm Each microprogram of the microprogram contains two microoperations. In the first microoperation is stored the code of the display indication body 6, which changes its state in this operation of the control algorithm. In the second micro-operation of the micro-command, the code of the control body of block 7 is stored, on which the operator has to act in this operation of the algorithm.

Register 3 stores a microinstruction corresponding to the current operation of the algorithm performed by the operator.

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Table 6 and block 7 are the physical model of the real operator control panel on which it performs the control task.

Block 8 is designed dp evaluation. the error-free operation of the operator, performed using the controls of unit 7,

Elements I9 and 10 perform the functions of switching nodes of choice () of locks 2 or 18, respectively, for issuing data to the operator about the main control algorithm or the emergency algorithm.

The trigger 11 controls the selection of the appropriate-: real-time operator algorithm.

Counter 12 is designed to count the number of operations performed by the main control algorithm before the occurrence of the Avar situation,

Block 13 is used to determine the moment of non-paring, after which the operator is obliged to proceed with the execution of the emergency algorithm.

Register 14 is designed to store the number, the operation of the main algorithm, on which the Fault occurs,

The OR 15 element combines the outputs of the registers 17 and the output of block 8 through the AND 9 element with the information input of the register 1 of the main algorithm.

Group 16 allows you to commute the required emergency algorithm, for the operator to work out, depending on the operation number of the main algorithm on which the Fault occurred, (

Element OR 19 and delay element 20 synchronize the process of reading the second micro-operation from register 3 to block 8 and the time it compares the received codes.

The group of elements And 21 commutes the outputs of the register 14 to the inputs of the decoder 22,

The decoder 22 makes it possible to unambiguously match the operation number of the main algorithm on which the Fault occurred, the required algorithm for its elimination.

The counter 23 together with the generator 25 are designed to randomly set the operation number on which the Fault should occur. The capacity of the counter is determined by the number of operations of the main algorithm.

The group of triggers 28 ensures the stable operation of the device during the operator’s working out of the corresponding emergency algorithm.

The device works as follows.

When the device is turned on, a signal appears at the external input 29 of the device. This signal starts the generator 25, arriving at the input of register 1, selects the address of the first

microcommands in block 2 and rewrites its contents to register 3 through the elements OR 5. At the first outputs of register 3, a signal appears that arrives at the 6th panel of the operator’s console and, in accordance with the code recorded in the first microoperation of the microcommand, changes its state. The operator, perceiving this information, acts on the corresponding governing body of block 7, the code of the body involved enters the inputs of the first

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cut element 27 - to rokho counter 12, block 13 and register 1A, as well as to the input of the register I through the element OR 1 5,

The next cell of register 1 is shifted and the address of the next microcommand in block 2 is selected. Next, the operation of the device is repeated in the order described earlier to the number of the operation on which the Fault occurs, the order is set next, From the moment the device is turned on, the generator 25 starts and generates clock pulses, which from its output are fed to the input of counter 23, the capacity of which is determined by the number of operations of the main control algorithm. In the case of overflow of counter 23, counting begins with first operation. The training instructor, pressing the forcing button 26, stops the generator 25 and through the element 24 with a signal 25 and enters the counter 23 rewrites its contents into the register 14. Thus, the main algorithm will be executed until it is 15

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the number of operations performed by block 8 and through the OR 19 element by the operator will fall (it is counted by the command to enter register 3 for chip 12), and the operation number for which the contents of the second micro-operation are read is the code of the required governing body of block 7 to the inputs of block 8, the command to compare comes from the output of the element OR 19 through the element 20 to the input of block 8, This command compares the codes of the involved and the required governing body of block 7 received at the inputs of block 8, If the received codes are not the same, the signal There will be no output at block 8; it only goes after the codes coincide and goes to the inputs of the first 9 and second 10 elements AND, Signals to their second inputs come from the direct and inverse outputs of trigger 1I, Trigger I1 is in the process of executing the main algorithm in the unit state due to the signal at its input, which comes from the output of the element OR 4, whose inputs combine the outputs of register 1, the signal from the direct output of the trigger 11 will be

the swarm occurs Fault, i.e., the code stored by register 14, the fact of the coincidence of these numbers is checked by increasing the content of counter 12 by one and is fixed by block 13, the signal from its output goes to the input of trigger 11, converting it to the zero state, and The inputs of the elements And 21, to the other inputs of the elements And 21 are signals from the output of the register 14, t, e, the code of the operation number on which HeHdn-equality occurs. This code arrives at decoder 22 and a signal appears at its output, which corresponds to the input signal code, which provides an unambiguous choice of the corresponding registers in the group 17 and block 18, which stores the elimination algorithm of the Fault. The signal from the inverse output of the trigger 11 arrives element 10 and opens it, and element 9 closes due to the absence of a signal at the direct output of the trigger 1I. When the operator continues to work, the signal from the output of block 8 enters through the element 10 and the inputs of the elements 16 ele50

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element 9 is opened, from the output of which the comparison signal of block 8 is fed to the input of counter 12 for counting the number of operations performed,

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cut element 27 - to rokho counter 12, block 13 and register 1A, as well as to the input of the register I through the element OR 1 5,

The next cell of register 1 is shifted and the address of the next microcommand in block 2 is selected. Next, the operation of the device is repeated in the order described earlier to the number of the operation on which the Fault occurs, the order is set next, From the moment the device is turned on, the generator 25 starts and generates clock pulses, which from its output are fed to the input of counter 23, the capacity of which is determined by the number of operations of the main control algorithm. In the case of overflow of counter 23, counting begins with first operation. The training instructor, by pressing the forcing button 26, stops the generator 25 and through the element 24 with a signal 5 to the input of the counter 23 rewrites its contents into the register 14. Thus, the main algorithm will be executed until it is combined

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the number of operations performed by the O operator (it is counted by the counter 12), and the operation number on which

the swarm occurs Fault, i.e., the code stored by register 14, the fact of the coincidence of these numbers is checked by increasing the content of counter 12 by one and is fixed by block 13, the signal from its output goes to the input of trigger 11, converting it to the zero state, and The inputs of the elements And 21, to the other inputs of the elements And 21 are signals from the output of the register 14, t, e, the code of the operation number on which HeHdn-equality occurs. This code arrives at decoder 22 and a signal appears at its output, which corresponds to the input signal code, which provides an unambiguous choice of the corresponding registers in the group 17 and block 18, which stores the elimination algorithm of the Fault. The signal from the inverse output of the trigger 11 arrives element 10 and opens it, and element 9 closes due to the absence of a signal at the direct output of the trigger 1I. When the operator continues to work, the signal from the output of block 8 enters through the element 10 and the inputs of the elements 16 ele0

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And 16, the input of which will be given a signal from the direct output of the trigger 28, which is transferred to one state by the arrival of a signal from the output of the depotfrarator 22. Appeal to the selected register 7 and block 18 until the operator completes execution troubleshooting algorithm; After an error-free execution of the emergency algorithm, the operator returns to continue the execution of the algorithm; For this, the signal from the last cell of the register 17 nocTynaei to the input of the corresponding trigger 28 returns it to the zero-state and closes the element I 16, as well as through the element 11PN 15 to the input of the register 1, the signal from whose output through the element I.GM 4 triggers the 1 1 trigger in a single state and reopens the AND 9 element. The device will continue to operate in the order described earlier, ensuring that the operator continues the basic control algorithm,

The proposed device allows to expand the didactic possibilities AND to ensure that the level of preparedness of operators to perform control algorithms is increased, taking into account the occurrence of possible malfunctions in the control objects or the technical part of the ACS in any operation of the control algorithm.

Claims (1)

Invention Formula A device for training operators, containing the address register, the installation input of which is: the device input, and the outputs are connected to the corresponding address inputs of the memory block, ret-micros of the microcommand, the outputs of the first group of which are connected to the corresponding information boards, control panels. The first input is to the output of the first OR element and the input of the first delay element, and the outputs of the second group are to the corresponding information inputs of the first group of the first comparison unit, the control of which your input is connected to the output the first delay element, and the information inputs of the second group with the corresponding inputs of the input unit for the response of the operator connected to the corresponding inputs 0 5 about d five 68 The first OR element, the second OR terminal, the output of which is connected to one trigger input, the other input of which is connected to the output of the second comparison unit, the inputs of the first group of which are connected to the corresponding outputs of the first counter, and the control input and a control input of the counter, a generator, a third delay element, and a third OR element, characterized in that, in order to expand;: the device’s educational capabilities, a group of address registers, a group of memory blocks, a group riggers, first and second groups of elements AND, 11PI group of elements, decoder, second counter, operation register, stop pulse generator and first and second elements AND, the first inputs of which are connected to the output of the first comparison unit, the second inputs - with single and zero outputs respectively trigger, the output of the first element I is connected to the information input of the first counter, the input of the second delay element and the input of the third element 1-SHI, and the output of the second element I to the first inputs of the AND elements of the first group, the second passages to They are connected to the unit outputs of the corresponding group triggers, and the outputs are connected to the inputs of the corresponding group address registers, whose information outputs are connected to the address inputs of the respective memory blocks, and the overflow outputs to the inputs of the corresponding group triggers and to the corresponding inputs of the first group of the second element Tt OR, the inputs of the second group of the second element 1PI are connected to the corresponding 1 outputs of the address register, whose information input connected to the output of the third element 1 | T OR, the outputs of the memory blocks are connected to the corresponding inputs of elements OR of the groups whose outputs are connected to the information inputs of the microcommand register, the generator start input is connected to the device input, the output from the information input of the second counter, and the stop input - with the output of the for1 addr-wa1 sl stop pulses, connected to the - INPUT of the third delay element, U9236610 the course of which is connected to the control group — with the first inputs, the corresponding input of the second counter, the outputs of the cat / -relaying elements AND of the first group, the second are connected to the corresponding third inputs of the elements AND of the first group and the formation inputs of the operation register are connected to the output of the second block; the groups of which are combined-comparisons, and the outputs are corresponding to the corresponding inputs to the second inputs of the decoder, the outputs of which are groups of the second comparison unit, which are connected to the S inputs of the corresponding control input m vtorogoschih triggers group delay element, and outputs a second