SU1336084A1 - Device for training operators - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in simulators of ACS operators. The purpose of the invention is to expand the didactic capabilities of the device. The device contains the address register 1, memory block 2, microcommand register 3, indication block 4, response input block 5, comparison blocks 6, 7, AND elements 8, memory block 9, trigger 10, OR element 11, delay element 12, elements AND 13, triggers 14, element OR 15, elements AND 16, element OR 17. The essence of the invention consists in training the operator to perform step-by-step self-control of the actions performed, as well as the ability to detect and correct errors made in the control of individual objects in general control algorithm. 1 il. S (L with So 05 O 00 4

Description

The invention relates to simulators of control system operators and can be used to train control system operators.

The purpose of the invention is to expand the didactic capabilities of the device.

The drawing shows a block diagram of a device for training operators.

The device contains the address register 1 (microcommand), memory block 2 (firmware), microcommand register 3, indication block 4, response input block 5, comparison blocks 6 and 7, AND 8 block of elements, memory block 9, trigger 10, OR 11, delay element 12, AND 13 group of elements, trigger group 14, OR 15 group of elements, AND 16 group of elements, OR 17 element and device launch input 18.

Register 1 is intended to specify the control component of the operator's activity algorithm. Unit 2 is designed to store, in the form of micro-commands, data about each operation of the control algorithm. When signals appear at the inputs of block 2, the microcommand of the current operation of the algorithm is read into register 3, which is intended for storing data of the current, processed, operation of the algorithm. This register consists of two micro-operations: in the first one there is stored the code of the display unit-block 4, which changes its state in this operation of the algorithm, and in the second micro-operation, the code of the organ block 5, which the operator must influence in the same operation of the algorithm. activities.

Blocks 4 and 5 are the physical model of the real operator control panel.

Unit 6 is designed to assess the accuracy of the operator’s effect on the organ of unit 5 - the required organ. In the case of coincidence of incoming codes, i.e., the operator’s impact-free operation, a signal appears at the first output of block 6. If the operator engages the wrong body of block 5, then the codes do not occur and the signal appears at the second output of block 6.

Block 7 is used to check the fact of detection by the operator in the management of a single object before his transition to the management of the next object. If the operator detected the error made earlier and resumed control of the same object, then in block 7, the codes from the outputs of block 5 and block 9 are compared, and a signal appears at the second output of block 7. A signal at its first output appears in case the operator proceeded to control the next object without finding or eliminating an error in the management of the previous object.

Block 9 stores the control codes from which each control begins

0

The new facility, the operator must return to the same controls, if the goal of controlling this facility is not achieved due to the mistakes made by it.

The trigger 10 stores the fact that the operator has committed an error in the process of controlling the object.

The group of triggers 14 contains as many of them as the number of control objects included in the general algorithm. They allow the operator, after detecting an error in the control of the object, to return to the first operation of this part of the algorithm and eliminate the allowed error.

The device functions as follows.

5 way.

Before turning on its trigger 10 is in the zero state, the triggers 14 are in one states.

With the inclusion of the device, due to the occurrence of a signal at input 18, through the element 17

 this signal is fed to the input of register 1. By this signal, the code of the first microcommand in block 2 is selected from the first cell of register 1. This microcommand is rewritten into register 3, from which the contents

5 of the first micro-operation enters the panel of the block 4, where the corresponding organ changes its state. The operator, perceiving the information, carries out the corresponding action with the help of the organ of block 5. The code of the activated control body enters one input of block 6, the other inputs of which come from the second microoperation of the microcommand code of the required control. When the received codes coincide, the signal appears at the first output of block 6 and enters the input of register 1. When a signal arrives at this input of register 1, it shifts to the right and reads the code of the next microcommand from register cells 1. The entire described operation cycle repeats, but already for

0 of the second operation of the algorithm, etc. In this case, the technique provides for the possibility of the operator moving to the next operation, within the control of one object, even if he makes an error on the current operation. Therefore, in the event of erroneous actions and mismatch of codes in block 6, the signal appears at its other output and through the input of element 11 enters the input of register 1.

Register 1 outputs are grouped together.

Q according to the number of control objects, while the outputs of each group are connected via the elements 15 to the single inputs of the trigger 14. When controlling individual objects, the operator’s error-free operation is controlled by the zero state of the trigger 14. When the operator makes an error, the signal appears at the second output block 6, this signal translates the trigger 10 into one state and through element 16

switches trigger 14 to one state. After the operator completes the control of this object, the signal from the output of register 1 is fed to the corresponding input of block 9, from the output of which, through the open elements 8, the control body code of the first control operation of this object is fed to the input of block 7. when controlling this object, it will try to proceed to the control of the next object, the code of the involved unit of block 5 is fed to the input of block 7 and no comparison is made. The signal from the output of block 7 through element 17 enters the input of register 1 and brings the device into the state corresponding to the beginning of the algorithm, i.e., a new workout. In the event that the operator detects an admitted error, he chooses a control corresponding to the re-execution of that part of the algorithm that relates to the control object. At the same time, as a result of the comparison, the signal now appears at the second output of block 7. This signal transfers trigger 10 to the zero state and through element 12 and the prepared element 13 enters the input of register 1 and selects its cell with the address of the microcommand storing the parameters operations of the control algorithm for these control objects.

The invention expands the didactic capabilities of the device due to the fact that the operator learns the phased self-control of the actions performed, which improves the quality of his work due to his ability to detect and eliminate errors made in the management of individual objects in the overall control algorithm.

Claims (1)

Invention Formula A device for training operators, containing an address register, the outputs of the first, second and third groups of which are connected to the corresponding inputs of the first memory block, the outputs of which are connected to the corresponding inputs of the microcommand register, the outputs of the first group of which are connected to the corresponding inputs of the block indications, and the outputs of the second group - with the corresponding inputs of the first group of the first comparison unit, the inputs of the second group of which are connected to the corresponding outputs of the response input unit, and the first OR element, characterized in that, in order to expand the didactic capabilities of the device, the second unit is entered into it memory, the second unit of comparison, the second element OR, the trigger, the delay element, the three groups of elements AND, the group of triggers and the group of elements OR whose inputs are connected to the corresponding outputs of the second group of the register ad ENA, and outputs - with R-inputs of the respective flip-flops  the groups whose S-inputs are connected to the outputs of the corresponding elements of AND of the first group, inverse outputs, to the first inputs of the corresponding elements of AND of the first group, and the direct outputs to the first Q inputs of the corresponding elements AND of the second group, the second inputs of which are connected to the output of the delay element, and outputs with the corresponding information inputs of the address register, the synchronization and installation inputs of which are connected respectively to the outputs of the first and second elements OR, the second inputs of the AND elements of the first group are connected with one output of the first comparison unit connected to the S-input of the trigger and one input The first OR element whose other input is connected to another output of the first comparison unit, the input of the delay element and the R input of the trigger are connected to one output of the second comparison unit, the other output of which is connected to the first input of the second OR element, the first input of which is the input of the device, the inputs of the second memory block are connected to the corresponding outputs of the third group of the address register, and the output, b to the first inputs of the corresponding elements AND of the third group, the second inputs Which are connected to the direct output of the trigger, and the outputs to the corresponding inputs of the first group of the second comparison unit, the inputs of the second group of which are connected to the corresponding outputs of the response input unit.