SU1683038A1 - Computer-aided system for checking radioelectronic devices - Google Patents

Abstract

The invention relates to electronic control systems and can be used to control tuning and acceptance tests of digital, digital-analog and analog CEA nodes. The purpose of the invention is to expand the functionality of the monitoring system by ensuring that specified sections of the text are looped, the normalized number of times and multiple cycles are embedded in the cycles, which allows to form complex time diagrams and superlong normalized signal sequences necessary for checking and controlling radio electronic devices of increased complexity. The possibility of accessing the subroutine during the test control is also implemented. The automated control system contains a control computing complex, a interface unit, an address decoder, a first memory block, a synchronizer, an interrupt block, a switch, a standard instrument block, a controller, an information interchange unit, three OR-NOT elements, two buffer registers, two D triggers, two multiplexers, four OR-AND-OR elements, an address counter, a selector, three AND elements, six IK-flip-flops, a cycle counter, two pulse shapers, an OR element, a comparison unit, two RS-triggers, a delay element, three the element OR-and- DOES NOT-two counter. Introduction to the device of the second memory block, the second multiplexer, the second buffer register, the comparison block, two counters, a number of RS- and IK-flip-flops and auxiliary logic elements, as well as appropriately organized communications allows two-way communication between the second block memory and loop counter, and thereby realize the mode of nesting loops into loops, as well as accessing the subroutines in the monitoring process. 3 hp ff, 7 ill. (L with CH 00 s about with 00

Description

The invention relates to control systems for digital, digital-to-analog and analog devices and can be used to control, set up and transient tests of digital, digital-to-analog and analog cells and blocks of complex

radio electronic devices: logical DAC, ADC, amplifiers, etc.

The aim of the invention is to expand the functionality of the automated control system by introducing the ability to access programs without disrupting the timing diagram of the exchange with the object of control and the possibility of nesting cycles into cycles to increase the total number of cycles when the test section is looped.

Figure 1 shows the functional diagram of the automated system for monitoring electronic devices; figure 2 is a functional diagram of the block of information exchange; fig.Z - functional diagram of the synchronizer; figure 4 is a functional block diagram interrupt; Figure 5 is a functional diagram of the switch and instrument cluster; figure 6 is a functional diagram of the controller; 7 is a timing diagram of the operation of the pulse distributor.

Automated system for controlling radioelectronic devices contains a control computer complex 1, an interface 2 block, an address decoder 3, an instruction memory block 4, a synchronizer 5, an interrupt block 6, a sync pulse bus 7, an input-output bus 8 for connecting a control object, a switch 9 , block 10 of standard instruments, controller 11, block 12 of information exchange, the first element OR-NOT 13, the first buffer register 14, the first D-flip-flop 15, the second D-flip-flop 16, the first multiplexer 17, the first element OR-AND-OR 18 , counter 19 addresses, selector 20, first The element 21, the second element OR-NOT 22, the first IK trigger 23, the counter 24 cycles, the second multiplexer 25, the second element IL AND-IL AND 26, the block 27 of the memory of cycles, the second element AND 28, the first driver 29 pulses, element OR 30, second buffer register 31, first comparison block 32, second pulse generator 33; the third element OR-NOT 34, the first RS-trigger 35, the second RS-trigger 36, the second IK-three / ger 37, the delay element 38, the first and second elements OR-AND-OR-NOT 39 and 40, the third IK -trigger 41. the third element AND 42, the third element OR-AND-OR-NOT 43, the fourth IK-trigger 44, the fourth element AND 45, the fifth and sixth IK-triggers 46 and 47, the third element OR-AND-OR 48 , the fourth element OR-AND- OR 49, the first and second counters 50 and 51. The information exchange unit 12 contains the test memory node 52, the first group of 53 elements OR-NOT, the lock register 54, the test register 55, the switch register 56, the register 57 protection The first group 58 elements OR, group 59 main amplifiers, the first element OR 60, the comparison circuit 61, the second and third groups 62 and 63 elements OR-NOT, the group 64 delay elements, the first multiplexer 65. the second element OR 66, the fourth group 67 elements OR, fault memory node 68, second multiplexer 69.

Synchronizer 5 contains master

generator 70, generator 71 single pulse, element 4И-OR 72, register 73 modes, pulse shaper 74, first IK-trigger 75, first element OR-NOT 76, first element AND 77, distributor 78

pulses, the second element OR-NOT 79, the first element AND-NOT 80, the second IK-trigger 81, the second, third, fourth and fifth elements And 82-85, the first and second D-triggers 86 and 87, the sixth element And 88 , register 89

5 of the delay code, the seventh element AND 90, the element OR 91, the delay counter 92, the second element IS-HE 93, the comparison circuit 94, the third IK trigger 95.

Block 6 (4) interrupt contains

0 the first inverter 96, the register of triggers 97 interrupt requests, the first group of elements AND 98, the group 99 elements of the prohibition, the element OR-NOT 100, the register of the trigger 101 interrupt enable,

5 second group 102 of elements AND, the first element OR 103, the encoder 104, the pulse shaper 105, the first and second delay elements 106 and 107, the amplifier 108, the second inverter 109, the driver

0 110 interrupt vectors, second element OR 111, amplifier 112.

Switch 9 contains the switching register 113, the first, second, third, fourth, and fifth groups of relays 114-118.

5 The instrument cluster 10 comprises a group of stimulating instruments 119 and a group of measuring instruments 120.

The controller 11 contains the information register 121. The control register 122,

0 output stage 123, block 124 loads, multiplexer 125.

Control computer complex 1 is designed to enter information into memory blocks 4.52 and 68, to output information about the control results from information exchange 12 to the display screen included in the computer complex. External magnetic memory (on floppy disks) of the computer complex

0 is used for long-term storage of control programs, a computer of a computer complex is also intended for analyzing and processing control results. Interface block 2 is intended for

5 of the electrical interface of the computing complex 1 with the corresponding blocks of the automated control system. Signals from block 1 to block 2 are transmitted using a bidirectional bus consisting of 16 lines.

address data and lines of interface signals: slaves (external devices); SIL (active device sync signal); Reset (set zero); Input (signal to accompany information input from a computer); CIP (passive device synchronization signal); CRA (interrupt request); PPR (provision of interruption), etc. Address data lines are aligned, i.e. the address and data are transmitted along the same time-separated lines. In block 2, at the input of each line there is a resistive divider designed to match the inputs of block 2 with the characteristic impedance of the communication line. The address register is intended for storing the address for the time of the elementary exchange cycle. If necessary, an entry in the address register is formed by combining the SIA and VU signals on the leading edge of the SIA signal. The address register is zeroed on the falling edge of the SI A-or signal. on a signal Reset from the computer of the computing complex. Signals Input and Output are collected in block 2 by OR and gates the decoder 3 addresses. The bi-directionality of the bus connection to the computer is accomplished by connecting the trunk transmitters with an open collector to this bus according to the OR circuit.

The address decoder 3 is designed to decipher the subscriber's address and form information recording signals into memory blocks, registers, counters in accordance with this address, to read their state and to form a number of auxiliary signals. The address decoder 3 is a decoder for 16 outputs with a gate input. The gated signal is received from the OR block 2 at the gating input. The outputs of the decoder, besides their primary purpose, are collected at OR. Next, this output signal is passed through the delay element and from the second output of the address decoder 3 is fed to the input of the interface 2 as a CIP signal.

The first instruction memory unit 4 is for storing control codes. To increase speed by eliminating the intermediate decoder, the control codes have a positional construction principle, i.e. certain commands or groups of bits in memory block 4 correspond to certain commands. The first group of inputs of the memory block 4 receives a 16-bit code from the data bus of the interface 2 block. The second group of inputs of the memory block 4 is designed to supply

the recording signals from the second group of outputs of the decoder 3 addresses. The third group of inputs of the memory block 4 is designed to supply the address code from the group of outputs of the counter 5 19 addresses for addressing the memory. The first group of outputs of the memory block 4 is designed to issue a control code either to the buffer register 14 or to the counter 51, depending on the presence of the control 0 signals. The second group of outputs of the memory block 4 is designed to issue a delay code in the synchronizer block 5. From the remaining outputs of the memory block 4, 5 control signals are removed.

The synchronizer 5 is designed to form a timing diagram of the exchange during the test control of digital devices. The master oscillator 70 generates a continuous pulse train that synchronizes the operation of the device,

Block b interrupt is intended for the organization of interaction between computers

5 computer complex 1 and the rest of the automated control system. The interrupt request register is designed to store interrupt request signals from various external sources. The highest priority is the top trigger. Further priority decreases downward. The highest priority has a cause associated with the operation of protection in block 12 of information exchange.

B The next priority has a cause associated with a malfunction in the test object during test control. The remaining causes of interruptions are measurement completion signals from

0 standard devices, after which the computer goes to the subroutine processing of measurement results. The priority chains, consisting of elements 98, 99 and 102, are intended to prohibit the interrogation of a request for interruption from reasons having the lowest priorities, if at a given moment in time there are reasons with a higher priority. However, the scheme is structured in such a way that the causes of interruptions with low priorities are not lost and are processed after the completion of the processing of causes with top priorities. An interrupt enable register, consisting of triggers 101, participates in the process of forming the interrupt vector and the CIP (OTV) signal in accordance with the standard timing diagram. The encoder 104 is designed to form an interrupt vector code in accordance with the priority number of the request signal. The vector is formed with the help of the elements AND NOT with

open collector, which are connected to the data bus according to the OR circuit. The interrupt vector is fed to the 8 lowest data bus bits in accordance with the standard requirements of the organization of interrupts in a computer. In the zero, first, fifth, sixth, and seventh bits of the vector, a permanent code is stitched. If necessary, a code from the buffer register can be fed to these bits and thereby modified the vector, i.e. handle more causes of interruptions. The shaper 105 pulses according to a negative differential produces a pulse of zeroing of the register 101 after the end of the output of the interrupt vector in the computer.

The bus 8 is connected to the control object, which interacts with the automated control system through the switch 9.

Switching register 113 controls five relay groups. FIG. 5 shows the connections between the outputs of the switching register 113 and the relay coils. The relay group 114 is designed to connect the digital channels of the control object to the IF exchange unit 12. If any channels of the control object are digital, then the switching contacts of the relay 114 of these channels are in the upper position, and if they are analog, then in the lower positions. A relay group 116 connects the necessary contacts of the test object to the bus of stimulating devices. A relay group 115 connects a specific stimulating device to the control object. Standard digital remote control devices are used as stimulating devices.

Relay group 118 connects the specified contacts of the test object to the meter bus, and relay group 117 connects a specific measuring device. As measuring devices 120, standard measuring devices with digital remote control are used.

The controller 11 is designed to control devices with digital remote control. Control register 122 is configured to control the output stage 123. A load unit 124 serves to electrically match the communication lines. For communication lines made with a twisted pair of wires having a characteristic impedance of 125 ohms, each line is loaded onto a 180 ohm / 360 ohm resistive divider. For the KOP interface, the divider has a resistance of 1 kΩ / 3 kΩ in accordance with GOST.

The information exchange unit 12 is intended for organizing test control of digital objects and performs the following main functions: storing the entire test control program; switching of inputs and outputs of exchange channels; storing and delivering the current test set to the control object; blocking control results for specified channels; protection of the output stages against

0 short circuit at the input of the control object; comparison of control results with reference codes and registration of comparison results; issuing to the computer of the contents of all the registers of the block, RAM and results

5 control, as well as control codes.

The test memory block 52 is designed to store test, interlock and switching sets. The block 52 is addressed during operation by means of the counter 19 of the address. Interlock registers 54, test 55, switching 56 And protection 57 are implemented on TM8 530 or 533 series microcircuits, Register 54 is designed to lock the record

5 comparison results in the fault memory block 68. When installing its corresponding bits in the unit at the corresponding outputs of the second group of 62 elements OR NO, there will be zero potentials regardless of

0 comparison results. Consequently, zeros will be written to these bits of the fault memory block 68 regardless of the comparison results. Register 55 is designed to store the current test set, which is issued to the control object through the trunk amplifier 59 with three output states. In addition, the same code goes to the first inputs of the comparison circuit 61, the second inputs of which are connected

0 with the outputs of the trunk amplifiers 59 and the I / O bus to which the test object is connected. If the trunk amplifier 59 is in the third state, the signal at the second inputs of the comparison circuit 61 is uniquely determined by the state of the output of the test object. The reference codes arrive at the first inputs of the comparison circuit 61. If the trunk amplifiers are in the signal output mode, then in the comparison circuit 61, the codes issued to the control object (output signals of the trunk amplifiers 59) are compared with the codes stored in the corresponding register bits 55 te5. Switching register 56 is designed to control trunk amplifiers 59 through a group of 58 OR elements. If s of this bit of switching register 56 is written 0, then a single potential arrives at the control input of the output stage 59 and the stage is in the third state, i.e. This channel is in the mode of receiving information from the control object. A group of trunk amplifiers 59 are also controlled from the protection register 57. The point of such control is that if any output stage 61 is switched to the signal output mode (i.e. one is recorded in the corresponding switching register register 56), then in the case of a short circuit on the body at the control object when issuing it over this channel of the unit, the comparison circuit 61 will register over this channel of incomparability, i.e. gives zero potential. Thus, at both inputs of the corresponding OR-NOT element from the group of 53 OR-NOT elements there will be zero potentials and, in this register of the protection register 57, a unit will be written that will transfer this output stage 61 to the third state, in which the short circuit exit will not disable it. The multiplexer 65 is designed to record information into the fault memory node 68 either over the X channel from the data bus (in self-monitoring mode) or over the Y channel from the comparison circuit 61 through a group of 62 OR-NOT elements (in the operating mode). Failure memory node 68 is designed to record results in it compared to each test set. If the control object is intact, all its bits on all test sets will have zeros. The multiplexer 69 is designed to transmit to the computer the contents of all registers and memory blocks of block 12. A check code (alternating zeros and ones) is rigidly fed to one group of its inputs to check the connections of the multiplexer outputs to the computer channel. Its inclusion in the channel is carried out by means of elements with an open collector (not shown). The first buffer register 14 is designed to write an address code into it, which is then rewritten into address counter 19 via multiplexer 17 in loop modes, conditional and unconditional jumps, and so on. Inputs V1 and V2 work on OR and allow the recording of information in the register on a signal arriving at its C-input.

Triggers 15 and 16 are designed to transfer the address 19 counter to the parallel code recording mode in the unconditional jump and loop modes. Counter 19 is switched to the parallel code recording mode when a single potential arrives at its V input from element 18.

The multiplexer 17 is designed to supply to the information group of inputs of the counter 19 the address code of the address to be written.

its parallel code. The address code can be transmitted either from the data bus (from the block 2 of the conjugation), or from the buffer register 14, or from the counter 50.

The address counter 19 is intended to address all of the memory blocks included in the device. The counter works both in the mode of sequential counting and in the mode of recording the parallel code. The mode of operation is controlled by applying a control signal to the V input of the counter. A single signal at input V sets the counter to the parallel code recording mode, and zero to the serial counting mode. The counter is synchronized by OR from either the first pulse of the synchronizer (pulse distributor) or from the signal generated by the address decoder.

The selector 20 is designed to organize the reading of the contents of the counter 19 address. The first inputs of the microcircuit provide signals from the bits of the counter 19. The second inputs are combined, and the reading signal from the decoder 3 is applied to them.

The trigger 23 is designed to control the operation mode of the counter for 24 cycles. If the trigger 23 is in the Zero state, then the counter 24 operates in the parallel code recording mode. When the trigger is set to 23 in the Unit, the counter operates in the sequential counting mode.

The multiplexer 25 is designed to write to the second memory block 27, either the contents of the 24-cycle counter, or any initial code directly from the data bus through the 2-gate unit. The element OR-AND-OR 26 is intended to control the read / write mode in the second memory block 27. If the output of the element 26 has a zero signal, then the memory block 27 is in read mode, and if the unit is, then it is in write mode.

The second cycle memory unit 27 directly participates in the process of organizing the insertion of cycles into cycles. Its necessity is determined by the fact that when the number of cycles is more than one and when passing from higher cycles to lower ones, information about the number of higher cycles in counter 24 is lost. However, it is rewritten in memory block 27, and then at the right time is rewritten again to the counter of 24 cycles, and the processing of this senior cycle is resumed.

Through the element 28, the number of cycles code is written to the second buffer register 31.

The pulse shaper 29 generates a pulse by a positive differential

input signal. This impulse is necessary to add a +1 to the counter of 24 cycles after the parallel code is written to it and it is switched to the sequential counting mode.

The second buffer register 31 is designed to memorize the number of cycles code for its subsequent comparison with the current value of the 24 cycles counter in the comparison block 32.

The shaper 33 generates a short positive pulse when the code in register 31 and the counter 24 are equal. This pulse sets the trigger 35 to one and through the OR-HAY 34 element the counter of 24 cycles is turned over by the counter.

The trigger 35 when installing it in the unit blocks the translation of the counter 19 addresses in the recording mode of the parallel code, thereby providing an exit from the cycle. In addition, after the trigger unit 35 is set to zero, the trigger 41 is reset.

The trigger 36 is designed to transfer the address counter 19 to the parallel code recording mode, for example, to set an initial address in the counter 19.

The trigger 37 is designed to transfer the address counter 19 to the parallel code recording mode when organizing the transition to subroutines.

A delay element 38 is needed to eliminate races when switching triggers 41 and 46 to avoid the appearance of spurious pulses at the clock inputs of counters 50 and 51.

The element OR-AND-OR-NOT 39 is intended for resetting the trigger 46, and the element OR-AND-OR-NOT 40 is the trigger 41. The trigger 41 is intended for blocking the operation of the counter 51 (the counter of the subroutine sets) in the case there are cycles (for example, if pulse trains are formed in the subroutine). If this is not foreseen, then at each cycle cycle all the looped sets will be counted by the counter 51, as a result of which the output from the subroutine will not occur in the specified place.

Logic element AND 42 serves to set the buffer trigger 44 by the command of the Subroutine arriving at its second input from the fourth output of the first memory block 4 to the synchronizer pulse U 2 arriving at its first input. In addition, using the same signal combination, the start code is recorded in counter 51 (sub-program set counter) via element 49.

Element 43 is intended for zeroing triggers 44 and 47, and element 45 is dsh

install the trigger 47 at its sync input and write the parallel code to the counter 50 through the element 48.

Trigger 44 is a buffer and serves

to control trigger 46, and in combination with trigger 47, to control counter 50, transfer it at the right time from parallel recording mode to sequential counting mode.

0 Trigger 46 controls the operation of counter 51, also translating it at the right time from parallel recording mode to sequential counting mode.

Counter 50 is intended to be recorded in

5, it is the address from which the transition to the subroutine is made (recording is done by a parallel code), after which the counter 50 is transferred to the sequential counting mode (by setting to

0 trigger 47) and a + 1 is added to its contents. Thus, the return address code from the subroutine is in the counter.

Counter 51 is for counting.

5 of the number of sets in the subroutine and allows the subroutine to be passed in whole or in any part thereof. First, a parallel code records the code for the number of subroutine sets. Then he

0 is transferred to sequential counting mode and counts until overflow. The overflow signal is a subroutine exit signal. In this case, the address counter 19 is rewritten via multiplexer 17.

5 code from counter 50, which is the return address code. The number written to counter 51 (the code of the number of sets of the subroutine) is determined by the formula

P - N,

0 where P is the number recorded in the counter 51 (decimal);

k is the number of bits of the counter 51; N is the required number of sets in the subroutine (decimal).

5 The device operates as follows.

Consider first the process of controlling a digital device in Step mode, i.e. when, after issuing a digital code corresponding to one test set to the object, receiving the control object's response and analyzing the control results, the check stops. The resumption of verification is carried out

5 on the next Start signal. Thus, the entire test program can be passed with stops after each test set.

Since the procedure for writing information to external devices (including memory blocks) is standard, a test program with control codes is stored in memory. To set the Step mode, it is sufficient to set the second register of the synchronizer register 73 to one. Then, using the Start signal from the fifth output of the decoder 3 to the fourth input of the synchronizer 5, the GOI 71 of the synchronizer 5 generates a single pulse, which sets the trigger 75 to one. at this point in time, the pulse distributor 78 begins to form a four-pulse timing diagram in accordance with FIG. 7.

The pulse U 1 from the first output of the synchronizer 5 performs the following actions.

Zeroed through the element OR 91 counter 92 delay (in this case confirms its zeroed state). Similar actions are performed on trigger 23 through member 22.

Increments the counter-19 addresses since the trigger 15,16,36 and 37 are at zero and the input V of the counter 19 through the element 18 receives a zero potential (assume that this is a normal test set without cycles and transitions).

Pulse U 2 performs the following actions:

Generates at the output of the element 82, the signal recording the delay code in the register 89.

Forms at the outputs of one of the elements 83-85, depending on the command received at their second inputs, write signals to the test register 55, the lock register 54, the switching register 56. Suppose that the considered set is a test one. Then, the command arrives at the second input of the element 83 and, by the pulse U 2, at its output a signal is written to the test register 55.

Sets to one (or to zero) trigger 86, depending on the signal at the input of trigger 86. If a poll is required for this test set, then one from block 4 of memory is fed to the input of trigger 86.

The trigger (87), which generates a sync pulse to synchronize the oscilloscope, resetted (in sync).

Sets (under certain conditions) to the unit trigger 81, which allows the passage of clock pulses through the element 88 to the counting input of the counter 92 delay. A prerequisite for setting flip-flop 81 is the presence in register 89 of any non-zero delay code. In this case, at least one of the inverse outputs of the register will have zero potential, which will determine the presence of a single potential at the output of element 93.

Since the second register bit 73 was previously set to one (Step mode), then through element 72, the driver 74 and element 76 reset 5 trigger 75.

Thus, one complete cycle of the device operation will end. At the same time, the next cycle will be resumed only after the trigger 75 is set by the Start-up signal.

0 output decoder 3.

In the Auto mode, the same actions are performed. The difference is that the second register of the 73 register contains Zero, which corresponds to the Auto5 mode, therefore, the U 4 pulse will not reset trigger 75, and the distributor 78 will form the next four pulse cycle. work. In this case, the reasons for stopping U 4 pulse are the signal

0 Protection coming to the third input of the synchronizer 5 from the second output of the exchange unit 12; the Failure signal arriving at the second input of the synchronizer 5 from the first output of the exchange unit 12, and the Stop command,

5 arriving at element 72 (first group of inputs) from the second group of outputs of memory block 4.

The Stop command and the signal Fault are blocked in the Cycle mode by setting the first digit of the first register to 73

Let us consider in more detail Cycle mode. There are two variations of this mode in the device: an unnormalized, infinite loop, when a given region

5, the test is repeated until a forced stop is made by zeroing the trigger 75; the normalized cycle, when the specified part of the test is repeated a specified number of times, after which the exit from the cycle and the transition to the further execution of the test program are performed. The non-normalized cycle is used when troubleshooting in the control object, when on the oscilloscope screen it is necessary to observe a timing diagram when passing a specified portion of the test. At the same time, to synchronize the oscilloscope on the bus 7 of the sync pulse, an oscilloscope synchronization pulse is generated, corresponding to the time specified in the test set. The non-normalized cycle is performed as follows. In the memory cell of the memory block 4, corresponding to its third output, is pre-recorded

5 unit (Cycle 1 command) at the address corresponding to the set number from which it is necessary to make a transition to the specified (minor) address. In addition, in the memory cell of block 4 corresponding to the first group of its outputs, the address code to which it is necessary to go to (the return address code) is recorded at the same address. As soon as the test program reaches the address in which the Cyclic 1 command is written, the input potential V 2 of register 14 receives a single potential that allows the parallel code to be written to it (the resolution inputs V 1 and V 2 of register 14 operate OR). A pulse U 2 arriving at the synchronous input of register 14 from the second output of synchronizer 5 will register in register 14 a return address code from the first group of outputs of memory block 4. The impulse U 3 of the synchronizer 5, coming from its fourth output to the synchronous input of the trigger 15, will be set to one and, through element 18, will transfer the address counter 19 to the parallel code recording mode, Impulse U 4 of the synchronizer 5 will not perform any actions. Then, synchronizer 5 will start forming the next microcycle from pulse U 1. Since triggers 36 and 37 are at zero, channel M is activated at multiplexer 17, therefore, by pulse U 1, address return code 19 is rewritten from address register 19, i.e. . go to the specified address of the test program. Thus, the program section between the return address and the address where Cycle 1 is recorded will be repeated until the trigger 75 of synchronizer 5 on the common circuit YO (the first input of synchronizer 5) is forced to be reset by dialing the console of the computing complex of the address corresponding to the first output of the decoder 1. With the appropriate software on the console, instead of the specific physical address, the command mnemonic YO is typed or simply the corresponding key.

The normalized cycle is more complex. Consider the process of forming normalized cycles with nesting cycles.

Two teams, Cycle 2 and Cycle 3, take part in the formation of such cycles. Team Cycle 2 corresponds to a single potential at the second output of the first memory block, and Cycle 3 to a command corresponds to a single potential at the first output of the first memory block. The Cycle 4 command is located in the memory cell of the memory block 4 at an address one unit larger than the Cycle 2 command, i.e. in the next for Cycle 2 command cell memory. On the command Cycle 2 with the arrival of the pulse U 2 from the second output of block 5 to the second buffer register 31 from the second block 27 of memory, a code corresponding to the required number of cycles will be written. In addition, the return address code is written to the first buffer register 14 of the first memory block 4. Impulses U 3, U 4 synchronizer

5 will not perform loops in this set of actions. In the next set, on the first output of block 4, memory is set to command Cycle 3. By the time of arrival of the pulse U 2, the trigger 23 is at zero, which

0 determines the operation of the counter 24 in the recording mode of the parallel code. Thus, the impulse U 2, passing through elements 21 and 30, with its leading edge will record in the counter 24 the original current value of the quantity

5 cycles - number zero. By its falling edge, pulse U 2 will set trigger 23 to one, which will transfer counter 24 to the sequential counting mode, Pulse U 3 from fourth output of synchronizer 5 will set trigger one to 16. Since trigger 35 is at zero and from its inverse output If the input of element 18 is a unit, then the counter 19 of the address is switched to the recording mode of the parallel code E (which is recorded there in the next micro-cycle of the synchronizer 5). The impulse U 4 from the fifth output of the synchronizer 5, through element 26, overwrites the contents of the counter 24 cycles into the second memory block 27. It will be

0 code number 1, which corresponds to the fact that this part of the test will take place one 2 times. Writing the code from memory block 27 to counter 24 cycles on pulse U 2, transferring counter 24 to sequential counting mode, adding one to its contents and rewriting the new code value of counter 24 to memory block 27 on pulse U 4 occurs during one microcycle of synchronizer operation 5. Further, this test section

0 will be repeated n times until the contents of the counter of 24 cycles become equal to the contents of the second buffer register 31. If these codes are equal, the comparison unit 32 will form a single potential,

5 in which the driver 33 will generate a pulse. This impulse will reset the counter 34 and set the trigger 15 to unit. The zero code of the counter 24 will be rewritten with the impulse U 4 into the memory block 27, i.e. formation pattern

0 cycles will be reset. The zero potential from the output of the trigger 35 through the element 18 will transfer the address counter 19 to the sequential counting mode, i.e. in the next micro-cycle of operation of the synchronizer 5, a unit will be added to the contents of counter 19. The loop will exit, the test program will continue. In the same way, the next cycle will be formed from K repetitions of some other part of the test program. During the formation of such simple cycles, the bilateral exchange of information between the counter 24 and the second memory block 27 does not impart a new quality to the circuit.

However, when forming complex cycles with investments of small cycles into larger ones, such information exchange between the memory unit 27 and the counter of 24 cycles is of fundamental importance. So, at the first transition along the No branch, when forming a large cycle from K repetitions, information about the current value of K in counter 24 is lost, However, it will remain in block 27 and by the time the next entry into cycle K will restore the current value of the number of cycles in counter 24 Thus, in the counter 24 each time, the correct current value of the large cycle will be restored. The number of attachments is determined by the volume (depth) of the memory block 27.

In the process of test control, it becomes necessary to repeatedly refer to individual sections of test programs, and the length of these sections may be different each time. To save memory, it is advisable to arrange part of the test as a subroutine and, in the process of test control, refer to this subroutine (or subroutines). In the proposed device, this problem is solved as follows. The transition to the subprogramme is carried out in two sets in series with each other (as in the case of the formation of normalized and nested cycles). The subprogram command corresponds to one at the fourth output of memory block 4. When this command is received by the pulse U 2 through the element U 2, the trigger 44 will be set to one. In addition, since the trigger 16 is at zero, the counter 51 is in the parallel code recording mode and through the element 49 the code of the number of subroutine sets arriving at its information inputs from the first group of outputs of the memory 4 will be written. The pulses U 3 and U 4 of the synchronizer 5 in this micro cycle of the synchronizer operation for forming the subroutine are not used. In the next microcycle of operation of the synchronizer 5, the command Cycle 1 should appear at the third output of memory block 4. By this command and by pulse U 2, register 14 of block 4 of memory will write the code of the address of the start of the subroutine and trigger 15 is set to one. In addition, since trigger 44 in the previous set was set to one, pulse U 2 will pass through the element

45. Since the trigger 47 is still at zero, then the counter 50 is in the parallel code recording mode, and the pulse U2 passes further through the element 48, with its front 5 edge it will record the current state of the address counter 19 in the counter 50. pulse U2 trigger 47 is set to one, thereby transferring counter 50 to counting mode and allowing passage of pulse U 3 through delay element 38 and element 48, which will add one to the code previously recorded in counter 50. Thus, in counter 50 will be the address code, per unit bo even more than the one from which the transition to the subprogramme is being made. This will result in a & return after passing through the subroutine. main test program. The trailing edge of the U 3 pulse will be set to one trigger

0 46, which will cause the transfer of the counter 51 to the counting mode and allow the passage of the pulse U 3 through the element 49 to the counting input of the counter 51. However, in this micro-cycle of the synchronizer 5 counting

5 there will be no pulse at the input of the counter 51, since the trigger 46 is set by the falling edge of the predetermined pulse U 3. The pulse U 4 from the fifth output of the synchronizer 5, having passed through the element 43, will reset the triggers 44 and

0 47. At this, the preparation of the transition to the subroutine is completed and in the next micro-cycle of synchronizer 5 operation, according to the impulse U 1 from the first output of synchronizer 5, the code will be written to the address counter 19

5 addresses of the transition from the buffer register 14 through the multiplexer 17. The parallel recording mode causes the trigger 15, which is set to one in the previous micro-cycle of the synchronizer 5. With

At this time point, the subroutine will start to execute. In each microcycle of operation of the synchronizer 5, the pulse U 3 of the synchronizer 5 will add one to the counter 51, i.e. counter 51 will count sets of sub5 programs. However, if there are cycles in the subroutine, TO counter 51 will read them, and the actual value of the number of subroutine sets will be distorted. To prevent this occurrence, the third IK-trigger 41 is intended. When installed in a cycle of 1 on the delayed pulse U 3 (on its falling edge), this trigger will block further receipt of the pulses U 3 on counter 51 through element 49. Thus, counter 51 counts looped sets only once during the first loop pass. Trigger 41 is reset at the end of a cycle with a U 4 pulse from the fifth output of synchronizer 5, when trigger 35 is set to one.

After the counter 51 counts a predetermined number of subroutine sets, it will overflow and the output will transfer a pulse, which sets trigger 37 to one. This trigger allows pulse U 4 of synchronizer 5 to pass through element 39 to reset trigger 46. In addition, trigger 37 translates the address counter 19 via element 18 into parallel recording mode, and on the control inputs of multiplexer 17 there is a code activating channel z of multiplexer 17. Thus, in the next micro-cycle of synchronizer 5 operation, m U 2 synchronizer 5 into the counter 19 of the address will be written the code from the counter 50 and further execution of the test program will begin with the address, one unit larger than the one from which the subroutine was entered.

If the control object requires supplying analog signals to its inputs and measurement at its outputs, this is done through the operation of blocks 6, 9, 10 and 11. Digital signals can be fed to the digital inputs of the control object. The supply and measurement of analog signals is performed according to the following algorithm. First, the signal transmission direction is set in the controller 11 by writing the corresponding code to the control register 122. Next, a register is written to the register 121, which, through appropriately connected channels of the output stage, is fed to the control inputs of the instrument cluster and sets these instruments to the desired operation modes. All control and other codes come from the data bus, i.e. from the first group of outputs of block 2 conjugation. Next, the control code in the register 113 of the switch 9 is written, in accordance with which the relay groups 114,115,116,118 and 119 are switched. The relay group 114 disables the analog inputs and outputs of the control object from the exchange unit 12. A relay group 116 connects the desired analog inputs of the test object to the bus of stimulating devices, and a relay group 115 connects the desired stimulating device to this bus. Figure 5 shows only one bus of stimulating devices. In general, there may be several such bus bars (i.e., several parallel relay groups 116) to simultaneously connect to different analog inputs of the control object. Standard devices with digital remote control are used as stimulating devices, for example, power supplies B5-43 ... B5-49, generators G5-75, G5-82, G4-158, etc. Relay group 118 connects the necessary, analog contacts of the test object to the meter bus, and relay group 119 connects the desired meter to this bus. After the described presets and commutations, a Start signal is output through the corresponding register bit 121 and the corresponding channel of the output stage 123, through which the measuring device begins to measure this parameter. The computer of the computing complex at this time may be engaged in processing the results of previous measurements or may be in standby mode. At the end of the measurement, the measuring device generates a signal at the end of the measurement, which from the corresponding output of the second group of outputs of block 10 goes to the corresponding input of the first group of inputs of block 6 interrupts. The priorities of the measuring devices are chosen by the user. When a signal arrives at one of the inputs of the first group of inputs of interrupt block 6, the corresponding trigger 97 is set to one, and if the channels with a higher priority are free, then a single signal from the output of the corresponding trigger 97 goes to the D input of the corresponding trigger 101, closes the corresponding element 99 and through it all the channels with a lower priority, and through elements 111 and 112 of block 6, form a TPD signal (interruption request), which through the block 2 of the conjugation enters the computer of the computing complex. From this point in time, the computer generates a standard interrupt processing timing diagram. The timing diagram starts with the output of the DZP signal (input), which goes to the corresponding input from the second group of inputs of block 6 and further to the C inputs of the trigger 101. By this signal, the corresponding trigger from the group of trigger 101 will be set to one. At the same time, the corresponding input of the encoder 104 is activated and the corresponding code is formed at its output, which, however, does not pass to the output of block 6, since the group of elements of the driver 110 is closed. In addition, the trigger 101 confirms the prohibition of signal propagation through the element 99 of its channel through the lower element 102 of its channel and allows the signal to pass through the upper element 102 of its channel. Further, with some delay in relation to the signal of the computer DZP, the computer generates an SPR signal (interrupt provision), which:

Flashes the trigger 97 (trigger TPR) of the channel. Triggers 97 with lower priorities will not be reset, since the propagation of the SPR signal through the lower elements 102 is prohibited. Thus, interrupt requests with lower priorities are not lost and will be processed upon completion of the processing of interrupts with higher priorities.

Through the upper element 102 of this channel, it enters the corresponding input of the OR element 103 and then, after passing through elements 106 and 108, enters the output of block 6 as a signal of the TOV (CIP). The TSS signal, coming through the interface 2 in the computer, informs it that the interrupt vector has been formed.

Opens interrupt vector shaper elements 110. 107 delays are necessary in order to ensure reliable reception of the interrupt vector in a computer, since the reception circuit is built on latch type triggers and the trailing edge of the OTV signal must end before the interrupt vector is removed. ,

After this, the computer proceeds to the processing of the interrupt subroutine, which, in general, consists in receiving data from the measuring device and comparing the measured value with the specified tolerances.

Claims (4)

1. Automated control system of electronic devices. containing a control computing complex, an interface unit, an address decoder, a command memory, a synchronization unit, an interrupt unit, a switchboard, an instrumentation unit, a controller, the information exchange unit, the first and second elements OR NOT, the first buffer register, first and second D-triggers, first multiplexer, OR-AND-OR element, address counter, selector, first AND element, first IK trigger and cycle counter associated with its first input to the first output of the first IK trigger, inverse output which is connected to its 1-input, K- the input is grounded, the sync input is connected to the output of the first element AND, and the reset input is connected to the output of the second element OR NOT connected to its first input with the first output of the synchronization unit and the first synchronization input of the address counter, and the second input to the first output of the address decoder and the reset inputs of the synchronization unit, the information exchange unit, the switch, the interrupt unit, the controller, the first element OR NOT, the reset input of the first buffer register, the synchronous input which is connected to the second output of the synchronizer, the second input of the first element OR NOT and the first input of the first element I. The second input of which is connected to the D input of the second D-flip-flop and the output of selecting the source of the loop sequence address of the first memory block, enable output write down the reference code which is associated with the first input of the write access of the first buffer register, and the output of the write permission of the subroutine's address with the D input of the first D-flip-flop and the second input of the write permission of the first buffer register, the output group to Is connected to the first group of inputs of the first multiplexer, and the group of information inputs to the first group of outputs of the command memory block connected by the second group of outputs to the first group of information inputs of the synchronizer, and the first group of information inputs to the first group of outputs of the interface block, the second the group of inputs of the first multiplexer, the second group of information inputs of the synchronizer and the first groups of information inputs of the information exchange unit, the switch and controller, the second group of address inputs in one of which is connected to the first group of outputs of the address decoder, the third information group of inputs is to the first group of outputs of the instrument, the first group of information inputs-outputs of which is associated with the first group of information inputs of the switch, the second group of outputs with the first group inputs of the interrupt unit, and the second group of information inputs / outputs - with a group of information inputs / outputs of the controller connected by a group of information outputs to the group of information outputs of the interrupt unit, groups information outputs of the selector, a group of information outputs of the information exchange unit and a group of information inputs of the interface block, information inputs / outputs of which are associated with information inputs / outputs of the computing complex, a readiness input - with a readiness output preparing an interrupt block and a second output of the address decoder, and the second group of information outputs - with the second group of information inputs of the controller and the group of information inputs of the address decoder connected by its third output to to the input of the address of the selector, the fourth output to the second synchronization of the address counter, the second group of information outputs to the group of inputs write-read the first memory block, the third group of outputs to the group of inputs for controlling the reading-writing of the information exchange unit, and the fourth group of outputs to the group of address inputs of the switch, the second group of information inputs-outputs of which are connected to the group of information inputs-outputs intended for the device to connect the control object, and the third group of information inputs / outputs - with the group of information inputs / outputs of the information exchange unit, the synchronous input of the protection record of which is connected to the fifth output synchronizer, and the protection and malfunction signaling outputs, respectively, with the first and second synchronizer blocking inputs connected by the information source output group to the information source selection input group, and the recording control output group to the recording control input group of the information exchange unit, the synchronization output is the device sync output, the start input and the recording input are connected respectively to the fifth and sixth outputs of the address decoder, and the fourth output is connected to the synchronous inputs with respectively, the first and second D-flip-flops, the reset inputs of which are connected to the output of the first element OR-NOT, are the direct outputs respectively to the first and second inputs of the first element OR-AND-OR connected by their output to the control input of the address counter, the information group the inputs of which are associated with the output group of the first multiplexer, and the output group with the group of information inputs of the selector, the group of address inputs of the command memory block, and the group of address inputs of the information exchange unit, of the functionality of the automated control system by introducing the possibility of accessing the programs without disturbing the time diagram of the exchange with the control object and the possibility of nesting cycles in cycles to increase the regional number of cycles when the test section loops, contains a second multiplexer, second, third and fourth elements - ILY. the memory block of cycles, the second, third and fourth elements AND, the first and second pulse formers, the element OR, the third element OR NOT, the second buffer register, the first comparison block, the first and second RS-triggers, the second, third, fourth, n th sixth IK-triggers, the delay element, the first, second and third elements OR-AND-OR-EE, the first and second counters, and the outputs of the signaling protection and fault of the information exchange unit are connected to the first and second inputs of the interrupt unit, respectively, the fifth, sixth and the seventh outputs of the address decoder are connected respectively to the first input 0 of the second element OR-AND-OR, the installation input of the second RS-flip-flop and the first reset input of the second RS-flip-flop, the second reset input of which is connected to the first input of the first OR-NOT element, and my output 5 to the third input of the first OR-element And-OR, and the inverse output to the first address input of the first multiplexer, the third group of information inputs of which is connected to 0 by a group of outputs of the first counter, and the second address input with an inverse input and I- input of the second I “trigger, whose input is grounded, the reset input is connected to the output of the first element OR NOT, the synchronous input to 5 to the output of the second counter, and the direct output to the fourth input of the first element OR-AND-OR, the fifth input of which is connected to the first input of the second element OR-AND-OR-NOT and the inverse output of the first RS0 trigger, the installation input of which is connected to the output of the second shaper, the first reset input - to the first inputs of the second, third and fourth elements And, and the second input of the second element And to the output 5 enable the recording of the reference code of the first memory block, the output of recording the starting address of the subroutine of which is connected to the second input of the third AND element connected by its output to the first input of the fourth OR-AND-OR element to the synchronous input of the fourth IK trigger, whose K input grounded, 1 input connected to the inverse output, direct output to the i-output of the sixth 5 IK-flip-flops, the second input of the fourth element I and the first one 1 input of the second K-flip-flop, and the reset input - with the reset input of the sixth SK-flip-flop and the output of the third element OR-AND-OR-NOT connected by its first input to the first input of the first, the second input of the second element OR-AND-OR-NOT and the first input of the first element OR-NOT, the second input to the third input of the fourth element AND, the first input of the third element. OR-AND-OR, the second input of the first IK-trigger and the D input of the first D-trigger, and the third input to the second input of the second OR-AND-OR element, the first output of the synchronization unit, the third input of the second the OR-AND-OR-NOT element and the second input of the first OR-AND-OR-NOT element, the third input of which is connected to the direct output of the second IK flip-flop, and the output to the reset input of the first IK flip-flop, K-input which is grounded, and the direct output is connected to the control input of the second counter and the second input of the fourth element OR-AND-OR, the third input of which is connected to the input of the delay element and the synchronous input of the second D-trigger, the output to the synchronization input of the second counter, and the fourth input - with the inverse output of the third IK-flip-flop, the reset input of which is connected to the output one second OR-AND-OR-NOT element, the K-input is grounded, the l-input is connected to the D-input of the second D-flip-flop, and the sync input is connected to the output of the delay element, the sync input of the fifth IK-flip-flop and the second input of the third OR element - OR-OR, connected by its third input to the output of the fourth element I and the synchronous input of the sixth IK-flip-flop, output to the synchronous input of the first counter, and the fourth input to the direct output of the sixth K-flip-flop, the K-input of which is grounded, and the direct output is connected to the control input of the first counter, the group of information inputs of which are connected inen with an address counter output group and a cycle memory address input group, and a reset input with a second counter reset input, a group of information inputs of which is associated with a pee group of outputs of a command memory block, and a reset input with the first input of a third the element OR is NOT, the second reset input of the first RS flip-flop and the reset input of the second buffer register, the synchronous input of which is connected to the output of the second element AND, the output group to the first Group of inputs of the first comparison unit, and the group of information inputs to the information group the cycle counter and the group of outputs of the cycle memory unit whose recording input is associated with the output of the second element OR-AND-OR, and the group of information inputs is connected with the group of outputs of the second multiplexer, the first group of information inputs of which are connected to the group of information inputs the outputs of the interface unit, the second group of information inputs — with the output group of the cycle counter and the second group of inputs of the first comparison unit, and the control input — with the third input of the second OR-AND-OR element and the resolution input of the first cp unit connected to its output to the first input of the second pulse shaper, the second input of which is connected to the fourth output of the synchronizer, and the output to the second input of the third element OR NOT connected to the reset input of the cycle counter, its synchronous input associated with the output of the element OR connected by its first input to the output of the first element I, and the second input to the output of the first generator, the input of which is connected to the direct output of the first 1K flip-flop. 2. Automated system according to claim 1, characterized in that the information exchange unit contains a memory node of the test, the first, second and third groups of elements OR-NOT, the lock register, the test register, the switching register, the protection register, the first, second and the third group of elements OR, the element OR, the group of trunk amplifiers, the comparison circuit, the group of delay elements, the first and second multiplexers and the fault memory node, whose address input is connected to the address input of the test memory node and is the address input of the block, information input to then connected to the information input of the test memory node and the first information input of the first multiplexer; the block record input is connected to the recording record node of the test memory node, the output of which is connected to the information inputs of the lock registers, test register, switching register, first information input of the second chip, the second , the third, fourth, fifth, sixth and seventh information ports are connected respectively to the output of the fault memory node, the outputs of the trunk amplifier groups and the first inputs of the circuit connected by the outputs of the security register, the first inputs of the first group of elements OR and the inputs of the element OR, connected together by the outputs of the register of blocking and the first inputs of the second group of elements OR — NOT, the direct outputs of the test register, the direct outputs of the switching register, the address input and output the second switch is, respectively, the address input of the source selection of the information block and the information output of the block, the recording entry of the test memory node, connected together the inputs of the OR-NOT element and the group of elements The gateways strobe the input of the second switch form the control input of the state of the block, the synchronous inputs of the lock register, test register, switching register and the second inputs of the second group of elements OR form the group of synchronized moves of the block, connected together the reset inputs of the lock register, test register, register the protection register is connected to the reset input of the unit, the inverse of the test register is connected to the second input of the comparison circuit and the information inputs of the trunk amplifier group whose resolution inputs are connected to the outputs of the first group of elements OR, the second inputs of which are connected to the inverse the outputs of the switching register and the first inputs of the first group of elements OR NOT, the outputs of which are connected to the information inputs of the protection register, and the second inputs to the outputs of the comparison circuit and the second inputs of the second group OR NOT, whose outputs are connected to the second information inputs of the first multiplexer and the inputs of the second OR element, the address input of the first multiplexer is connected to the output of the OR-NOT element, and the output to the information input of the fault memory node, whose recording inputs are connected to the outputs of the second group of elements OR, the output of the second element OR is the output of the presence of a block fault, the outputs of the group of trunk amplifiers are information inputs / outputs of the block, the synchronous input of the protection register is the synchronous input om block 3, The automated system according to claim 1, wherein the synchronizer includes a master oscillator, a single pulse generator, an AND-OR element, a mode register, a pulse driver, first, second and third IK triggers, first and second elements OR-NOT, first, second, third, fourth, fifth, sixth and seventh elements AND, first and second 0- triggers, register delay code, z-lemcht OR, delay counter-, first and second elements AND-NOT and circuit comparing the first, second information inputs, the synchronous input and output of which are connected respectively O with the output of the delay code register, the output of the delay counter, the output of the second NAND element, the input of the third IK- trigger, whose input K is connected to the common bus, the counting input is connected to the counting input of the delay counter and the output of the sixth And element, the reset input - with the reset input of the delay counter and the output of the OR element, the output with the first input of the second OR-NOT element, the second input of which is the reset input of the synchronizer and connected to the reset inputs of the mode register, the first and second D-flip-flops, the delay code register first in th first OR-NO element, a second input coupled with the output of the pulse shaper, and the output with the reset input of the first (K-flip-flop, input K of which is connected to the common bus, the inverse output — with the input I, the counting input — with the output of the generator of a single pulse, the input of the first element And, the second input of which is connected to the inverse output of the second K-flip-flop, the output - with the input of the pulse distributor, the third input with the synchronous input of the single pulse generator, the output of the master oscillator and the first input of the sixth element And, the second input of which is connected to the pr my exit the IK-flip-flop, whose input K is connected to the common bus, the sync-input - with the sync-inputs of the first and second D-triggers, and the first inputs of the second, third, fourth and fifth elements I, the second inputs of which, as well as the information inputs of the first the trigger, the delay code register, the first input of the first element AND- and the first input of the element AND-OR form the first information input of the synchronizer, the information input of the mode register is the second information input of the synchronizer, the synchronous input of the mode register is the recording input synchronizer mode, the single pulse generator start input is the synchronizer start input, the output of the second element AND is connected to the synchronization input of the delay code register, the inverse group of outputs of which is connected to the inputs of the second AND-NOT element, the first output of the pulse distributor is connected to the second input of the element OR and The first output of the synchronizer, the second output is the second output of the synchronizer, the third output is connected to the first input of the seventh AND element, and is the third output of the synchronizer, even Rotary output - connected to the second inputs of the 4I-OR element and the second input of the first AND-NO element and is the fourth output of the synchronizer, the output of the first AND-NE element is connected to the installation input of the second D-flip-flop, the inverse output of which is the fifth synchronizer output , the output of the first D-flip-flop is connected to the second input of the seventh element And, the output of which, together with the outputs of the third, fourth and fifth elements And form the first group of outputs, the output of the first bit of the mode register is connected to the inverse inputs of the second and t The second element of the fourth element of element 4I-OR is connected to the output of the second section of the mode register, the higher bits of which form the second group of outputs of the synchronizer, the third and second inputs of the first and second elements of element 4I-OR the second and third inputs of the synchronizer, respectively; the output of element 4I-OR is connected to the input of the pulse shaper. 4. Automated system according to claim 1, wherein the controller contains a control register, an output stage, a load unit, a multiplexer and an information register, whose information input is connected to the information input of the control register and is the first information input of the control The ler, sync inputs of the information register and the control register share the multiplexer address inputs form the controller control input, the information register reset register and the controller reset control register, the first multiplexer information input is the second information input of the controller, the output stage of which is connected to the information input / output of load unit and the second information input of the multiplexer, the output of which is the information output of the controller, the outputs nformatsionnogo register and control register are respectively connected to first and second inputs of the output stage. p ta.9 group of departures first group. 6 under 6 Vtor: group 4YuI I third Group vgov WITH 2nd Entry first. entrance thursday p ha L eight W a with Oj about 00 CD ifyana tii's FIG. 2 with so about with so (ABOUT G W & gOXg Tl / qgdm gffOJtg fcxg -cc / osh nnuiaduj (-nimjddgujfh Ouvttd evgdfft / gifowf pojr / qy in ° b niogoau QOgoig puu / irf 6Vyddli nujddw aore  nOQOWQ road eodoujf | EN 2fB g sh l B "C 3S 1Y §-g ed 8SOЕ891