SU1374232A1 - Device for interfacing computer with m external devices - Google Patents

Abstract

The invention relates to advanced technology and automation and can be used in various systems of automated control and automatic control. The purpose of the invention is to expand the range of external devices by increasing the information width q, 4eT transmitted to an external device. The device contains a computer communication unit 1, a communication unit with an external device and a switching unit 2, the computer communication unit contains three channel receivers 4-6, two groups of channel receivers 7, 8, two bus driver 12, 13 , two groups 19, 20 bus drivers, address register 15, decoder 16, trigger 18, comparison element 14, four AND-NOT elements 10, 11, 17, 21, delay element 9} the communication unit with an external device contains a channel receiver, channel transmitter group, switch, decoder, trigger group, register, AND-NOT element; the switching unit contains a channel receiver, two NAND elements, two NOT elements. 1 hp f-ly, 2 ill. (L

Description

00

and 1h9

WITH

to

The invention relates to computing and automation and can be used in various systems of automated control and automatic control.

The purpose of the invention is to expand the range of external devices by increasing the size of the information transmitted to the external device.

Figure 1 shows the block diagram of the device; figure 2 - timing diagrams illustrating the operation of the device.

The device contains (Fig. 1) a computer communication unit 2, a switching unit 2, communication units 3 with an external device.

Unit 1 of communication with a computer contains channel receivers A-6, channel groups 20

receivers 7 and 8, delay element 9, AND-HE elements 10 and 11, bus drivers (PF) 1.2 and 13, comparison element 14, address register 15, decoder 16, AND-NE element 17, trigger 18, bus form groups - 25 teli 19 and 20, the element AND-NOT 21.

The switching unit 2 contains a channel receiver 22, the element AND-NO 23, the elements NOT 24 and 25, the element AND-NOT 26.

was greater than or equal to 35. Any 33 lines of the first group of input-output 34 of block 3 are connected to the WU circuits intended for transmitting signals from the computer to the WU, and the remaining two lines are connected to the WU circuits intended for transmitting signals from the WU to the computer . The inputs of the first and second groups of channel receivers 7 and 8 from the address main line 35 of the computer are supplied (with), respectively, 9 older and 7 younger bits of the address / data of the main line of the computer. A group of device inputs 41 serves the nine-digit device address code. The output of the NE-21 element is connected to the SIP circuit (the response signal of the passive device) of the computer interface, the input of the channel receiver 4 is connected to the OUTPUT circuit of the computer interface, the input of the channel receiver 5 is connected to the IN input circuit of the computer interface, the input of the channel receiver 6 is connected to the SIL circuit (synchronization of the active device) of the computer interface, the input-output 42 of the device is connected to one of the address / data bits of the computer. Each output signal for the slave is generated with a separate software program.

Unit 3 communication with an external device 30 accessing a computer to one of the internal

0

five

0

five

was greater than or equal to 35. Any 33 lines of the first group of input-output 34 of block 3 are connected to the WU circuits intended for transmitting signals from the computer to the WU, and the remaining two lines are connected to the WU circuits intended for transmitting signals from the WU to the computer . The inputs of the first and second groups of channel receivers 7 and 8 from the address main line 35 of the computer are supplied (with), respectively, 9 older and 7 younger bits of the address / data of the main line of the computer. A group of device inputs 41 serves the nine-digit device address code. The output of the NE-21 element is connected to the SIP circuit (the response signal of the passive device) of the computer interface, the input of the channel receiver 4 is connected to the OUTPUT circuit of the computer interface, the input of the channel receiver 5 is connected to the IN input circuit of the computer interface, the input of the channel receiver 6 is connected to the SIL circuit (synchronization of the active device) of the computer interface, the input-output 42 of the device is connected to one of the address / data bits of the computer. Each output signal for the slave is generated with a separate software program.

contains a channel receiver 27, a decoder 28, a switch 29, a group of channel transmitters 30, an AND-NE element 31, a group of flip-flops 32, a register 33.

1 also shows the inputs and outputs of the trunk device and internal buses 34-43. In FIG. 2, position a denotes the time diagram of the readiness signal of an external device (WU); 8 is a timing diagram of information signals from a computer to a VU; B - timing diagram of the strobe signal from the computer to the VU; i - time diagram of the signal response VU;

Let us consider the device operation using the example of using it for interfacing an Elektronika-60 computer (a common bus interface, information word width is 16 bits) with an external device whose input bus is 32 bits wide (the direction from the computer to the PC ), the number of input control signals from the computer to the slave is 1, the number of output control signals from the slave to the computer is 2. For this, it is necessary that the total number of lines of the first group of inputs-outputs 34 of block 3

device registers in the trunk cycle OUTPUT. Output information from the WU computer reads with software applications in the main cycle ENTER. Information is exchanged between a computer and a VU in accordance with the following algorithm: VU, when it is ready to exchange, exposes a ready signal (Fig. 2a, T,), a computer generates information signals by this signal (Fig. 26, T, ), The computer generates a strobe signal (Fig. 2b, Tg), the slave receives a strobe signal, processes the information signals and exposes a response signal (Fig. 2d, Td), then the computer removes the strobe signal (Fig. 2b, T), and WU removes the response signal (Fig.2d, Tj-), the computer carries out the formation of new information 2 signals, T (T „)), and the process can be repeated. The interface device provides this exchange algorithm at the expense of the program executed in the computer as follows. The computer, through program cycles OUTPUT, sequentially fills with information (logical units) a group of triggers 32 blocks 3. Triggers before

put the first stage (buffer) memory. When recording information into the last trigger of group 32, the output 43 of one of the blocks 3 generates a signal that rewrites the accumulated information into registers 33. In this case, the signals from logical units from the outputs of registers 33 generate high level signals at the outputs of a group of channel transmitters 30. This allows programming the function of each line when using 30 channel elements as channel transmitters, which implement on the group of inputs-outputs 34 of block 3 of the ASSEMBLY SHW function with WU signal, i.e. if the output of this line is a high level signal from the output of the channel transmitter 30, it is possible to use both the output from the slave and the information from the computer

Thus, the recording of high levels in registers 33 is equivalent to the initial setup signal of a group of channel transmitters 30. Then, the software program enters the computer to analyze information on the ready signal line from the slave unit (Fig. 2a). Having detected a change in the level on this line, the computer performs the filling of information with the first stage of the triggers 32 in the OUTPUT cycles. Then, information is rewritten into register 3 and issued to trunk 34 (FIG. 26. After this, the recording information is written to the corresponding trigger 32 and its value is overwritten in register bit 33 and then to the corresponding output of highway 34 (FIG. Next, the computer performs a software analysis of the response signal of the control unit (Fig. 2d). Upon detecting this signal, the computer removes the strobe signal by recording the corresponding information in one of the triggers 32. Then the process can be continued due to the program logic we have a computer that uses the cycles of the input and output of the respective flip-flops 32 addresses.

The device in the computer cycle OUTPUT works as follows.

Address part of the cycle. In accordance with the time sequence of signals of the computer interface at the beginning of the cycle, it forms on the chains of the address highway 35 a cell address into which information is supposed to be recorded.

0

five

five

0

five

0

five

0

five

The higher address bits through the first group of channel receivers 7 are fed to the first group of inputs of the reference element 14. Channel receivers 7 can be implemented on the basis of commercially available IC series KP 559. To the second group of inputs of the comparison element 14 serves the code of the group address 41 of the device. When the group address code coincides with the high-order bits of the interface address, a logical unit signal is generated at the output of the comparison element 14 and is fed to the D input of the D flip-flop 18.. After issuing the address, the computer generates an SIA signal, which is fed through the channel receiver 6 to the record input (C input) of the trigger 18 and sets it to one state. In this case, the trigger 18 by the signal from the zero output stores in the register 15 lower bits of the address, which arrive at the information inputs of the register through the channel receivers B group. Signals from the output of the register 15 are divided into two groups. The first group (senior), representing the channel address code, arrives at the channel number decoder 16, which at one of its outputs generates a signal of the logical unit, the inputs to the information input of one of. of the ShF 20 group. Since at the moment the resolving potential of the single output of the trigger 18 arrives at the enabling input of the ShF 20 group, the signal for selecting the channel number is fed to the input of the selected block 3. The elemental element can be used as an IF. You are 585 AP16. Thus, the first potential input is supplied to the first gate input of the decoder 28 and the first input of the NAND element 31 of the selected unit 3. Similarly, the second group (younger) signals from the output of the address register 15, representing the address code of one of the main lines of the WU 34 in block 3, goes to the inputs of the ShF 19 group and, when allowing the potential output from the trigger 18, goes to the group of information inputs of the channel receiver 27 each of the blocks 3. The address code signals from the group of information outputs of the channel receiver 27 are sent to the address (control) inputs of the switch 29, which passes a signal from the selected line to VU 34 on its output, and also receives on the group of information inputs of the decoder 28, carried out the preparation for the formation of one of the signals arriving at the recording input of the corresponding trigger 32 of block 3.

Informational part of the cycle CONCLUSION information. After issuing a signal, the SIL of the computer removes the address and generates an information signal (logical zero or one) entering the input-output of the device 42 and then through the channel receiver 22 to the second input of the element IS-NOT 23, at the first input of which a resolution signal is present, since a high level signal is generated at the output of the NAND 11 element. The information signal from the output of the NAND 23 element goes to the internal information bus-37 of the device and then through the input-output of each block 3 to the D-inputs of the trigger group

32, Then the computer forms on the interface 25 which is analyzed by the computer and perceive

Signal Output, which through the channel receiver 4 is fed to the first input of the element AND-NOT 10 and the information input of the second SchF 13. At the output of the element AND-NOT 10 a logic zero signal is set, at the output of the second SchF 13 - an active level signal, and at the output of the first ShF 12 and at the output of the AND-NE 11 element - signals of the passive and active level, respectively (due to the signal of the logical zero at the second inputs).

The active recording signal from the output of the PF 13 enters the internal control bus of the device 39 (recording bus) and through the second information input of the channel receiver 27 enters the second gate input of the decoder 28 of each block 3, ensuring that the decoder 28 is formed at one of the outputs 3 the active level signal input to the recording of the corresponding trigger 32. In this case, information from the internal information bus 37 is recorded in the trigger 32 addressed by the computer. The signal from the trigger output 32a is fed to the input of the corresponding register bit 33. When writing information to one of the triggers 32 (in FIG. 1, the lower trigger 32 of the first block), information from the trigger groups 32 of all

blocks 3 in the corresponding registers 33 blocks 3.

From the outputs of the register 33, the information enters through groups of channel transmitters 30 on the trunk lines of the external device 34. As channel transmitters 30, elements with an open collector can be used, for example, IP1 559.

The final part of the cycle. The high level signals at the inputs of the NAND 10 element form a low level signal at its output, which, acting on the second input of the NAND element 17, forms a high level signal at its output. From the output of the element AND-NOT 17, the high level signal arrives at the first input of the element AND-NOT 21 and through the delay element 9 to its second input. As a result, the output element AND-NOT 21 after a time t determined by the delay element, a low-level signal (CIP) is generated,

five

0

g

five

0

is raised as a result of the termination of the operation Output. The delay duration is chosen greater than or equal to the sum of the propagation time of the signal from the output of the SchF 13 to the recording input of the trigger 32 and the time required to record information in the trigger 32. When receiving an SIP signal (low level - active) from a computer device, it removes the signal Output to the channel receiver 4. As a result, a passive signal level is established at the output of the second PF 13 and the internal bus 39, which ultimately leads to the removal of the recording signals at the inputs of the flip-flops 32 and the register 33. At the second input of the AND-17 element along the way; a high level signal as its output - the low-level signal, setting the output element to AND-21 high-level signal is yuschiys computer for passive. Upon receipt of a passive level through the CIP computer circuit, it removes the signal from the AIA.

The operation of the device in the computer cycle ENTER. The address part of the Input cycle is similar to that considered in the Output cycle. The information part of the cycle starts from the moment when the computer removes the address on the trunk and forms the Input signal, which is fed through the channel receiver 5 to the first input of the AND-NOT element 11 and the ShF 12 information input. The signal level at these inputs is high at that moment leads to the appearance of an active signal on the internal control bus 38. This signal, through the first information input of the channel receiver 27, reaches a high active level at the second input of the AND-31 element. At the first input of the AND-31 element in the selected block 3 (signal ShF corresponding output group 20) also present a logic one signal. At the third input of the NAND 31 element there is an information signal coming from the trunk of the external device 34 through the switch 29. The signal number (address) goes through the group of information inputs of the channel receiver 27 to the control input of the switch 29. The switch can be implemented based on commercially available IC series K133 for example K133 KPZ, KP7. Thus, only in the selected block 3, at the first and second inputs of the NAND element 31, conditions (logical units) are formed, at which its output signal is determined by the information signal at the third input. At the outputs of the AND-31 elements of the remaining M-1 blocks 3, a high level signal is generated. When implementing NE elements 31 on elements that allow the outputs to be combined according to the INSTALLATION OR scheme (for example, K133 LA7), the signal on the internal information bus 37 is determined by the selected information signal from the external device highway 34. The signal from the internal information bus 37 of the device enters through the element NOT 24 at the first input of the element AND-NOT 26. The element NOT 24 compensates for the inversion of the information signal at the element AND-NOT 31. At the second input of the element AND-NOT 26 into this

the time moment there is a resolving signal, since at the output of the NANDI element 11 a low level signal is formed, the inverting element is NOT 25 and, besides, it prohibits the passage of information through the NAND element 23 and provides a high level at its output. Thus, the signal supplied to the computer from the output of the NAND 26 element is determined by the information signal on the internal information bus of the device 37. At the same time, the low level signal from the output of the NAND 11 element goes to

j 0 5 Q l

,

uh

five

0

the first input of the NAND element 17. At the same time, on the input of the NAND 21 element, a CIP signal is formed, similarly to the considered OUTPUT cycle. The delay time in this case is determined by the sum of the propagation time of the signal from the output of the first SchF 12 to the second input of the NAND 31 element and the propagation time of the signal from the output of the NAND 31 element to the output of the NAND 26. For the stability of the device, the delay time of the element 22 is chosen equal to the maximum value of the sum in the OUTPUT or INPUT cycles. The computer, having received an SIP signal, receives information on the input-output of device 42 and then removes the Input signal. Further, the process is completed as described, i.e. in response to the removal of the signal, the input device removes the SIP signal at the output of the element IS-NOT 21, then the computer removes the signal SIA.

Claims (2)

1. A device for interfacing a computer with M external devices, comprising a switching unit and M communication units with an external device, each of which contains a decoder, a register, a switch, the first information input / output of the switching unit being the input-output device for connecting to an information input-output of a computer, characterized in that, in order to expand the range of external devices to increase the information width transmitted to an external device, a communication unit with a computer is inserted into it, and in each communication unit with external the device introduces a group of channel transmitters, a channel receiver, a group of triggers, an AND-NOT element, with the first, second and third information inputs of the communication unit with ERM | These are the device inputs for connecting to the computer clock input / output outputs, respectively The first information output of the computer communication unit is the output of the device connected to the synchronization input of the computer, the first, second groups of information inputs of the computer communication unit form the device input groups for connecting respectively to the groups Tarsch and low bits of the address 913 computer outputs, a group of information inputs of the switch and information outputs of channel transmitters i-ro (i 1, M) of a communication unit with an external device form groups of device inputs-outputs for connection to a group of information inputs / outputs of an i-ro external device, while the second the information output of the computer communication unit is connected to the control input of the switching unit, the second information input / output of which is connected to the output of the NAND element and the information inputs of the triggers of the group of the 1st communication unit with an external device, info group of the communication outputs of a computer communication unit connected to a group of information inputs of a channel receiver i-ro communication unit with an external device, the third, fourth information outputs of a communication unit with a computer are connected respectively to the first, second information inputs of a channel receiver i-ro block of a communication unit The j with the external device, the j-th information output (j 5, M + 5) of the communication unit with the computer is connected to the first gate input of the decoder and the first input of the element of the IS-NOT unit  i-ro (i 1, I) of the unit connected to an external device, in each communication unit with an external device the first information output of the channel receiver is connected to the second input of the NAND element, the third input of which is connected to the output of the switch, the control group which inputs are connected to the group of information inputs of the decoder and to the group of information outputs of the channel receiver, the second information output of which is connected to the second gate input of the decoder, the outputs of which are connected to the synchronous inputs of the group triggers, The ports of which are connected to the information inputs of the register, the information outputs of which are connected to the inputs of the channel transmitters of the group, the output of the senior bit of the decoder of the first communication unit with the external device connected to the recording input of its register and the recording inputs of the i-ro communication unit with an external device (i 2, M), and the computer communication unit contains a comparison element, an address register, a decoder, two groups of bus drivers, two bus drivers. ten 5 0 5 o five 0 with 0 five trigger, two groups of channel receivers, three channel receivers, four NAND elements, a delay element, the information inputs of the first, second, and third channel receivers being the first, second, and third information inputs of the computer communication unit, information inputs channel receivers of the first, second groups form, respectively, the first, second group of information inputs of a communication unit with a computer, the output of the first element -I-NOT is the first information output of a communication unit with a computer, the output of the second element AND- NOT connected to the first input of the third element AND-NOT and is the second information output of the communication unit with the computer, the outputs of the first, second bus drivers are respectively the third, fourth information outputs of the communication unit with the computer, the output of the j-ro driver of the first group is the j-th (j 5, M + 5) information output of the communication unit with a computer, while in the communication unit with a computer the output of the first channel receiver is connected to the information input of the second bus driver and the first input of the fourth AND-NOT element whose output with Connected to the second input of the third NAND element, the output of which is connected to the first input of the first NAND element and to the input of the delay element, the output of which is connected to the second input of the first NAND element, the output of the second channel receiver is connected to the information input of the first bus driver and with the first input of the second NAND element, the second input of which is connected to the second input of the fourth NAND element, with the enabling inputs of the first, second bus drivers, with the enabling inputs of the first, second, second shaper drivers SCP and with a single trigger output whose clock terminal is connected to data output. the third channel receiver, the outputs of the channel receivers of the first group are connected to the first group of inputs of the comparison element, the output of which is connected to the information input of the trigger, the zero output of which is co-; It is connected to the input of the record of the address register, the group of the lower bits of the information output of which is connected to the information inputs of the bus worlds of the second group, the information inputs of the bus drivers of the first group are connected to the output group of the decoder, the input group of which is connected to the group of senior bits of the information output of the address register, the group of information inputs of which is connected to the outputs of the channel receivers of the second group, the second group of inputs of the comparison element forms the address group device inputs. 2. The device POP.1, characterized in that the switching unit contains a channel receiver, two AND-NOT elements, two NOT elements, and and 12 the output of the first NAND element and the input of the channel receiver form the first information input / output of the switching unit; the output of the second NAND element and the input of the first element do NOT form the second information input / output of the switching unit; the first input of the second AND element is NOT connected to the input of the second element is NOT and is the control input of the switching unit, while in the switching unit the output of the channel receiver is connected to the second input of the second NAND element, the output of the first element is NOT connected to the first input of the first NAND element, the second input which is connected to the output of the second element is NOT.