SU1508222A1 - Device for interfacing two computers - Google Patents

Abstract

The invention relates to computing and can be used for computer interfacing in information and measuring complexes. The aim of the invention is to expand the functionality of the device by organizing the parallelization of the computational process. The device comprises a receiver unit 1, a register 2, a write control block 3, a block of 4 transmitters, a block of 5 drivers, a decoder 6 addresses, a block 7 of synchronization, a block 8 of control of input-output. The device provides for the rapid exchange of information between two computers, which allows solving in parallel a number of computational and control problems. 3 hp f-ly, 4 ill.

Description

. 15

The invention relates to computing technology and can be used to interface computers in information measuring complexes.

The purpose of the invention is to expand the functional capabilities of the device due to the organization of the parallel computing process,

Figure 1 presents the block diagram of the device; figure 2 - diagram of the synchronization unit; FIG. 3 is a diagram of the recording control block; FIG. 4 is a diagram of an I / O control unit.

The device contains (Fig. 1) receiver unit 1, register 2, write control unit 3, transmitter unit 4, reset signal conditioner block 5, address decoder 6, synchronization unit 7 and, and input-output control unit 8.

The synchronization unit 7 forms .2) from the first to the fourth elements AND-NOT 9-12, as well as the first and second elements AND 13 and 14,

The recording control unit 3 includes. (fig.Z) the first and second elements And 15 and 6, and the element OR-HE.

The I / O control unit 8 contains (FIG. 4) the first and second decoders 18 and 19, and the first to fourth triggers 20-23.

The device can operate in the mode of outputting byte information from the first computer and inputting it into the second computer and in the mode of outputting byte information from the second computer and inputting it into the first computer. The transition from one mode of operation to another is carried out programmatically by computer commands. Information input-output is performed byte-by-byte in the standard code KOI-7N. The initial installation of the device is carried out by the block 5 of shapers of the Stop Signals of the first computer and the Stop of the second computer generated by pressing the corresponding keys on the keyboards of the first. The second and second computers enter the first and second informational inputs of unit 5, the first and second outputs of which generate pulses that bring the input / output control unit 8 to the initial state. The signals at the outputs of the request block 8 control input-output disable the bus of the first computer and the bus of the second computer

five

five

0

0

0

from the receiver unit 1, and also prohibits the operation of the recording control unit .3. The signal levels at the first and second outputs of the address decoder 6 disable the input bus of the first computer and the input bus of the second computer from the transmitter unit 4. When displaying a byte of information on the first computer and enter the second one. The first computer periodically on the address bus of the first computer sets the address of the second computer. The signal from the first output of the address decoder 6 is fed to the first permission input of the synchronization unit 7, allowing it to work. In this case, the first computer analyzes the state of the signal on the I / O synchronization line of the first computer. When the second computer is ready to receive a byte of information, the address of the first computer is periodically set on the address bus, sets the second computer on the I / O line, the signal level corresponding to the information input mode on the second computer, and issues a second pulse on the I / O control line . The signal from the second output of the address decoder 6 is fed to the second resolution input of the transmitter unit 4, connected to it is the input bus of the second computer. The signal level on the I / O line of the second computer determines the operation of the input-output control unit 8 for inputting information to the second computer. On the input-output control input-output control clock, the input-output control unit 8 generates a signal at the second request output arriving at the corresponding inputs of the fleet 1 receivers, the recording control unit 3 and the synchronization unit 7. The signal level at the second request output of the input-output control unit 8 connects the output bus of the first computer to lock 1 of the receivers, determines the operation of the write control recording unit 3 to record information byte in the register 2 from the first computer and enable the synchronization unit 7 . At the same time, synchronization unit 7 produces on the first output a signal arriving at the input-output synchronization line of the first computer. The first computer, having received the I / O synchronization signal, sets the Signal level on the I / O bus corresponding to the information output mode on the first computer, the byte of the information on the output bus of the first computer, the address of the second computer on the address bus, and

Claims (1)

sends a sync pulse to the input-output control line. The signal level on the I / O line of the first computer determines the operation of the I / O control unit 8 to output information from the first computer. The information byte of the output of the first computer through the receiver unit 1 is fed to the information inputs by a register-JQ record connected to the synchronizer input 2, on the leading edge of the synchronizing pulse. Input-output control of the first computer, coming from the output of the input-output control unit through the control unit 3 the recording of control register 2 is carried out. writing a byte of information to register 2, and also changes the signal level at the first output of the I / O control unit 8, the signal from the first gate output of the I / O control unit 8 posts to the first gate input of the synchronization unit 7. In this case, the synchronization unit 7 produces on the second and fourth outputs pulses arriving at the I / O synchronization line of the second computer and the second input of the block 5, respectively. A second computer on an I / O synchronization pulse through a block of 4 transmitters according to the input pin of the second computer receives a byte of information from register 2, and Block 5 generates a pulse at the falling front of the pulse at the second resolution input at its second output; The translating I / O control unit 8 is reset. Invention Formula 1, A device for interfacing two computers containing a receiver unit, a Transmitter unit, a register, a write control unit, an I / O control unit, a synchronization unit, a reset signal generator unit, and an address decoder, the first and second information inputs of the receiver unit are inputs devices for connecting information outputs of the First, second computer, respectively, the first input of the address decoder is the input of the device for connecting the address output of the first computer, the output of the receiver unit is connected to information the input of the register, the output of which is connected to the information, the input of the transmitter unit, per15 20 25 thirty 35 40 45 50 55 register register, the first output of the synchronization block is the output of the device for connecting the input-output synchronization input of the first computer, the first enable input of the receiver block is connected to the first enable input of the write control block, the first input of the synchronization block request and the output of the first input control computer - output, the second resolution input of the receiver unit is connected to the second input of the record control unit, with the second input of the synchronization unit request. and with the output of the request of the second computer of the I / O control unit, the first, second synchronization inputs of the recording control unit are connected respectively to the first PCR, the second synchronization outputs of the I / O control unit, the first information input of the reset signaling unit is the device input to connect the stop output of the first computer, the first stop code of the reset signal generator block is connected to the first reset input of the I / O control block, the first, second address inputs and the first, second inputs p Press of which are the device inputs for connecting, respectively, the address outputs of the first and second computers and I / O outputs and controlling the input-output of the first computer, which is different from the fact that, in order to expand the functionality of the device through the organization of parallelization The second output of the address decoder is connected to the second enable input of the transmitter unit and to the second enable input of the synchronization unit, the second output of which is the output of the device for connecting the input nhronizatsii IO second computer, a third sync block chetverty.y outputs connected respectively to the first, the second inputs of block formers ALLOW .ni signals out, the second outputs of which are. the device outputs for connecting the information inputs of the first and second computers, respectively, the first output of the address decoder is connected to the first enable input of the transmitter unit and, the first enable input of the synchronization unit, the output of the control unit five 0 five 0 five 0 five 0 five register register, the first output of the synchronization block is the output of the device for connecting the input-output synchronization input of the first computer, the first enable input of the receiver block is connected to the first enable input of the write control block, the first input of the synchronization block request and the output of the first input control computer - output, the second resolution input of the receiver unit is connected to the second input of the record control unit, with the second input of the synchronization unit request. and with the output of the request of the second computer of the I / O control unit, the first, second synchronization inputs of the recording control unit are connected respectively to the first PCR, the second synchronization outputs of the I / O control unit, the first information input of the reset signaling unit is the device input to connect the stop output of the first computer, the first stop code of the reset signal generator block is connected to the first reset input of the I / O control block, the first, second address inputs and the first, second inputs p Press of which are the device inputs for connecting, respectively, the address outputs of the first and second computers and I / O outputs and controlling the input-output of the first computer, which is different from the fact that, in order to expand the functionality of the device through the organization of parallelization The second output of the address decoder is connected to the second enable input of the transmitter unit and to the second enable input of the synchronization unit, the second output of which is the output of the device for connecting the input nhronizatsii IO second computer, a third sync block chetverty.y outputs connected respectively to the first, the second inputs of block formers ALLOW .ni signals reset, the second information input of which is the input of the device for connecting the stop output of the second computer, the second output of the reset signal generator block is connected to the second reset input of the I / O control unitJ the second decoder input is the device input For connecting the address output of the second computer, the third, fourth inputs of the I / O control unit mode are the inputs of the device for connecting, respectively, the outputs of the I / O feature and control Lenin by the input / output of the second computer, The second, second gate outputs of the I / O control unit are connected respectively to PEREL, the second gate inputs of the sync-and-sync block, the first, second sync outputs of the input control block are. the output is connected respectively to the first, second synchronization inputs of the recording control unit, 2, the device according to claim 1, about tl and is the fact that the synchronization unit contains the first to fourth AND-NOT elements and the first, second AND elements, the first one. the block enable input is connected to: the first inputs of the first, second AND-E elements, the second resolution input of the block is connected to the first inputs of the third, fourth AND-NOT elements, the first, second request inputs and the first, second gate inputs of the block are connected to the second inputs of the third, first, fourth and second elements of the NAND, respectively, the outputs of the first and third elements of the NAND are connected respectively to the first inputs of the first, second elements AND, the outputs of which are connected respectively to the first, second outputs of the block, output to The other element is NOT connected to the second input of the nepBdro element I and G by the third output of the block, the output of the fourth element. AND-NOT connected to the second vhbDom second element And with the fourth output of the block. 3. The device according to claim 1, about the t of l and some that block control 0 0 five 0 The first entry contains the first., the second AND elements and the OR-NOT element, with the first, second resolution inputs and the first j,. The second synchronization inputs of the block are connected respectively to the first inputs of the first, second AND elements and the second inputs of the first, second AND elements, the outputs of the first, second AND elements are connected respectively to the first, second inputs of the OR-NOT element, the output of which is the output of the block. AO Device by nl, tl and - that the I / O control block contains the first, second decoders and the first to fourth triggers, the first, second address inputs of the block, the first, second inputs of the block mode and the third, fourth inputs block mode. connected respectively with the first, second and third inputs of the first, second decoders, the first, second outputs of the first decoder and the first ,. The second outputs of the second decoder are connected respectively to the single inputs of the first, second, third and fourth flip-flops, the first input The unit reset 5 is connected to the zero inputs of the first and fourth triggers, the second reset input of the block is connected to the zero inputs of the second, third triggers, the third outputs of the first, second decoders are connected respectively to the first, second synchronization outputs of the block, the outputs of the first and third triggers are connected to query outputs 5 of the first and second computer units, the outputs of the second, fourth triggers are connected respectively to the first, second strobing outputs of the unit. (rig 2