SU1599865A1 - Interface of processor group with peripheral group - Google Patents

Abstract

The invention relates to computing and can be used in multiprocessor computing systems, for example, in embedded control and information processing systems. The aim of the invention is to reduce hardware costs. The device comprises an exchange signal generating unit, a sampling node, two decoders, two selector-multiplexers, a group of transceivers. 2 hp ff, 4 ill.

Description

The invention relates to computing and can be used in multiprocessor computing systems, such as embedded control and information processing systems.

The aim of the invention is to reduce hardware costs.

Figure 1 shows the structural diagram of the device; figure 2 - the same, the sample node; fig. 3 - the same, block of forming exchange signals; figure 4 - the same transceiver.

The device (Fig. 1) contains a group of external devices 1, a bus 2 of the input-view, a group of transceivers 3, 4, processor buses 5, a group of processors 6, signal lines 7 from the external devices, output buses 8 of the code required processor from external devices, sampling node 9, 10 pulse generator, sync pulse line 11, write inhibit signal line 12, generalized request signal line 13, device feature signal line 14, exchange signal generating unit 15, sampling node output bus 16 priority is arranged properties), the communication resolution signal line 17, a decoder 18, a group of signal lines 19 that allow an external device to respond to an interception, a decoder 20, a bus capture resolution line 21, a selector-multiplexer 22, an output bus 23 of a selector-multiplexer 22, the selector-multiplexer 24, the output bus 25 of the selector-multiplexer 24, the group of lines 26 signals the request for the capture of the tire 2.

The I / O bus 2 structure corresponds to the structure of processor buses 5, which in turn depend on the type of processors used. In this case, tires MPI (GOST 26765.51-86) are used.

Sample node 9 (FIG. 2) contains a request register 27, a service register 28, a group of outputs 29 of a service register, a priority encoder 30, a decoder 31, a group you (L

bi

00

ate

moves 32 decoder, the element is NOT 33, the element is AND 34, the element is OR 35.

The exchange signal shaping unit 15 (FIG. 3) comprises an IL 30 element triggers 37-39, a second element OR 40 element OR 41, a trigger 42, a transmitter 43, an OR element 44, a signal line 45 of the Bus 2 exchange, a line 46 of the interrupt bus provision signal 2, signal line 47 Installing bus 2, interrupt request signal line 48.

Transceivers 4 (FIG. 4) contain an AND 49 element, an interrupt request link 50, a bus capture resolution line 51, a processor, a bus signal response line 52, a transmitter 53, an amplified interrogation request line 54, a processor enhancement signal line 55 bus 2, amplified signal line 56 Response, element NOT 57, element 58, line group 59 Bus-2 address-data, bi-directional transceiver 60, line group 61 Address-bus 5 data group, bus control 2 line 62, ACC signal line 63 bus 2, transmitter 64, group of lines 65 control bus 5 s.

The device works as follows.

The processors 6 of a multiprocessor computing system, operating in parallel and independently of one another, can at any time access external devices 1 connected to the I / O bus 2 (which is common to the entire system). For this, the processor issues a request to capture the bus 2, which on line 26 enters the sample node 9 for the information input of the request register 27 defined for this device (an information input is defined for each device in the request register). All requests are written to register 27 through; as they arrive. In turn, external devices 1 may require interrupt service, and it is necessary that such an interruption be serviced by a processor, which is indicated by an external device. A service request from an external device enters the sampling node 9 on register 27, and the number of the required processor is sent to the input of the multiplexer-selector 22 via bus 8. From the register output

0

0

five

0

five

0

five

0

five

27 requests are received to the information inputs of the service register 28, to the entry entry of which through the element

And 34 pulses are received from the generator 10 pulses on line 11. From the output of the register 28, requests are received via lines 29 to the inputs of the priority encoder 30 and the OR element 35 (the number of inputs equals the number of devices that can issue a service request). If the register

If at least one request is recorded, then the output of the OR element 35 produces a generalized request signal: (13), which enters the exchange signal generation unit 15, in response to which the unit 15 generates a signal on the recording prohibition line 12. At this time, at the output of the encoder 30, a device code is generated, the request of which has the highest priority and all requests written to register 28, consisting of the device number on line 16 and the sign of the device

on line 14 (since external devices 1 and processors 6 are independently numbered, they must be distinguished: 1 is a device sign corresponding to an external device, O is a processor). The device code enters the sampling node at the information inputs of the gated decoder 31, at the input of which a gate is allowed through element NO 33, a write inhibit signal (12) from block 15 is received. The same signal enters input of the And 34 element, prohibiting clock pulses 28. Thus, writing to the register 28 is prohibited for the time when the signal 12 is set. In addition, the number on line 16 goes to the inputs of the decoder 18 and the selector-multiplexer 22, as well as to the input of the selector-multiplexer 24, line 14 goes to the prohibitive input of the decoder 18, to the input of the selector-multiplexer 22 and 3 block 15. The further passage of the signals depends on whether the processor or an external device has priority (i.e., what value the device sign is O or 1) . Suppose that a device tag corresponds to O, i.e., a request from the processor for a bus 2 seizure has begun to be serviced. Then the device tag

disables the outputs of the decoder 18 and switches the selector-multiplexer 22 so that the number of the processor making the request passes on its output, and from the output it goes to the inputs of the decoder 20, after which the block: 15 generates a communication enable signal, which via line 1 goes to the input of the decoder 20 and one of the inputs of the decoder 18, but the outputs of the decoder 18 are prohibited by the device, and from the output of the decoder 20, the communication permission signal through line 21 goes to the processor’s transceiver, which makes a logical request Electrically processor bus 5 with bus 2, providing access for processor 6 to external devices 1. If the device sign corresponds to 1, then the device number chosen by the sampling unit 9 corresponds to the number of the external device. Then, the number of the external device that placed the request arrives at the input of the decoder 18, and when block 15 generates a communication enable signal, from the output of this decoder, a signal is received to the external device through line 19, allowing it to react to the signal of the interrogation signal. In addition, at the output of the selector-multiplexer 22, the number of the processor required by an external device is passed, which passes through the selector-multiplexer 24 and enters the input of the decoder 20, the output of which, after the receipt of the communication permission signal, receives the communication resolution on the transceiver 3, 4 processors 6, which is requested by an external device. At this time, block 15 generates an interrogation request signal and drives it over bus 2. The processor must stop the interrupt grant signal, which over bus 2 goes to an external device. In response to this, the external device 1 issues an interrupt vector to the bus 2 and then the processor serves the interrupt.

The exchange signal generating unit 15 operates as follows.

When the computing system is initially turned on, bus 2 through line 4 through the element OR 40 to the zero inputs of the flip-flops 37 and 38 receives a synapte of the initial setup and sets the signal-generating unit

 ,

99865

1C

exchange to the original state. The sync and trigger inputs of triggers 37, 38 and 42 receive clock pulses from generator 10 through line t. A generic request 13 is sent to the information input of trigger 37. Then, the output of the trigger 37 generates a communication prohibition signal 12, which enters sample node 9 and to the information input of the trigger 38 of block 15. At the output of the trigger 38, a signal is generated on the communication resolution line 17 (the signal delay on the line 17 by one cycle

r relative (the signal on line 12 is organized in connection with the fact that during this time the required information should be established at the inputs 18 and 20 of the decoders). If the device tag is on

20 of line 14 corresponds to 1, it passes through the OR 41 element to the information input of flip-flop 42, which at the output of this flip-flop generates an interrogation request signal that passes through transmitter 43 via line 48 to bus 2. This signal is reset by the leading edge of the interrupt grant signal , which, besides the external device, comes from the processor via bus 2 and via SRI 46 through the element OR 44 to the zero input of the trigger 42. If the sign

ABOUT.

thirty

device matches

that

trigger 42 is not set. When the processor exchanges with an external device from bus 2 via line 45 through element OR 44, a synchronous input of trigger 39 passes the signal Exchange or after the termination of the interruption service through line 46 from bus 2 through another input of element 44 44, an interrupt provision signal. These signals, with a falling front, set the trigger output 39 to a unit that

The d5 through the OR 40 element passes to the zero inputs of trigger 37 and trigger 38, causing the signals on lines 12 and 17 to stop forming. Block 15 is ready to process the next request. Transceivers 3, 4 operate as follows.

In the initial state, the transmission of information through transmitters 53 and 64, as well as transceiver 60, is prohibited. The communication enable signal on line 21 is fed to the enable inputs of transceiver 60 and transmitters 53 and 64, allowing the passage of information, as well as to the inputs of elements

50

55

And 49, 58. At the other input of the element 49 and 49, a signal is received on the Interrupt Request signal, and, if this signal is formed, then on the line 50 a Interrupt Request signal is generated, which passes through the transmitter 53, on line 54 enters the bus 5 and it is sent to processor 6, in this case, the processor generates a signal to provide a preglogani which via bus 5 via transmitter 6 via line 46 enters block 15 of generating exchange signals. To the other input of the And 58 signal, the Interrupt Request is received through the NOT 57 element. Thus, if the device sign corresponds to O, then the Interrupt Request signal is not formed on line 48, and then the output (I And 58 element fails to receive a signal; which via line 51 through transmitter 53, through line 55 and bus 5 goes to processor 6, which starts the address exchange.In addition, through the transmitter 53 passes the Answer signal from the external device to the processor, and through the transmitter 64 from the processor to the external device post control signals are fed in. A bi-directional transceiver is used to provide for transmission over a group of lines of Address data.

Claims (3)

1. A device for interfacing a group of processors with a group of external devices, containing; its sampling unit, an exchange signal generating unit, a pulse generator, a group of transceivers, the first groups of information inputs and outputs of the group of transceivers forming device input-output groups for connecting to information groups inputs-outputs of the respective processors of the group, the second groups of information inputs-outputs of the transceiver groups of the group are connected to the group of inputs-codes of the logical condition of the block forming the exchange signals and form groups of inputs and outputs of the device for connecting to groups of information inputs of the respective external devices of the group, different in tbm, which, in order to reduce d 5 0 5 0 five 0 5 p five device costs, the device contains two decoders and two selector-multiplexers, the output group of the nepBioro decoder forms a group of device outputs for connecting to the interrupt enable inputs of the corresponding external devices of the group, the input group of the interrupt request node of the device forms a group of device inputs for connecting the output requirements of the corresponding signals external devices of the group, groups of information inputs of the first selector-multiplexer form the groups of inputs of the device for Keys to the address output groups of the corresponding external devices of the group, the input group of the bus seizure request input group forms a device input group for connecting the corresponding group processors to the bus seizure request outputs, and the pulse generator synchronous code is connected to the sample node's synchronous input and the syncro input of the signal conditioning unit exchange, the output of the communication permission of which is connected, with the first permitting input of the first decoder and with the authorizing input of the second decoder, a group of information in one of which is connected to the group of information outputs of the second selector-multiplexer, the first group of information inputs of which is connected to the group of code outputs of the sampling node, the group of information inputs of the first decoder and the group of control inputs of the first selector multiplexer, the group of information outputs of which is connected to r second a group of information inputs of the second selector-multiplexer, the control input of which is connected to the second enabling input of the first decoder, with the output recognizing a sampling assembly of the apparatus to the first input of the logical condition of exchange of signals forming unit, a second input and an output of logical conditions disable recording of which are connected respectively with the output of a generalized request and to the input of the recording sampling node prohibition gruppavyhodov second decoder coupled to the enable input of groups of transceivers s. 2. The device according to claim 1, of which is that the exchange signal forming unit contains four flip-flops, a transmitter, an OR element, the first, second inputs of the first OR element, the first input of the second OR element, and the information output of the transmitter form a group of inputs and outputs of the logical condition of the block, the sync input of the first trigger is connected to the sync inputs of the second, third triggers and is the synchronous input of the block, the first input of the third element OR, and the information input of the first trigger The logical block condition, the output of the first trigger is connected to the information input of the second trigger, the first input of the fourth OR element, the second input of the third OR element, and is the output of block prohibition, the output of the second trigger is connected to the second input of the fourth OR element. the output of the communication permission of the block; in the block of forming the exchange signals, the output of the fourth element OR is connected to single inputs of the fourth trigger, the output of which is connected to the second input of the second element OR, Which is connected to the zero inputs of the first and second triggers, the output of the first element OR is connected to the synchronous input of the fourth trigger and to the zero input of the third trigger, the information input and output of which are connected respectively to the output of the third element OR and the information input of the transmitter, lO to 15 A true trigger is connected to the device's zero potential bus. 3. The device according to claim 1, of which the sampling node contains a query register, a service register, a priority encoder, a decoder, an OR element, an AND element, an NOT element, and the first and second groups of information inputs of the query register form respectively the input group of the pregge demand and the group of inputs for the acquisition of the tire bus, the first input of the AND element is the synchronous input of the node, the second input of the AND element is connected to the input of the element NOT and is the input of the node recording prohibition; The 20 information input of the decoder is the output of the node device feature, the output group of the priority chip is connected to the group of information inputs of the decoder, and it forms the code output group of the node, the output of the OR element is the output of the generalized request of the node; NOT connected to the strobe input of the decoder, the output group of which is connected to the group of installation inputs of the request register, the output group of which is connected to the group of information inputs of the register nor, the group of outputs of which is connected to the group of inputs of the element ISH1 and with the group of information inputs of the priority encoder, the output of the element And is connected to the recording input 4Q service register. 25 thirty 35 5f Fiz.