SU1291993A1 - Interface for linking electronic computer with terminals - Google Patents

Abstract

The invention relates to computing and can be used in multi-terminal systems, such as class type. The aim of the invention is to increase the number of connected terminals. The goal is achieved in that a device containing a communication unit with a computer consisting of a first gain unit, an address decoder and a control signal decoder, a second gain node, a switching unit and a group of communication units with a terminal, and each communication unit with a group terminal contains a readiness trigger, a terminal address decoder, a strobe trigger, input and output registers, a start strobe trigger, a request trigger, an input strobe counter, an address dialing node, an AND node, a node of NO elements, three evil elements AND-NOT, element OR-NOT, a group of elements NOT, two groups of elements OR-NOT, four elements NOT, a delay element, two elements AND, three elements AND-NOT, a group of elements AND NOT, an element AND -OR or matching resistor node. 4 il. (L N9 oo with co 00

Description

The invention relates to computing and can be used in multi-terminal systems, such as class type.

The purpose of the invention is to increase the number of connected terminals.

FIG. 1 is a block diagram of the device; nr fig. 2 is a functional diagram of a communication unit with a terminal; in fig. 3 and 4 - timing charts of exchange at the junction with the computer.

The device (Fig. 1) contains a block of communication with a computer, a switch 2, a block 3 of matching resistors, a group of blocks 4 of communication with a terminal 5, a second gain node 6, a data bus 7 - addresses, buses (lines) 8-10 signals data input synchronization, reset and synchronization of data output, bus (lines) 11 and 12 ready signals and service requests. The device is connected to the computer 13.

The communication units 4 with the terminal (FIG. 2) contain a terminal address decoder consisting of the AND 14 element set field 14, the AND 15 element, the OR-NOT 16, the readiness trigger 17, the first group of OR-NOT 18 elements, the first and second elements NOT 19 and 20, delay element 21, trigger 22, gate 22, first and second elements 23 and 24, input register 25, third element NOT 26, trigger trigger 27, first AND-NE element 28, request trigger 29, input gate counter 30 , a group of elements AND-NOT 31, an element AND-OR 32, a node of elements AND 33, an internal highway 34 of the device, output register 35., WTO the second node of the elements AND-NOT 36, the node 37 of the terminal address set, the third node of the elements AND-NOT 38, the fourth element NOT 39 the second element AND-NOT 40, the second group of elements OR-NOT 41, the group of elements NOT 42, the third element AND- NOT 43 node 44 of the matching register, the first node of the NAND 45 and the node of the elements 46.

The second gain node (Fig. 2) contains ycSliteJDI 47. The switch (Fig. 1) contains the nodes 48 of the AND-NOT elements. The computer communication unit 1 (Fig. 1) comprises a control decoder 49, an address decoder 50, and a first gain node 51.

In addition, the device (Figs. 1 and 2) contains buses (lines) 52-56 of communication of blocks 4 with terminal 5 and buses (lines) 57 and 58 of the inputs and outputs of the data input synchronization signals of blocks 1.

Unit 1 is used to transfer from a computer 13 to a data byte containing a device address or an information code intended for processing in the device a Reset signal intended for resetting the hardware signal of a strobe signal Output data accompanying data byte when outputting information from the computer 13, the strobe signal Input data, accompanying, its data byte when entering information B computer 13.

Block 1 is used to transmit 13 bytes of data from the device to the computer, which contains the address of the terminal 5 or information intended for processing in the computer, a Ready signal from the terminal 5, a signal - Service request from the terminal 5. 5 Tires have the following functionality: bus 7 (YES0-07) - bidirectional data lines of the address; line 10 (Output data) —a line of the strobe signal accompanying the Q data at the time of output from the computer (similar to the command read by devices of information located on bus 7); line 8 (input data) - the line of the strobe signal issued by the computer in response to the request for service signal; by this signal terminal 5, which put a signal in line 56 The request for service should place 7 bytes of information Q (address or data) on the bus, and on the second

the edge of the signal in line 57 is removed from the bus 7 information; each device connected to the computer channel must have hardware allowing to block the signal broadcasting Input data provided to the channel if the device itself has sent a Service Request signal; line 11 - signal line Ready, which is set by terminal 5 in the event that it was accessed by the computer 13 and the hardware part is ready for information processing; line 12 - signal line Service request, the signal can be set by a device that has an active part, such as a keyboard, while the device stops transmitting the signal Input data until

50

3

will be served; line 9 is a reset line, which is placed on the computer 13 and is used by devices connected to the computer channel to install the equipment into the original connection.

The device works as follows

The computer 13 places data bytes on the channel line, which is the address of terminal 5 with which it needs to be exchanged. The data byte is accompanied by the Output data signal.

All blocks 4 receive information. In the trigger 22, gates are written 1, and at the end of the strobe. Output data on line 10, the trigger 22 is reset, if during the time of the strobe the trigger 17 was not activated, the latter can be activated if the following conditions are met: And 15 there is a logical zero signal, which corresponds to the coincidence of the address placed on the lines of the DA00-07 channel with the address of the devices specified with jumpers or switches of the field 14; the device's hardware is ready for operation - there is a signal Hardware readiness on line 56; trigger 22 recorded 1 - there is a signal. on line 12 there is no signal from the other

block 4.

If trigger 17 is set, a logical zero signal from its inverse is prohibited from resetting trigger 22 after the end of the signal. Output data on line 10. The described operation is a bus catch operation.

The computer 13 receives the Ready signal from line 12 and, if available, continues the exchange, or organizes a new exchange cycle.

On the Ready signal, the computer exposes a new data byte on the DA00-DA07 line, which is designed to control the operation of the selected terminal 5. The data byte is accompanied by a signal Output data on line 10.

Trigger 17 cannot be coded in any block 4 (even if the code on the DA00-DA07 line with the device address matches), since the Ready signal is present on the channel line. Thus, all blocks 4, except the block that captured the bus, ignore the information.

fO

15

20

25

five

thirty

35

0

five

The trigger 22 of block 4, with which the exchange takes place, is recorded 1 - n. A signal appears on the output. Page 2. By signal pp. 2 information from the channel DA00-DA07 is recorded in the input register 25. It will be stored until terminal 5 places a signal on the line 56 Hardware readiness and the computer 13 does not begin a new exchange cycle with terminal 5. Upon termination of the signal Output data trigger 17 is reset, the Ready signal on line 11 disappears, the trigger 22 is updated.

At this time, the communication cycle Reception ends.

The timing diagram of the signals on the lines of the communication channel of the loop. The reception is shown in FIG. 4. Algorithm of the Reception cycle can be described in a trace way.

The computer 13 sets on the line DA07 the address of one of the terminals 5, followed by the strobe Output data. Terminal 5 exposes the Ready signal on line 56. The COMPUTER 13 transmits necessary information on the DA00-DA07 line, accompanied by its strobe Data conclusions. Terminal 5 writes information to register 25 and is reset to the initial state by a second signal edge. Output data on line 10.

In order to issue a signal to line 12, the Service Request in block 4 must be triggered 29, which is carried out under the following conditions: Start gate arrives from terminal 5, which starts trigger 27 in one state. By the Start Gate, the data is received into output register 35; on lines 8, 9 and 12, there are no signals.

After -terminal 5 has sent a signal to line 12, a request for servicing a computer 13 should be issued (

0

five

cut arbitrary amount of time) signal input data. This signal from line 8 can only be received by blocks 4, which are physically closer to computer 13 than block 4, which placed Service Request on line 12.

Terminal 5, which has submitted a Request for Service, prohibits the propagation of a signal to subsequent ones, by closing element I-NE 43 with a logical O signal from the inverse shoulder of trigger 29.

Signal Input data is written 1 to the counter 30 input gates. If trigger 29 is cocked in this block 4, a signal is generated. 11, which opens the elements AND of the nodes 38 and 35 to transmit the address of the terminal 5 to the buses 7. On the second edge of the signal, the input data on lines 8 is removed from the buses 7.

living - with the second output and the second and third inputs of the second gain node, the third output connected to the synchronization input (5 data input of the first communication unit with the terminal of the group, the first output of the decoder of the control signals, which is different) ,

20 that, in order to increase the number of connected terminals, a matching resistor block is inserted into the device, the switch input is connected to a group of outputs of the first gain node, the fourth output of the second gain block is connected to the reset inputs of the terminal blocks of the group

After an arbitrary time interval of readiness and the output of the request for servicing a computer 13, it issues the following signal Input data. This signal records +1 in counter 30. If trigger 29 is cocked in this block 4, a signal is generated. 22, which permits the transmission of information from output register 35 to bus 7 and later on channel DA00-DA007.

On the second signal edge, the input data is reset by triggers 29 and 27 and counter 30.

The time diagram of signals on the lines of the communication channel is shown in FIG. 3

The algorithm of the device when entering information into the computer 13 is as follows. Terminal 5 places a Service Request signal on line 55 and on line 12. The computer 13 exposes the data input to the i-ro communication unit with the ter- minal Data input to line 8, a 30 min terminal () is connected to the input of the minal 5 via a signal The input data input synchronization data i + 1 exposes to bus 7 its address, the communication unit with the group terminal, the computer 13 reads the data from the busses 7 and the redundancy input and output, the first signal outputs the input data. Recording strobe, start strobe inputs Terminal 5 on the second signal The ready data of the i-ro communication unit from the terminal exposes a group of information bytes of the group's terminal and the corresponding inputs and outputs of the i-th device group for connecting the information output and the input, the strobe input 40 recordings and outputs of the start and readout gate of the i-ro terminal, the inputs of the matching register block are connected to the switch input / output, the second and third 45 outputs and inputs of the second gain node and the input synchronization output of the M-th communication unit with m rminalom, wherein Ks1zhdy communication unit with tervvoda

on the bus 7. The computer 13 reads the data and removes the signal Input data. On the second edge of the signal, the input data of TDS5 is put into the initial connection.

Claims (1)

Invention Formula A device for interfacing a computer with terminals, comprising a computer communication unit consisting of a first amplification node, address decoders and a control signal decoder, a second amplification node, the first inputs and outputs of which are connected respectively to the first output of the control and the decoder information signals, the second output and the second terminal of the group contain a trigger of readiness, a terminal address decoder, a gate trigger, input and output registers, a trigger gate trigger, a query trigger, an input structure counter, ate a set of addresses, node whose formation input is connected with 55 elements AND, a node of elements NOT, three respectively to the first input and output of a node of elements AND-NOT, an element NLI-NK, the first amplification node, and authorizing a group of elements NOT, two groups of effective input - through the address decoder address of the HW-NOT cops, four elements NOT, to the group of outputs of the first node of the amplification is an element of delay, two elements AND, oi, the input group of which is connected to the switch output, and the input-output is the input-output of the device for connection to the information control buses of the computer, and the group of communication blocks with the terminal, the information inputs-outputs of which are connected to the input-output of the switch, and input data output sync output living, respectively, with the second output and the second and third inputs of the second amplification node, the third output of the first communication unit connected to the input synchronization input to the group terminal, the first output of the control decoder is connected to the control input of the switch, that, in order to increase the number of connected terminals, a matching resistor block is inserted into the device, the switch input is connected to the output group of the first gain node, the fourth output of the second gain block is connected to the reset inputs of communication blocks with the terminal group availability and request for service input data of the i-ro communication unit with the terminal () is connected to the input input data input synchronization i + 1 of the communication unit with the group terminal, information input and output, output of the recording strobe, inputs of the readiness start gate i-ro the communication unit with the terminal of the group are the corresponding inputs and outputs of the i-th group of the device for connecting the information output and input, the input of the recording strobe and the output strobe of the i-ro terminal, the inputs of the register register are connected, respectively, to the input switch output, second, and third output and the inputs of the second gain node and the output of data input synchronization of the M-th communication unit with the terminal, where the X1 each communication unit with the group terminal contains a 5K trigger, a terminal address decoder, a gates trigger, input and output registers, and a start gate trigger , query trigger, input stb counter, address set node, node the three NAND elements, the NAND element group, the AND-OR element and the matching register node, the input register output and the output register information input are respectively the information output and the input of the communication unit with the terminal, the information input / output of which is connected to the information input of the first node of the NAND elements and the output of the node of the AND elements, the input of the first element is NOT the input synchronization of the data output of the communication unit with the terminal, and the output is connected to the input of the second element NOT and the control input of the first node of the NAND elements, the output of which is directly and through the node of the elements NOT connected to the input of the terminal address dedifferator; connected to the information input of the input register, the sync input of which is the output of the write strobe of the communication unit with the terminal and connected to the single output of the strobe trigger and the first input of the first And element, the second input connected to the output The second element AND and the reset input of the gate trigger, whose installation input is connected via the delay element to the output of the second element NOT and the first input of the second element AND, the second input connected to the zero output of the ready trigger, the installation input of which is connected to the output of the element OR NOT, first the second and third inputs of which are connected respectively to the output of the terminal address decoder, the zero output of the gate trigger and the readiness input of the communication unit with the terminal whose readiness output is connected to a quarter the input of an OR-NOT element and the output of the first OR-NOT element of the first group, the input connected to the enable input of the input register and the single input of the ready trigger, the reset input of which is connected to the output of the second OR-NOT element of the first group, the first and second inputs connected respectively to the outputs the first AND element and the third OR element of the first group, whose input is the reset input of the communication unit with the terminal, and the output is connected to the first input of the OR-NOT element of the second group; O five 0 five which is connected to the reset inputs of the trip request requestr and the start gate trigger, the installation input of the NOT connected via the third element to the start gate of the communication unit with the terminal and the output register synchronous input, the output of which is connected to the information input of the second node of the AND-NOT element, the output of the connected to the input of the node of the matching resistors and the information input of the node of the elements AND, the control input of which is connected to the output of the element AND-OR, the first and second inputs of which are connected respectively to the outputs of the first and second A group of NAND elements and control inputs of the second and third elements of NAND element, and a third input with a single output of the request trigger and an input of the second element OR NONE of the second group, the output of which is the output of the request for servicing the communication unit with the terminal and connected through the fourth element is NOT to the first input of the first NAND element, the second input and the output connected respectively to the trigger output of the start gate to the setup input of the request trigger, and the third input to the output of the first NOT element of the group, the first input of the third and third NAND elements to the sync input of the data entry counter, connected by the reset input to the zero output of the request trigger and the second input of the third NAND element, the output of which is the data input synchronization output of the communication unit with the terminal, the input input synchronization of which through the second element of the NOT group is connected to the input of the first element of the NOT group and the fourth input of the AND-OR element, the first inputs of the first and second elements of the NAND group are connected respectively to the first and second outputs of the counter s, and the second inputs - respectively to the output of the second NOT member rpynnbj request output unit and trigger a second input and 0 the output of the second element AND-NOT is connected respectively with the output of the second element of the IS-NOT group and the second input of the first element OR-NOT group, information input and output of the third node 5 elements AND-NOT are connected respectively to the output of the address set node to the information input of the node of elements I. 0 five 0 five . OAI  at 25 fZ not Data Strad 2 FI.3 Editor N.Rogulich Tehred I.Popovich Proofreader E.Sirohman Order 272/48 Circulation 673 Subscription VNNIPI USSR State Committee for inventions and discoveries 113U35, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, Projecto st., 4