SU1363230A1 - Device for interfacing two computers - Google Patents

Abstract

The invention relates to computing and can be used in the construction of multi-machine computing systems based on microcomputer bus. The aim of the invention is to increase speed. The device contains two blocks of bus drivers, two data registers, two registers of control signals and states, two blocks of main transmitters, two address decoders, two control blocks. 4 hp f-ly, 8 and l. from / about: so 00

Description

The invention relates to computing and can be used in the construction of multi-machine computing systems based on mini (micro) computers.

The purpose of the invention is to increase the speed.

Figure 1 presents the structural scheme of the proposed device; Fig. 2 is a functional diagram of the control and status registers; FIG. 3 shows the structure of the control unit; figure 4 - block diagram of the main transmitters; FIG. 3 is a functional diagram of an exchange control node; Fig 6 is the same as the direct access node; 7 is the same as the interrupt control node; on fig.Z - the temporary diagram of operation of the device in the mode of an exchange of arrays on the example of the cycle Output.

Microcomputer 1, containing central processor unit 2 (central processing unit 2), permanent storage device 3 (ROM 3), random access memory

4 (RAM 4) and a group of external devices

5 (WU 5), connected by trunk 6, via interface 7, is connected to trunk 8 of microcomputer 9 containing a central processor 10 (CPU Yu), permanent memory 11 (ROM P), random access memory 12 (RAM 12)

and a group of external devices 1 (WU 13

The structure of the device 7 includes (fig.O blocks 14 and 15 of tire formers (BSF 14 and BSF 15), tires 16 and 17, two data registers 18 and 19 (RD18 and RD19), tires 20 and 21, highways 22 and 23 , registers 24 and 25 of control signals and states (РУС 24 and РУС 25), each of which contains two mode triggers - Word by word 26 (TP P26) and Exchange arrays 27 (TPM 27), five memory management triggers : Prohibition of INPUT in ROM 1 / PZU2 28 (TRVVTS 28), Prohibition of INPUT in RAM 1 / RAM 2 29 (TRBVO 29), Prohibition of OUTPUT in RAM 1 / RAM 2 30 (TRVO 30), Prohibition of Enter in VU1 / VU2 31 (TRVVV 31), Prohibition of OUTPUT in VU 1 / VU 2 32 (TRVV 32); agistrali 33 and 34, blocks 35 and 36 of the main transmitters (35 BMP and BMP 36), tires 37 and 38, tires 39 and 40, decoders 41 and 42 adre-, s6v (DSHA DSHA 4 and 42), the tires 43 and 44

tires 45 and 46, control blocks 47 and 48 (CU 47 and COO 48), tires 49 and 50; each of the CU 47 and CU 48 comprises an exchange control node 51 (SSS 51), a forward access node 52 (CLC 52), a distress control node 53 (CIR 53); tires 54 and 55, highway 56, tires 57, 58 and 59.60, lines 61 and 62, tires

Q 63 and 64, lines 65 and 66, tires B7 and 68, bus 69, lines 70 and 71, lines 72 - 76 and 77 - 81.

In addition to the TRP triggers. 26, TRM 27, TRVVP 28, TRVV 29, TRVO 30, TRVVV 31,

5 TRBB 32, each of RUS 24 and 25 contains trigger 82 Exchange enable (TPP032), trigger 83 Error (TRO 83), trigger 84 Ready (TRG 84), AND-NE element 85, element

0 OR NOT 86, node 87 transmitters.

The lines 88 of busbars 68 and 67 are {fig. 3) the BUT 52-BU 47 and 48 inputs-outputs, their other inputs-outputs are the lines 89 of busbars 54 and 55;

5, the lines 90 of buses 67 and 68 are connected to the inputs-outputs of the SPS 53 BU 47 and 48, and the other inputs-outputs of the SPS 53 are the lines 91 of buses 55 and 54; line 92 bus 63 and 64 is the input of the UPR 53

0 БУ 48 and 47, and lines 93 tires 63 and 64 - by the input УУО 51 БУ 48 and 47; lines 94. buses 55 and 54 are the input-output of the CCD 51 BU 48 and 47, the entrance of the CCD 51 by bus 95 is connected to the output of the DAD 52.

Each of the BMPs 35 and 36 contains two nodes 96 and 97 of the trunk transmitters.

Each of the UUO 51 BU 47 and 48 contains receivers 98 and 99, transmitters 100 and 101, elements 102 - 104 delays, triggers 105 and 106, elements OR-NOT 107 and 108, elements OR 109 - 114, AND-NOT element 115, elements AND 116, element NOT 117. DFC 52 contains receiver 118, transmitters 119, delay element 120, AND-NO element 12.1, triggers 122, 123. UPR 53 contains receiver 124, transmitters 125, element. And 126, trigger 127.

Q The device works in two modes: Word-by-word exchange and Array exchange.

In the word exchange mode, one of the computers, for example, a computer, 1, polls

5 state of TRRO 82 RUS 25, the signal from the output of which via bus 69 is fed to the input of transmitter 87 RUS 24 and through the control signal from bus 70 from DSHA 42 is read in computer 1; if a

five

0

five

this trigger is installed, the computer 1 resets the similar trigger RUS 24 and sets TRP 26 РУС 24 "The signal from the output of TRP 26 over tires 68 and 90 sets to О the trigger 127 UPR 53 TU 47, from the output of which to the interrupt request line c. the highest priority of the highway 8 through the transmitter 125 on the bus 91 and 54 receives the signal TPD. The signal PIR of the highway 8 through the receiver 124 and the element And 126 sets at the outputs of the transmitter I25 the address of the interruption vector and the signal of the CIP, which through the buses 91 and 54 arrive at the highway 8. After that, the computer I enters the RD 18 and output information, while request, the interruption of the RD 18 appears an active signal, which via line 61 enters the inputs of the transmitters 87 of the ENG 24 and 25 and can be read into the computer 1 and 2 via a control signal from the bus 70 or 74 from the ASL 42 and 41. The computer 2, after interrogating this bit (in the program of processing the pre-edge for a given vector), it reads from RD 18. This can be a transition command to the maintenance routine of trunk 6 or the tuning routine of computer I to work with trunk 8, as well as other information. Information exchange in this mode is carried out through RD 18 BSF 15 or 19 BSF 14 through the interrogation of their requests for interruptions; Records and recordings from RD 18 or 19 are performed as follows,

DSHA 41, having inserted the address of the taxiway 18 in line 8, generates a signal that goes through the bus 50 to the first input of the element OR FROM UUO 51 BU 48 and through the element 116 to the bus 60 turns on the taxiway 18 to 45 is fed to the input of the element OR 109 UUO 51 BU 47

and through the elements OR NOT 108,

OR 111, 112, AND-NOT 115 via bus 57 turns on BSF 15 to receive, and information from the output of RD 18 via tires 22 and 17 enters trunk 8.

Writing to RD 18 is carried out from trunk 6 via bus 20. Lying on address RD 18, DSHA 42 generates a signal that goes through bus 46 to the first input of the OR 114 element and bus 60 turns on RD 18 to write. Similarly, recording and reading is carried out in RD 19,

The recording in RUS 24 carries out the computer 1 from the trunk, 6 via tires 16 and 22 through BSF 14, using a control signal from da1A 42, which via buses 46 and 59 through elements OR 112, AND-NE 115 includes BSF 14 to the transmission and bus 70 gates through inputs C the recording of information on the O inputs of the trigger trigger RU 24 from the bus 22. The recording of information in the RUS 25 is carried out in a similar way. To avoid conflict situations when writing information to ENG 24 or reading from RD 19, the signal from ASH 42 via bus 49 enters the second input of the IS-HE element 115 and prohibits the activation of BSF 15 for the duration of access to the registers, likewise. 25 and on the RD 18.

In the Exchange Arrays mode, one of the computers, for example, the computer 2, sets the TRM 27 trigger and the required memory management triggers, for example, the TRVO trigger 30. At the same time, the logical zero level on the bus 69 of the inverted output of the TPM 27 RUS 25 enters the zero input of the TPM 27 RUS 24 , prohibiting its installation. The signal from the output of the TRM 27 RUS 25 via bus 67 sets the trigger 122 DFC 52 BU 48, and a TSC signal is sent to the TPA request line of trunk 6 through buses 89 and 55 from the output of transmitter 119. After exchanging the standard signals for capturing the trunk from the output of the receiver 118 through the I-NE 121 element, the TCD is reset (by setting 1 trigger 122) and a trigger 123 is installed, from which the signal through the transmitter 119 via buses 89 and 55 enters the PV line of highway 6 The same signal on line 65 is fed to the control input of the node 97 of the BMP 36 transmitters, the control signals from the REMOTE outputs of the TRVVP trigger 28., TRVO 29, TRVO 30,. TRVV H 31, TRBB 32 bus 34 through the node 97 amplifiers on lines 72-76 enters the control, and the inputs of the receiver of channel signals Input and Output to the ROM 3, RAM 4, VU 5. Thus, the input of the receiver channel signal The output to RAM 4 via line 74 is allowed, and the control inputs of the remaining receivers are barring signals. The signal from the direct output of the trigger 123 on the bus 95 turns on the receiver 99, through the elements OR-

HE 107, 108 together with the signal from in-; l boiled trigger output 123 (on the bus 95, elements OR 110-12 and AND-NOT from) nQ bus 59 includes BSF 14 for transmission. The signal from the inverse trigger output 123 DFC 52 BU 48 via bus 67 is set by TRG 84 RUS 25. From the output of this trigger bus 64 and line 95 to the input of receiver 98 UUO 5 BU 47 channel signals SIA, WU, CIP from highway 8 receives the resolving signal , and to the input of the receiver of the channel signal, the enabling signal comes from the output of the TRVO flip-flop. 30 through the element OR NOT 86 on the tires 64 and 93. In addition, the enabling signal from the output of the TRG 84 RUS

I The signal from the output of the element IS-NOT 85 РУС 25 via buses 64 and 95 turns on the receiver of the channel signal. Entering the CCD 51 BU 47. Address transmission is carried out similarly to transmission ad25 via bus 64 arrives at the enabling input of node 96 of BMP 35.20 transmitters in a cycle Conclusion. from the output of node 96, the enabling signal, the signal input from the output of the receiver

98 UUO 51 BU 47 through delay elements 103 and AND 116 via bus 58 disconnects RD 19 from bus 23, and through elements 25 OR 109, 111,112, OR-NOT 108, AND-NOT 115 UUO 51 BU 47 via bus 57 includes BSF 15 at the reception. From the output of the transmitter GOO UUO 51 BU 47 via bus 56 and through receiver 99 and elements 30 ShJ-NOT

on line 79 goes to the channel signal receiver. Output to RAM 12. The device is ready for operation. Considering the trigger TRG 84 RUS 25, the computer 2 starts the exchange.

In this case, the SIA signal from the output of the element 98 of the CID 51 BU 47 through the elements OR 114 and 113, AND 116 on the bus 58 builds a record of information (address of the address) from the bus 21 to the taxiway 19 and turns on the taxiway 19 to read, while RD 19 via bus 23 via BSF 14 and bus 16; the address of the call enters trunk 6; the signal from the output of the request for breaking the RD 19 via line 62 through the element NOT 117 sets the trigger 105 of the CCD 51 BU 47; signal SIA through the transmitters 100 and 101 of the UUO 51 BU 47 and BU 48 and receiver 99 enters the trunk 6 (with some delay). Signal Output from trunk 8 via receiver 98 of the CID 51 BU 47 through the time determined by the delay element 104, through the AND element 116 via the bus 58 disconnects the RD 19 from the bus 23, and through the OR 110 elements 112, AND-NOT 11.5 through the bus 57 includes the BSF 15 on the re. cottage. Signal Output from the re-u exit. sensor 100 UUO 51 BU 47 through receiver 99, delay element 102 and transmitter 101 UUO 51 BU 48 via bus 55. enters trunk 6, after which CIP appears on highway 6, which through receiver 99 and transmitter

, 101 UUO 51 BU 48, via bus 56 through receiver 98 and transmitter

 CAS 51 BU 47. bus 54 enters the highway 8, pos.

107 and 108 UUO 51 BU 48 via bus 59. The output includes BSF 14 to receive and via transmitter 101 via bus 55 enters trunk 6. Computer 2, having received the data, sets

a CIP signal, which via bus 54 through receiver 100 and transmitter 98 UUO 51 BU 47, through bus 56 through receiver 99 and transmitter 101 UUO 51 BU 48 via bus 55 enters magistral 6.

4Q When accessing through the device

to the slave, the slave signal is detected on the trigger 106 and, together with the address, is transmitted to the slave computer mainline. At the end of the exchange, the computer 2 resets the TPM 27

45 RUS 25, in this case. On bus 67, trigger 123 DFC 52 BU 48 is reset and the device returns to its initial state,

In the word-wise mode the main mode is tuned.

50

Array exchange,

In the Array Exchange mode, one of the computers can be connected to the ROM 55 or (and) RAM, or (and) the VU of the other computer,. carry out an array view from RAM: or VU of its complex into RAM or VU of another complex of input-output data from VU of another complex into RAM.

3230

b

Vysod

ten

15

What is the end of the loop?

When entering information from the highway 6, the computer 2 sets the trigger (s) of the ENG 25 TRVVP 28 or (and) TRVVO 29 or (and) TRVVV 31. At the same time, bus 37 through BIP 35 and lines 77, 78, 80 is prohibited from passing through Signal input Entering into ROM 11 or (and) RAM 12, or (and) WU 13, and through bus 34 through BMP 36 via lines 72.73, 75 the signal is allowed to enter into ROM 3 Or (and) RAM 4, or (and) WU 5.,

I The signal from the output of the element IS-NE 85 РУС 25 via the buses 64 and 95 turns on the receiver of the channel signal. Input of the CCD 51 BU 47. Address transfer is carried out similarly to the transfer of ad0 Resa in the Output loop. Signal Input from receiver output

98 UUO 51 BU 47 through elements 103 of delay and AND 116 via bus 58 disconnects RD 19 from bus 23, and through elements OR 109, 111,112, OR-NOT 108, AND-NOT 115 UU 51 BU 47 via bus 57 includes BSF 15 at the reception. From the output of the transmitter GOO UUO 51 BU 47 via bus 56 and through receiver 99 and elements of SHZHE

107 and 108 UUO 51 BU 48 via bus 59. The output includes BSF 14 to receive and via transmitter 101 via bus 55 enters trunk 6. Computer 2, having received the data, sets

SIP signal, which via bus 54 through receiver 100 and transmitter 98 UUO 51 BU 47, through bus 56 through receiver 99 and transmitter 101 UUO 51 BU 48 via bus 55 enters trunk 6.

When accessing through the device

to the slave, the slave signal is detected on the trigger 106 and, together with the address, is transmitted to the slave computer mainline. At the end of the exchange, the computer 2 resets the TPM 27

RU 25, while on bus 67, trigger 123 DFC 52 BU 48 is reset and the device returns to its initial state,

In the word-wise mode the main mode is tuned.

Array exchange,

In the Array Exchange mode, one of the computers can be connected to the ROM 55 or (and) RAM, or (and) the VU of the other computer,. carry out an array view from RAM: or VU of its complex into RAM or VU of another complex of input-output data from VU of another complex into RAM.

or the VU of its complex. This allows, in addition to the exchange function, to perform various modes of equipment redundancy using the proposed device.

A trigger for the SRW 83 Error was introduced to organize the backup mode, which is established by means of the control of one computer and read through the PC of the other computer. Having considered it, the computer through the machine-to-machine exchange device can be connected to the mag- netral of the failing computer and continue with the execution of the program.

Claims (5)

Formula iso p et e and n 1. A device for interfacing two computers, containing two data registers, two control signal registers and states, two address decoders, two control units, the groups of information inputs of the first and second data registers form groups of device inputs for connecting to groups of information outputs the first and second computers respectively, the first groups of information outputs of the first and second control signal registers and states form the device output groups for connecting to the control groups of the 1x inputs of the co respectively the first and second computers, groups of inputs of the first and second desh-. “With the conditions of which are connected with the third address fragments form device input groups for connecting the first and second computers to the address output groups, respectively; the first input / output groups of the logic conditions of the first and second control units form the device input-output groups for connecting to the control input / output computer groups of the first and second computers, respectively , while the first group of outputs of the first control unit is connected to the group of recording / writing inputs of the first data register, whose information output is connected to the input of logical services The first control unit, with the first information input of the first control signal and state register and the first information input of the second control signal and state register, the second information input of which is connected to the second information input of the first control register 40 45 50 55 groups of outputs of the first and second decoders of the address, respectively; a third group of inputs-outputs of the logic condition of the first control unit is connected to the third group of inputs-outputs of the logic condition of the second control unit, characterized in that, in order to improve speed, two sets of bus drivers and two blocks of main transmitters, the groups of information inputs-outputs of the first and second blocks of bus drivers form the groups of inputs-outputs of the device for connection to the groups the memory of information inputs-outputs, respectively, of the first, second computer, groups of information outputs of the first, second mainstream transmitters form groups of device outputs for connection to groups of request inputs, respectively, of the first, second computer, while the second group of you five 0 five 0 signals and status, with the logical condition input of the second control unit and with the information output of the second data register, the group of write / read inputs of which is connected to the first output group of the second control unit, the input permitting group of which is connected to the second group of information outputs of the second control register signals and states, the first group of information inputs / outputs of which is connected to the first group of information inputs / outputs of the first register of control signals and the state, second the group of information outputs of which are connected to the group of permitting inputs of the first control unit, the first groups of inputs of the logical condition of the first and second control blocks are connected to the first groups of outputs of the first and second address decoders, respectively, the second groups of outputs of which are connected to the groups of write / read inputs of the first and second, respectively control signal and status registers, the second groups of information input-outputs of which are connected to the second groups of input-output logic conditions of respectively the second and first control units, the second group of logical inputs 0 five 0 five groups of outputs of the first and second decoders of the address, respectively; a third group of inputs-outputs of the logic condition of the first control unit is connected to the third group of inputs-outputs of the logic condition of the second control unit, characterized in that, in order to improve speed, two sets of bus drivers and two blocks of main transmitters, the groups of information inputs-outputs of the first and second blocks of bus drivers form the groups of inputs-outputs of the device for connection to the groups the memory of information inputs-outputs, respectively, of the first, second computer, groups of information outputs of the first, second mainstream transmitters form groups of device outputs for connection to groups of request inputs, respectively, of the first, second computer, while the second group of you 9 the strokes of the first control unit are connected to the group of control inputs of the first block of bus drivers, the group of information outputs of which is connected to the group of information outputs of the first data register, the group of information inputs of the first register of control signals and the state, and the group of information inputs of the second block of bus drivers, the group of information outputs of which is connected to the group of information inputs of the first block of bus drivers, with the group of information outputs of the second re A data source and a group of information inputs of the second register of control signals and a state, a group of control inputs of the second block of bus drivers are connected to a second group of outputs of the second control unit, the outputs of the first and second control blocks are connected to the first permitting inputs, respectively the first and second blocks of the main transmitters, the second permitting inputs of which are connected with the higher bits of the second groups of information outputs of the first and second control registers, respectively incoming signals and condition, the third group of information outputs of which are connected with the first groups .informatsionnyh input, respectively of the first and second blocks of the main transmitter, group of information inputs of which are connected with the fourth group of information outputs of the first and respectively Bjroporo registers control signals and conditions. 2. The device according to claim 1, wherein each of the control blocks comprises a direct access node, an interrupt control node, an exchange control node, the first groups of control inputs / outputs of the direct access node, interrupt control node and the exchange control node form the first group of input-outputs of the logic condition of the control unit, the second group of control inputs-outputs of the direct access node, the interrupt control node form the second group of input-outputs of the logic condition of the control unit, the second groups actuating unit inputs-outputs one ten 15 25 2 6323010 exchange control unit forms the third group of input-outputs of the logic condition of the control unit, the enable input of the interrupt control node and the group of enable inputs of the exchange control node form the group of enable inputs of the control unit, the first and second groups of inputs of the logical condition of the exchange control node form the corresponding logical inputs the conditions of the control unit, the input of the logical condition and the first, second group of outputs of the exchange control node form respectively the input of the logical and the first condition, -sec group control unit outputs output unit direct access is the output of the control unit, the group of outputs direct access node connected to the third group of inputs of the logical control node exchange conditions. 3. The device according to claims 1 and 2, o t is characterized by: the fact that the exchange control node contains two copies | editor, two receivers, two triggers, AND element, 30 NAND element, two OR-NOT elements, six OR elements, NOT element, three delay elements, the first, second, third, fourth information inputs of the first receiver, (- first information output of the first transmitter, the first, second, third, fourth information outputs of the second transmitter, the first information input of the second receiver form the first group of control inputs-outputs of the exchange control node, the fifth information input of the first receiver, second, third, quarters first, fifth, first, third, third, fourth, fifth, information inputs of the second receiver, fifth information output of the second transmitter form the second group of control inputs and outputs of the exchange control node, first inputs of the first, second of the third element OR form the first group of inputs of the logical condition of the control node; by the exchange, the first inputs of the NAND element and the fourth element OR form the second group of inputs of the logical condition of the exchange control node, the first input of the first element OR NOT connected to 40 45 50 55 eleven the enable input of the second receiver, and the first input of the fifth element OR form the third group of inputs of the logical condition of the exchange control node, the input of the element is NOT the input of the logical condition of the exchange control node, the first enable input of the first receiver connected to the second and third permitting inputs of the first receiver, the fourth, fifth permitting inputs of the first receiver form a group of permitting inputs of the exchange control node, the output of the element And connected to the zero input of the first trigger, and the output of the third The OR elements form the first group of outputs of the exchange control node, the outputs. Of the second OR element and the NAND element form the second group of outputs of the exchange control node, while in the exchange control node, the output of the element is NOT connected to the synchronous input 13 the second trigger, the output of which is a co-25 transmitter, receiver, element I, is triggered with a permissive input permit, and the information input of the transmitter, the first information collector, the first, second, third, four-input which is connected to the information source, the fifth information output and zero inputs of the second trig thirty gera, with the first information output of the first receiver, with the second input of the third OR element, with the second input of the fourth OR element, the output of which is connected to the first input of the AND element, the second and third inputs of which are connected to the first outputs of the first and second delay elements, respectively connected respectively to the second and third information outputs of the first receiver, the fourth information output of which is connected to the synchronous input and information input of the first trigger, the output of which is connected to the second information input of the first transmitter, the third information input of which is connected to the fifth information output of the first receiver, the second input of the NAND element is connected to the output of the second OR element, the second input of which is connected to the output of the sixth OR element, the first input of which is connected to output n - 35 40 the transmitter, the trigger synchronization form the first group of control inputs-outputs of the interrupt control unit, the output of the And element connected to the first, second, third information inputs of the transmitter, and the information input of the trigger form the second group of control inputs-outputs of the interrupt control node, the first the transmitter enable input is the enable input of the cropping control node; in the interrupt control node, the zero output of the trigger is connected to the fourth information input of the transmitter and to The first input element And, the second 45 input of which is connected to the information output of the receiver and the second permitting input of the transmitter, the fifth information input of which is connected to the single output of the trigger, 5. The device according to Claims 1 and 2, characterized in that the direct access node comprises a receiver, a transmitter, a delay element, an NAND element, two triggers, and in 50 of the OR element, the second input is the receiver's first input. connected to the second input of the second delay element and to the fourth information input of the first transmitter, the fifth information input the second, third, information outputs of the transmitter form the first group of control inputs-outputs of the direct access node, the synchronous input of the first . Q J 36323012 which is connected to the second output of the first delay element and to the second input of the first ISh1 element, the output of which is connected to the second input of the sixth OR element and to the first input of the second OR element, the second input of which is connected to the output of the first OR element, the second input of which connected to the first information output of the second transmitter and the first information input of the second receiver, the second, third, fourth and fifth information inputs of which are connected respectively to the second, third, fourth information outputs of the second transmitter and the outputs of the third delay element, the input of which is connected to the fifth information output of the second transmitter. 4. The device according to claims 1, and 2, about t - is characterized by the fact that the node controlling the interruption contains ne 20 editor, receiver, element I, trigger, and the information input of the receiver, the first, second, third, fourth, fifth information outputs the transmitter, the trigger synchronization form the first group of control inputs-outputs of the interrupt control unit, the output of the And element connected to the first, second, third information inputs of the transmitter, and the information input of the trigger form the second group of control inputs-outputs of the interrupt control node, the first the transmitter enable input is the enable input of the cropping control node; in the interrupt control node, the zero output of the trigger is connected to the fourth information input of the transmitter and to rvym input AND gate, the second input of which is connected to data receiver output and the second enable input of the transmitter, a fifth informational input coupled to the output latch unit, 5. The device according to Claims 1 and 2, characterized in that the direct access node comprises a receiver, a transmitter, a delay element, an NAND element, two triggers, and the second, third, information outputs of the transmitter form the first group of control inputs-outputs of the direct access node, the synchronous input of the first a trigger connected to the zero input of the second trigger, a zero output BTopjoro trigger connected to the first information input of the transmitter, form the second control input-output node of the direct access node, the single output of the second trigger connected to the second information input of the transmitter and is the output of the output node access, zero and single outputs of the second trigger form a group of all-node direct access nodes, while at the direct access node a different The transmitter's crucial input is connected to the output of the delay element, whose input is connected to the information output of the receiver and to the first input of the NAND element, the output of which is connected to the single input of the second trigger and to the single input of the first trigger. The zero output of which is connected to the third information input of the transmitter and to the second input of the NAND element, the information input of the first trigger is connected to the zero potential bus of the device. I. S8 {e7) - 69 h J3 / J "j | l 38 (37) l i ui {: 22 {Z3) 6 SO 61 46 / 6tf) (fff) (S2} (4S) Figz 0tfS.f BJ ) (W. Well ftM toa with n fpUiB and -i / pofeHA cuiHOjro not t / freem iwrveffM J-ctitHOJi HO & roffe ycmfloe / c / nSa 2- c l / i a / r HP Sduofe ycmpouc / nSa Editor A.Makovska Compiled by S. Pestman Tehred M. Didyk Order 6364/42 Circulation 671 Subscription VNIIPI USSR State Committee on affairs of inventions and discoveries - 113035, Moekva, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader I. Muska