SU1262512A1 - Interface for linking computer with communication lines - Google Patents

Description

11 The invention relates to computer technology and can be used to exchange information via communication lines of electronic computers, for example, Electronics-60 type, located at significant distances and included in a hierarchical structure. The aim of the invention is to increase the capacity of the device. Figure 1 presents the block diagram of the device; in fig. 2- an example of a system using the proposed device; in fig. 3 - structural scheme of one of the registers of the control-reception-transmission; Fig. 4 is a block diagram of a transmitter of a buffer memory unit; Fig. 5 is a block diagram of a receiver of a buffer memory unit; Fig. 6 is a block diagram of the linear signal generation unit; Fig. 7 is a block diagram of the gain unit; Fig. 8 is a structural scheme for generating an address; in fig. 9 is a block diagram of the state register and control; in fig. Yu-- block diagram of the generation of exchange cycles; FIG. 1 is a block diagram of a communication link response signaling unit; on Fig - structural diagram of the decoder; in fig. 13 is the interrupt request processing unit circuit diagram. The device (Fig.) Contains registers 1 of control of reception and transmission, blocks 2 of buffer memory, blocks 3 of forming linear signals, block 4 of amplification, address forming unit 5, register of state 6 and control, block 7 of generating exchange cycles, link response signal generating unit 8 (synchronization of the passive device — SIL, decoder 9, interrupt request processing block 1, input-output 11, and line inputs and outputs 12 of the device. The transmit and receive control registers 1 generate control signals for the corresponding blocks 2 and stored information about the data received and transmitted in the device, form Response signals (TSS) when accessing them or executing the address operation on the corresponding blocks 2, control the generation of the interruption request signal (RFP). 12 Blocks 2 of the buffer memory they are intended to convert parallel data code into serial and vice versa and generate control signals and state signals in the process of data transmission between remote computers. The 3 3 linear signal generation units are designed to convert a unipolar signal into a powerful two-pole linear signal and vice versa. Amplification unit 4 performs buffer functions between the internal signals of the device and the signals of the computer channel. The address builder 5 is designed to decrypt the register addresses and device blocks and store the address code throughout the entire cycle of the device access cycle. The status and control register 6 is intended to store information about the interrupt resolution of the device, about the state of the blocks included in the device code, about the general reset signal for the blocks. The exchange generation unit 7 is designed to generate address and control signals necessary for accessing registers 1 and blocks 2. Block 8 is designed to generate a synchronization signal of a passive device for the operation Input or Output. The decoder 9 is designed to decrypt and form control signals for writing or reading the contents of the registers and blocks of the device, as well as for issuing a CIP signal by a signal from block 8 or in an interrupt loop. The interrupt request processing unit 10 is designed to request a computer program interruption request to perform a computer channel capture operation in order to transmit an interrupt vector code corresponding to the active requestor in the device. The input-output P of the device is intended for connection to a computer channel, for example, a micro-computer. Line inputs and outputs 12 devices are designed to connect communication lines. In FIG. 2, the first computer 13 is designated, the first device 14, the communication line 15, the second device 16, the second computer 17, the Transmit-Receive Control Registers I contain (FIG. 3) the element OR 18, the element NOT 19, the triggers 2024, the element OR 25, element AND 26, element OR 27, elements AND 28-37, elements OR 38 and 39, the first, third and second information inputs 40, 41 and 42 of the block, the third, second, first and fourth outputs 43, 44, 45 and 46 blocks. The buffer memory unit 2 consists of a transmitter and a receiver. The transmitter of block 2 contains (FIG. 4) node 47 of elements I, elements SH1I 48 and 49, generator 50 of pulses, counter 51, buffer register 52 of the transmission, elements 53 and 54 of delay, modulator 55, node 56 of parity, element OR 57 triggers 58 and 59, elements AND 60-62, -first information output 63 of block 2, Receiver of block 2 contains (FIG. 5) counter 64, element OR 65, demodulator 66, element AND 67, trigger 68, element OR 69, HE element 70, AND elements 71. and 72, HE element 73, receive buffer register 74, AND element 75, delay element 76, AND node 77, odd parity node 78, element 79, first information input 80 of block 2. Line signal generating unit 3 consists of two independently operating output signal generator 81 and input signal generator 82 (FIG. 6). Shaper 81 is designed to convert a unipolar signal at the input to a powerful two-pole signal with amplitude 12V output. A shaper 81 is a push-pull amplifier made according to a transformer circuit. Shaper 82 is designed to convert a two-pole signal at the input to a unipolar output and is a push-pull amplifier with a transformer coupling. The imaging unit 81 has a second input 63 for signals F1 and F2, a first input 83 for receiving information from a communication line, a first output 84 for transmitting information to a communication line, a second output 80 for transmitting signals for FZ and F4, Gain unit 4 contains (Fig , 7) multiplexer 85, node 86, receiver of computer channel signals, bus driver 87, node 88, signal transmitters to computer channel, node 89 receiver of computer channel signals, third, first, second inputs 90-92 of block 4, input-output 93 of block 4 the third, first and fourth outputs 94-96 of block 4, the address shaper 5 contains (Fig. 8) groups NOT elements 97, address register 98, decoder 99, the switching field LE, AND gate 101, an OR gate 102, flip-flop 103, decoder 104, AND gate 105, the second, third and first outputs 106-108 of register 5. The status and control register 6 contains FIG. 9, an AND element 109, triggers 110-112, a reset input 113, the first and second synchronization inputs 114 and 115, the third, second and fourth outputs 116-118 of register 6, the exchange cycle generation block 7 contains (Fig, 10) element NOT 119, elements OR 120, element AND 121, elements AND-OR 122, generator 123 pulses, element AND 124, a group of elements. And 125 node amplifiers, trigger 126, counter 127, element NOT 128, decoder 129, element 130, elements And 131-135 of node amplifier, inputs 136 and 137 of synchronization and reversal, and output 138 of synchronization of block 7 connection contains (FIG. II) the AND element 139, the NOT 140 element, the delay element 14, the AND elements 142 and 143, the OR element (44, the trigger 145, the reverse input 146 and the response signal output 147. The decoder 9 (FIG. 12) contains elements HE 148 and. 149, elements OR 150 and 151, element OR 152, elements and 153-160, third information input 161 and second output 162 of the decoder The interrupt request processing block 10 contains (FIG. 13) a request masking register 163, a request register 164, an AND 165 element, a HE 166 element, an AND trigger 167, an AND node 168, an AND 169 element, an encoder 170, and OR 171 and 172 elements, Operation The device is considered on the example of the system (FIG. 2). The device exchanges data between block 2 and the microcomputer under the control of a program using the interrupt mode, converts information from a parallel code to a serial one and writes it to a line, receiving information in a serial code from l SRI communication, transform it into a parallel code is assumed $ 1 that one of the computers is initiated exchange of information, such as computer 13 and other computers 17, e.g., configured for rapid response available in .informatsiey remotely distributed system. There are several such initiators of information exchange, such as a computer 13, in the system, each of which is connected to a computer 17 by means of a device 16 by means of a line 15 communication line. The initiator of the exchange of one of the microcomputers needs to be in intensive mode. information exchange in a remotely distributed system. Otherwise, a conflict situation may arise, when on line 15 simultaneously from two sides (computer side 13 and computer side 17) information is transmitted. In this case, the loss of the transmitted information is possible. The device works as follows,. When the system is turned on or the program is started up in the computer 13 and 17, the CBSRN signal is produced to bring the external devices of the micro-computer channel to the initial state. This signal passes through the receiver node 86 and goes through the output 42 of the latter to blocks 5, 6, 7 and 10 of the device, where it performs the initial setup: trigger 103, trigger 112, Response blocks, trigger 126 triggering the circuit through the circuit: input 117 , element OR 120, trigger reset input G26; register 163 for masking requests, trigger 167 for traversing the circuit, element NOT 166, reset input for trigger 167j, trigger 110 for the DCS (6), for clearing the circuit fault: element OR 172, output 113, reset input for the trigger 110; trigger 11I bit General reset (OSBR) along the circuit: element OR 120, output 115, element AND 109, reset input of the trigger 111. Restoring registers 1 and blocks 2 to the initial state before starting to exchange information is performed by a signal General reset ( IOSBR formed at the output of the element And 13 of block 7, IOSBR signal is received through the input 41 of registers 1 and resets 126 flip-flops 21 bits Ready for transmission (TRP-PER), as well as triggers 20, 23 and 24 bits (BSER), Error of the error bits and parity error (error), In blocks 2, the IOSBR signal performs sat The transmission register 52 grew, the triggers 58 and 68, the register 74, as well as the triggers included in the demodulator 66 and the counter 64. In addition, the IOSBR signal on the OR 69 element converted into the R-TPD signal is output to output 40 and in registers 1 through the element NOT 19, it triggers reset of trigger 22 bits Ready for Reception (TRP-PR). IOSBR signal is generated in block 7 with active status of OSBR generated by direct output of trigger 11I of register 6, and set to state 1 of the trigger cycle 126 exchange cycle. Since the exchange of information is supposed to be performed in the interrupt mode, it is necessary to set the 1 and the digit of the DCS (6) to enable the software to interrupt the trigger of the register 6. Setting the state 1 of the trigger 110 and 111 of the register 6 is fulfilled using the software program develop the DCS (6) - interrupt resolution and OSBR) at the address of register 6. For this purpose, the corresponding computer in its channel sets the address of the register 6 on the KDA bus (00-15), KVUN signals External device and XIAN (Synchronization active. Availability of these signals to the can a computer means the execution of the address part of the cycle of accessing an external device (WU), which is currently the proposed device. These signals are blunt on the input-output 93 of block 4, where, having passed through the driver 87 and elements of node 89, are, respectively, at inputs 42 and 96 of the mapper 5. In the latter, the address of the slave set on the KDA bus (00-15) of the computer channel, if it belongs to the device, is memorized. Decoding is subjected to higher address bits, which are received at input 42, and in case the address assigned to the device by means of switching field 100 coincides, a high level signal is stored at the output of element 10, which is stored on trigger 103 by the SIL sync signal. The minor bits of the address are fed to the inputs of the register 98, and when the output level of the AND 105 element appears, the active level of the VUS signal is memorized in it. The decoder 104 decrypts the low-order bits of the address to determine which register is being accessed. In this cycle, access is made to register 6, therefore, at the output of the decoder 104, an active signal of the ABS is formed, which allows the operation of the decoder 99, at one of the outputs of which the active AGC signal appears. At this point, the address part of the HLC cycle ends. Further, the information part of the circulation cycle is performed. On information buses, the computer exposes the code to be set in 1 trigger 0 and 111 of register 6. Signals KWINS and KBAITN are switched to the active state. Passing through the elements AND of node 86 of block 4, these signals enter the decoder 9, where with the participation of signals A (00), AGC on the elements NOT 148, AND-OR 151, AND 153 and 154, signals of the SMPRU and APSRU are written to write to the junior and senior Register 6 bids, ZPMRU and SPSRU signals come to I 14 register 6 and set the software triggers and 111 to the state corresponding to the availability of information from their D inputs, where the YES (06) and YES (08) signals respectively . The OSBR signal from the inverse output of the trigger 1 1-1 on the AND element 142 of block 8 prohibits the delay of the signal 141 held on the element 141 from the output 146 of the decoder 9. The OSBR signal from the direct output of the trigger 11I enters the block 7, where the AND-OR element 122, together with the signal of the MAS, enters 5 5 - trigger input 126. The Vdshod signal from input 95 through AND 156 and 139 elements and the delay element 141 in the form of LZ signal is fed to the C input of the trigger 126 and sets it to state, forming on the element And 13 signal IOSBR. In addition, the signal of the OSBR over the circuit through the elements NOT 128, And 130 of block 7 prohibits gating the signals of the addresses of registers 1 and blocks 2 and the signals of IPT and IST of writing and reading these registers on the elements 125, 134, 135, respectively. The signal from the direct trigger output 126 allows the generator 123 to work. When the active signal appears at the last output of the decoder 129 through the OR element 120, the trigger 126 is reset and the POSBR signal (End OSBR) is generated, which is reset via the AND element 109 and the 111 trigger. the falling edge of the OSBR signal from the inverse output of the trigger 11I through the element AND 142, OR 144 is set to the one state of the trigger 145 and the CIP signal is formed during the Enter or Vyshod operations. The TGSIP signal from the direct output of the trigger 145 enters the decoder 9, where the SIP signal is generated at the OR 152, AND 160 S1 elements from the AND 156 element output, which is transmitted through the And element 88 of the unit 4 of the computer channel to the CSIPN line. The computer, having received the signal KSIPN, ends the cycle of addressing the slave. At the same time, information is removed from the KDA information buses and the signals KVYVODN, KBAN, XIAN. To ensure the operation of devices 14 and 16 in the abort mode, the corresponding computer must unmask the requests from register 1. Each request signal of the RFP (k-1, M) received into the request register 164 of block 10 corresponds to a certain bit of register mask 163. To unmask the PSC requests, it is necessary to set the corresponding bits of the trigger 163 in a single state, which is performed by the computer program in the access cycle at the register address 163 of the mask. The write operation to the mask information register 163 occurs in the same way as the write operation to register 6, however, in this case, the write signal from the EPRMZ is generated in the decoder 9, which, from the output of the AND 155 element, enters the input of the recording register gate 163, The elements are formed through AND elements 156 and 139, delay element 141, AND elements 142, OR 144, trigger 145, elements OR 152, and 160. Having completed the preparatory operations, the computer 13 organizes the transmission to the device 14 of information, which between computer 13 and computer 17 is perceived as control information or as information for processing. To transfer data to device 14, it is necessary to form a request Hf

912

Prejugation in the computer 13 from this device, is accomplished with this purpose. the write operation of logical I to the readiness trigger 21 of the transfer of the corresponding register 1. The write operation is executed at the address of the h-per 1 horn, and the register 1 address from the corresponding output of the decoder 104 enters through the output 106 of the driver 5 to the appropriate one. . input elements And 125. The trigger 126, on the D-input of which enters the logic. along the circuit of elements HE 119, AND-OR 122, in the presence of a BEAD signal and the absence of an ABS signal, is set to a state. the LZ signal at the input 136, the generation of the exchange cycle starts, during which the ITSKL and ISTR signals are generated at the I 132, 133 elements, and the AND output element is gated by the control and address inputs at the I 25 elements AND 25 elements information. Writing 1 into the transmission readiness trigger 21 occurs along the circuit of the AND 35, 36 and OR 39 elements. When the write operation is executed in the required register, the TL response signal is generated on the OR 38 element, which goes to the trigger 12, as well as the And 143 element of the block 8, thereby resolving the passage of the STROBE pulse through the elements AND 143 and OR 144 and the trigger 145 to form the response signal CIP,

The state of logical 1 at the direct output of the trigger 2 causes the formation of a request for the CSC from the corresponding register 1k on the OR element 27, which goes to one of the information inputs of the register 164 of the request, Next to the registers 163 and 164 and the elements of AND 168, OR 171 and AND 165 A signal is generated. The requirement to terminate a TFR to interrupt a program in a computer 13

If this request is given priority over the executed program and other incoming requests, the computer 13 stops the main program and goes to the interruption service. To this end, the computer 13 sets the channel KVDODN and then the Enable interrupt signal KlfflPlH,

The Input signal, when a TPR signal is present, sets interrupt trigger 167 to the state. At the exit

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element 169 in the state of the trigger 167 and the signal R1R1, a PREP signal is generated, which in the decoder 9 on the elements 158 and 159 generates the signals UM-, UM-2 control multiplexer 85 of block 4, and the vector code appears at the outputs of the latter interrupt the highest priority of the requests of the RFP formed on the encoder 170 of block 10, the formation of the response signal of the CIP is formed by the circuit of the elements OR 152 and 160 and the computer 110 is reset by the device OR 172 simultaneously; vector pr rshani with SIP signal, removes KVVODN signals KSH1R1 and proceeds to query processing routine of device. In this case, the computer 13 initiates the operation Enter for the contents of the register, which put forward the request for PLC, the information contained in the register 1 K is read, it is going through the circuit of elements 26, 28-32 with the help of signals ИАRUPPk and И ИБТ,

When executing an interrupt handling routine, it is necessary to restore state 1 of the sixth bit of register 6 to ensure further operation in abort mode. The computer 13 analyzes the contents of register 1k: And, having determined the readiness for transmission, proceeds to write operations to block 2k,.

Claims (2)

The information, in the form of a data byte, is received at input 42 through node 47, where it is gated with a write-down signal to the transmit register, at the input of transmit register 52. The signal ЗПРПЕР enters the inputs of the register 52, which are respectively stop and start bits of the information word, through the OR 49 element performs a preliminary reset of the transfer register 52 and through the OR 48 element and the delay element 53 - the subsequent recording of information in the register 52, Od | At the same time, the signal ZPNPER is fed to the input of the trigger 58 and sets it to state 1. This circumstance allows the passage of a series of pulses produced on the counter 51 through element 61 to set to state 1 of the trigger 59, thereby allowing the passage of a series of pulses through element AND 62, from the output of which the clock pulses are fed to the input of the information shift gate in register 52 and to the input of the modulator 55. The APER signal from the output of the OR element 48 through the OR element 18 is fed to the input of the trigger 21. The transmission readiness signal is removed. Modulator 55 receives register information 52 in a sequential code. After reading the entire word from register 52, flip-flop 58 is reset, which in turn flushes flip-flop 59. Reading information from register 52 to modulator 55 stops. A modulator 55 provides a phase pulse modulation method for information. This method combines the principle of phase manipulation by 180 and impuls modulation. The imaging unit 8 converts one polar modulated pulse signals from the outputs of the modulator 55 into a two-pole signal. The code of logical 1 is represented as a signal of a positive polarity in the first half of the period and a signal of negative polarity in the second half of the period. And the code of logical O is represented as a signal of negative polarity in the first half of the period and a signal of positive polarity in the second half of the period. The device 14 after the completion of the transfer word. information on communication line 15 is awaiting a response from device 1 about the transmission results. Information through the communication link 15 is fed to the input of the device 16 and through the driver 82, the demodulator 66 to the inputs of the register 74. The demodulator 66 implements a relative method for separating the signals of logic 1 and О based on the separation of the alternation of polarities of signals coming from zi The direct and inverse information word codes obtained at the output of the demodulator 66 sequentially arrive at the inputs of the register 74. The synchronization inputs of the triggers of the register 74 from the output of the demodulator 66 receive the sync pulses generated by each bit of the received word. When the start bit of the information word enters de modulator 66, state 1 triggers 68, which allows passage of a series of clock pulses from the output of counter 51 through element I 71 to the count input of the bit 64 bits of the word. The matching circuit on the AND 67 element is tuned to the code of the number of bits in the received word. When the counter 64 counts the set number of pulses, a reset trigger 68 is generated on the AND 67 element through the OR 65 element, which will prohibit further operation of the counter 64, At the same time, the 70 bit signal of the end of the word bits is sent to the AND 72, 75 elements through the HE element. where it is compared with the state of the last bit of register 74, the last bit of register 74 records the start bit of the information word, which is always logical 1, so if there are no errors, the bits in the word are not lost when transmitting it through line 15 zi then the start bit will reach the last bit of register 74 at the moment when the word bits end signal is generated, and the TRO-PR readiness signal is generated on the AND 75 element, and the NO 73 element on the And 72 element will prohibit the generation of a loss of error signal. If there is an error of incorrect transmission of logical 1 or 0 in the receiving word, then node 78 will generate an error parity error signal. Any of the TRP-PR, ОШБ or ОШЧ signals enters the register 1k, where it sets the corresponding bit to state 1 (triggers 22, 23, 20, respectively). Any of these bits set to state 1 ensures the formation on the element OR 27 request for interruption of the RFP, coming through the block 10 on the KTPRN bus of the computer channel 17, computer, 17, having received the request for interruption, enters the subprogram processing-. If the analysis resulted in errors in the transmission of information, the computer 17 places the device 16 in the transfer mode and generates a message to the computer via the communication line 15 that the received information word is erroneous. If, as a result of analyzing the contents of register 1, no errors were detected, then the computer 17 reads the contents of register 74 of block 2k in the Entry access cycle to the device 16. At the same time, information from register 74 is transmitted 131 through node 77 using the CHTP signal, which later through delay element 76 and the OR 69 unit clears the register 74, the counter 64 and the trigger 22. At the same time, the PTPF signal arrives at the input of the transfer register 52 and the pushing of the response code about the word reception into the lines (P + 4), (P + 5) occurs 15 communications. The start bit of register 52 remains in the zero state. The response of the reception of the array through the link 15 of the generator 82 enters the demodulator 66 of the device 14, and the first received bit is the logical O bit, which in the demodulator 66 forms the response signal of the OPD receiver, which through the OR 39 element sets trigger 21 bits of readiness for transmission, computer 13, after analyzing in the subroutine of processing the alarm, caused by the set trigger 21, the contents of register 1, notes the correct execution of the transfer of a word of information and proceeds to transfer the next word inf rmatsii. The message on line 15 from computer 17 to computer 13 that the received information is erroneous is characterized by the presence of logic 1 in the bit (P-1-4). Thus, when writing this message to the register, 52 bits (P + 4) and (T1 + 5) |, which is the starting one, set: to 1. When this message is received in register 74, an error signal is transmitted to the element 79 at the AND79, which sets state 1 to trigger 20, computer 13, to analyze the contents of register 1, detects the transmission error message and makes a decision for further action but the exchange of information with VM 17, a similar operation is performed gateway device to communicate to other computers in a multi-machine system. Claim 1, A device for interfacing a computer with communication lines, comprising a gain unit, the input-output of which is connected to the input-output of the computer, the decoder the first information input and output of which are connected to the first input 12I4f and the output of the amplification unit, and the second information input - to the first output of the address resolver, the information input of which is connected to the second output of the amplification block, the interrupt request processing block, the interruption request output, the information input and the permission enable output The drives are connected respectively to the second input, second and third outputs of the gain unit, and the synchronization input with the second output of the decoder, the status and control register, the first output connected to the third input of the gain unit, and the first information and synchronization inputs, respectively, with the second output of the gain unit and the third output of the decoder, the exchange cycle generation unit, the reset input and the output of the reset gates, respectively, are connected to the second output and the second synchronized input register state and control, and information input and access input, respectively, to the second output of the address generator and fourth output of the decoder, the group of linear signal generation units, the first inputs and outputs of which are the linear input and output devices, a group of buffer memory blocks and a group of reception-transmit control registers, the second input and the output of each block forming linear signals of the group are connected respectively by first information output and input corresponding the group buffer memory block, the output of the error signals and the exchange mode input of which are connected respectively to the first information input and the first output of the corresponding receive-transmit control register; the second information inputs of the group's buffer memory blocks and the receive and transmit control registers of the group are connected to the second output of the block gain, the fourth input of which is connected to the second outputs of the control register of the transceiver, the third information inputs and the third outputs of which are connected respectively with the output of the exchange mode signals of the exchange cycle generation block and the reset inputs of the buffer memory blocks of the group and with the input of the interrupt request signal of the interrupt request processing block whose input has a resolution 1512 of which is connected to the third output of the status register and control, which is the purpose of increasing the capacity of the device, the block forming the reaction signal of the communication line is entered into it, the fourth outputs of the control registers of the reception and transmission of the group are connected to the second information input register state and the control input and the response signal line forming block reaction communication signal, output and clock input and whose reset input are connected respectively to the input and The yields. synchronization of the exchange cycle generation block and the fourth output of the state register and control, the reset input connected to the reset output of the interrupt request processing block, the output of the interrupt signal of which is connected to the third information input of the decoder, the fifth output and the fourth information input connected respectively to the access input and the output of the response signal of the communication line response signal generating unit, the resolution input of which is connected to the third output of the address former, synchronizing whose input is connected to the fourth 216 output of the gain unit, the second information outputs of the buffer memory blocks of the group are connected to the third input of the gain unit, 2. The device according to claim 1, 1 and 2, such that the communication link response signal generating unit comprises a trigger, three AND elements, an OR element, a delay element and an NOT element, the first input of the AND element being the input of the block, and the output is connected to the reset input of the trigger and through the delay element with the block synchronization output and the first input of the second element I, the second input of the block connected to the reset input, and the third input to the input of the block resolution and through the element NOT to the first input of the third element I, the second input is connected the second input of the first element AND and the input resolution of the block, and the third and fourth inputs are respectively the synchronization input of the block and the input of the response signal of the block, the first and second inputs of the OR element are connected respectively to the outputs of the second and third elements AND, and the output to the input set the trigger, the output of which is the output of the block response signal. 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