SU857963A2 - Interface - Google Patents

Description

The invention relates to computing and can be used to communicate external devices (subscribers) with a computer or for communication between computers when organizing multi-machine automated control systems. St. 712821 describes an interface device comprising a subscriber matching block, a buffer register block, a clock generator, a control block, M priority blocks, M status registers, a program tuning register, a clock switch and a channel switch, the first and second outputs of the block control units are connected respectively with the first inputs of the block of buffer registers and the matching unit of the subscriber connected by the first, second, third and fourth outputs respectively to the first input of the control unit controlling and the information outputs of the device and the second input of the buffer register block, the first and second outputs of the buffer register block are respectively connected to the second inputs of the control block and the buffer register block and connected to the second inputs of the control block and the subscriber matching block, the third and fourth inputs of which are respectively the control and information inputs of the device, the third, fourth and fifth outputs of the control unit, respectively, are connected to the first inputs of the channel switch, the status registers and the clock switch, the clock switch output is connected to the third input of the buffer register unit, the second and third outputs and the fourth and fifth inputs of which are connected to the second and third inputs of the switch and the first and second outputs of the channel switch, the output of the clock generator is connected to the second inputs of the switch of the clock pulses and the status registers and the third input of the control unit, the fourth input of the control unit is connected to the output of the program setting register and the third inputs to the register state and switch of clock pulses, the fourth input i-ro (i ' r7Tl) of the state register is connected to the i-th input of the device request, and the fifth input - with the output of the i-ro device request unit, priority, inputs of the first group whose inputs are connected respectively with the first

the outputs of the lower priority status registers, and the inputs of the second group of inputs with the second outputs of the higher priority status registers, the first group of inputs and outputs of the channel switch is a group of information inputs and outputs of the device, the second group of inputs and outputs is a group of control inputs and the device outputs, and the inputs of the third group of inputs are connected to the first outputs of the corresponding status registers C j.

A disadvantage of the known device is the limited operational capabilities, which consist in the fact that this device does not provide machine-to-machine information exchange between the computers of the computing system.

The purpose of the invention is to expand the functionality of the device by providing the possibility of machine-to-machine information exchange.

The goal is achieved by the fact that M machine-to-machine exchange units are entered into the device, and the information to the i-th machine-to-machine exchange unit (i 1, m) is connected to. the fourth output of the block of buffer registers, the control, synchronization and tunable inputs, respectively, with the first, second and third inputs of the i-th state register, the first and second control outputs, respectively, with the fourth input of the fourth group of inputs of the co-switch of channels and the sixth input of the i-th state register, and the information output is the i-th information output of the machine output group of the device, the output of the program setting register is connected to the fourth input of the channel switch,

In addition, the machine-to-machine exchange unit contains two elements OR, three elements AND, a trigger, an element NOT and a group of elements AND, and the inputs of the first element OR and the first inputs of elements AND of a group are connected to the corresponding buses of the information input of the block, first, second and third inputs of the first element AND are connected respectively to the tuning and synchronization inputs of the block and the output of the first OR element, and the output is connected to the first input of the trigger and the second inputs of the AND elements of the group, whose outputs are the corresponding buses block output, the first input of the second element AND, the input element NO, the fourth input of the first element AND and the second input of the trigger are connected to the corresponding buses of the control input of the block, the inputs of the second element OR are connected respectively to the outputs of the second and third elements AND, and the input first control output unit

the first input of the third element and connected to the output of the element is NOT, and the second input is connected to the second control input of the block and the first output of the trigger, the second input connected to the second output of the second element And,

FIG. 1 is a block diagram of the device; in fig. 2 - functional diagram of machine-to-machine exchange unit.

The device contains 1 priority blocks, 2 state registers (indexes indicate the block number), 3 sync pulse generator, 4 sync pulse switch, buffer register block 5, program setting register 6, control block 7, subscriber matching block 8, switch of 9 channels, the inputs 10 of the device requests and blocks 11 machine-to-machine exchange (Fig. 1),

Machine-to-machine exchange unit 11 contains a trigger 12, the first element OR 13, elements AND 14-16, the second element OR 17, elements, group 18, NOT element 19, information 20, control 21, tuning 22 and synchronization 23 block inputs, the first 24 and second 25 control and informational 26 block outputs (Fig. 2).

Priority block 1 is a combinational circuit at the output of which a signal can be generated if there are no signals at all its inputs (OR-NOT function). State registers 2 are designed to store the current channel state and the address of the subscriber. carried out by the device. On the first input, the register 2 is reset, the second input is the synchronization input of the register, the subscriber’s address is encoded on the third input of the register, the control input is received on the fourth input enable enable signal. The priorities of the I / O channels and their corresponding registers 2 increase with the number.

Claims (2)

The switch 4 of clock pulses is a controlled counter, which, based on the code at the output of register 6 and the commands of block 7, generates a series of clock signals corresponding to a given subscriber, which are necessary for information exchange. The buffer register unit 5 is a set of shift registers with which the coordination between the subscriber and channel information word formats is carried out. Register b of the programmable configuration stores information about the individual personal characteristics of the subscriber, such as his address, information word format, etc. Block 8 is used to match the subscriber to the device at the physical level. Switch 9 is a collection of AND elements and is intended to connect interface and selected for the operation of the input-output channel to the device buses. The device works as follows. Requests from channels come to the inputs 10 of the device and contain the address of the subscriber. When requests are received from the channels at the input of each state register 2, a comparison is made between the address received at input 10 and the address set in register 6 by the setup program. Each register 2, at which these addresses coincided, goes into the order state and generates signals at its second outputs. These signals block all priority blocks 1, except for one corresponding to the highest priority among the requesting channels. If all blocking signals are missing at the inputs of block 1 of this channel, block 1 generates a signal that switches the corresponding register 2 to the Enabled state; In this state of register 2, the signal of its first output blocks all blocks 1 of channels of higher priority, and also enters the corresponding input of the group of address inputs of switch 9 (the third group of inputs) for connecting the buses of the selected channel's interface to the device buses. After this, control unit 7 begins to generate a sequence of control signals for receiving a command from a connected channel. The period of control signals, the length and format of the command, the type of transmission (in parallel, in series, bytes) is determined by the information set on register 6 and the commands issued from block 7. In accordance with this information, the switch 5 is configured so that with. its output to block 5 of the buffer registers receives synchronization signals that ensure the timing of the interface between the connected channel and the subscriber. After receiving, checking and deciphering the features of a command by the block 5 of the buffer registers and provided that the register of the intermachine exchange is set in register 6 of the program setting, i.e. The subscriber control mode is set, block 7 generates a sequence of control signals necessary for transferring information between the channel and the subscriber through the switch 9, block 5 of the buffer registers and block 8 agreeing with the subscriber in the direction indicated by the channel command. The number of layers of information transmitted is determined either by the channel or by the subscriber. When a Stop signal is received from a channel or subscriber, unit 7 completes an input-output operation, then informs the channel of the end of the operation and sets register 2 to the initial state, thereby removing the blocking from priority 1 blocks of other channels. If there is a request from the channels, the device selects the corresponding request and in a similar way ensures the execution of an I / O operation. If the machine-to-machine feature is set in the register in the software setting, the device provides for pairwise interaction of any pair of M computers that are paired with the device. The computer that first accessed the device receives master status, while the friend receives slave status. The operation of the device in the mode of the exchange of the time of receiving the control word is similar to its operation in the subscriber control mode. The machine-to-machine control word consists of M fields defining a pair of interacting computers (master and slave); the field of flags defining the direction of data transfer between the master and the slave computers (a sign of the initiative and input-output code); device addresses. Each field of a pair of interacting computers contains (M-1) bits, since each computer has the ability to exchange with (M-1) computers. The position of each of the M fields determines the address of the slave computer, and the position of the bit within each field corresponds to the address of the master computer. For each block 11 of machine-to-machine exchange from block 5 of the buffer registers, information input 20 receives signals from the corresponding field, which determines a pair of interacting computers (master and slave). The set of signals in the field defining a pair of interacting computers from the buffer register block 5, a signal. The control word sign from the control block 7 and the intermachine mode from register 6 determines the selection of the corresponding computer-to-machine exchange block 11. The informational signal supplied to the input 20 of the block 11 of the machine-to-machine exchange enters the input of the first element OR 13. In the selected block 11, the output of the first element OR 13 contains a single signal, as in the control word, in the field defining a pair of interacting computers, there is always one single bit of information that identifies the slave computer. In all other blocks 11 machine-to-machine exchange, the signal at the output of the first element OR 13 is absent. This indicates that they do not participate in this exchange session and do not have any influence on the operation of the device. With the arrival of the synchronization signal at the output of the And 14 element, a single signal appears, which polls the And 18 elements. At the output of one of these elements, a single signal appears that is fed through the output. 26 block input priority system slave computers. In addition, the signal from the output of the element And 14 sets the trigger 12 in the unit. The signal from the single (first) output of the trigger 12 through the output 25 enters the sixth input of the corresponding state register 2 and serves to unlock it. . Thus, setting the trigger to one allows the control word to be received on the appropriate channel from the slave computer via the switch 9. In the control word received from. The computer contains an indication of the direction of exchange (write, read). Which block 7 goes to control input 21 of block 11. If trigger 12 is in one state, and Record sign is received on control input of block 11, the sign goes through the element NOT 19 and as a sign Read through the element AND 16 and the element OR 17 enters output 24 of block 11. If trigger 12 is in the zero state (this indicates that this computer is the master), then the Record sign passes through the element 15 and the element OR 17 and enters the output 24 of the block 11. Therefore, the input ra e commutators 9 for driving a computer to be installed sign exchange, which is present in the control word, and for slave computers - the opposite sign. Thus, the introduction of machine-to-machine exchange units into the device makes it possible to use the proposed device both for communicating the external computer devices and for the communication between the computers forming the computing system, i.e. significantly expanded the functionality of the device. Claim 1. Interfacing device by author. St. 712821, which is different from the fact that, in order to expand the functionality of the device to ensure the possibility of machine-to-machine information exchange, device M modules were entered into machine-to-machine exchange, and the information input of the first machine-to-machine exchange unit (, M) is connected to the fourth output of the buffer register block, the control, synchronization and tuning inputs — respectively with the first, second and third inputs of the i-th state register; the first and second control outputs — with the i -th input of the fourth group, respectively in the switch and the sixth input channel i-th state register and the data output is the i-fifth group of machine data output device outputs output software configuration register coupled to the fourth input channel switch. 2. The device according to claim 1, characterized in that the machine-machine communication block contains two elements OR, three elements AND, a trigger, element NOT and a group of elements AND, the inputs of the first element OR and the first inputs of elements AND of the group are connected to the corresponding buses of the information input the block, the first, second and third inputs of the first element AND are connected respectively to the tuning and synchronization inputs of the block and the output of the first OR element, and the output is connected to the first trigger input and the second inputs of the AND elements of the group, the KOTOpbix outputs are by the input information output buses, the first input of the second element AND, the input of the element NOT, the fourth input of the first element AND and the second input of the trigger are connected to the corresponding buses of the control input of the block, the inputs of the second element OR are connected respectively to the outputs of the second and third elements AND, and the output is the first control output of the block, the first input of the third element I is connected to the output of the element NOT, and the second input to the second control input of the block and the first output of the trigger, the second input connected to the second output House second element I. Sources of information received into account in the examination 1, USSR Author's Certificate 712,821, cl. G 06 F 3/04, 1978 (prototype).