SU754403A1 - Interface - Google Patents

Description

The invention relates to the field of computing and can be ^; used for interfacing two computers (computers) with different input-output interfaces.

Known devices [1] for interfacing the main and auxiliary digital computers, comprising interrupt blocks, a command address decryption unit, an exchange mode block, a syllable counters block, a synchronization and microprogramming control unit, interfacing blocks, a control bits generation unit. The device is used to connect three auxiliary machines to the main machine.

The disadvantage of the device is the low accuracy of the exchange, since the block forming the control bits does not contain a comparison circuit kontrobnykh gaps, accompanying information machines and formed in this block.

The closest to the invention by the essence of the technical solution is the device [2] for consistency. two computers, containing a node of readiness, control circuit (node syn->

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synchronization), the output of which is connected to the inputs of the first and second information registers, and the input is connected to the first input buses via; .

5 serially connected first information register, switch and shapers-transmitters with first output buses, second input buses connected to the input of driver-receivers, the output of which is connected through the second information to the second output buses and directly to the first inputs of the address block, command register and control unit. The second and third inputs of the control unit are connected respectively to the outputs of the command register and the address block, the first output is connected to the second input of the command register, ·

The second output through the address block — with the second input of the switch, the third output through the status register — with the third input of the switch, and the fourth output — directly from the fourth input of the switch.

A disadvantage of this device is the low reliability of the device, since most of the pairing functions of computers 30 are performed by software, which results

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PG "disrupting the work of the computing system in the event of faulty situations. Particularly in the prototype, for example, a failure of information in a small computer (MbOOO) during data transfer to a large computer (EC computer) is fixed by the parity control circuits of the I / O channel. “hard stop” state. The machine can be brought out of this state only by “Quenching” and “Loading.” In the case of a large computer operating in multiprogram mode, this is equivalent to a machine crash, since the computer system crashes and the result is lost The work of programs operating in the system in parallel with the exchange of information between computers is similar. A similar situation may arise when information is transferred from a large computer to a small one.

In addition, due to false alarms, it is possible to repeatedly transmit the same information.

Failure of this nature in most cases can not be fixed programmatically.

The aim of the invention is to improve the reliability of the device.

This goal is achieved by the fact that the device containing the node signal readiness, two information registers, control inputs of which are connected to the first output of the synchronization node, the switch, three information inputs of which are connected respectively to the output of the first information register, information input connected to the input of the synchronization node and the first input of the device, to the output of the status register and the first output of the address formation node, the first input of which is connected to the information input second information register, information output connected to the first output of the device, and through the node shapers-receivers to the second input of the device, the command register connected by the information input to the first inputs of the control node and the address generation node, and the first control input and output respectively to the first output and the second input of the control unit, the second output of which is connected to the first input of the status register, the third input and output, respectively, to the second output and the input of the address generation node, and the fourth output - to the control input of the switch, the output connected through the node of the driver-transmitters with the second output of the device, two nodes for fixing the exchange state, two OR elements and element I are entered. The first inputs of the nodes for fixing the exchange state are connected respectively to the switch output and the second information output register

the second inputs are with the fifth output of the control unit, the third inputs are with the second output of the synchronization node, the first outputs are with the first and second inputs of the OR elements, respectively, and the second outputs are respectively with the input of the transmitter-transmitters node and the first output of the device. The output of the first element OR is connected to the second input of the status register and the first input of the element I, the second input of which is connected to the output of the ready signal generation unit, the first input connected to the sixth output of the control node, and the second to the fourth input of the control node and the third output of the synchronization node. The outputs of the second OR element and the AND element are connected to the first information output of the device. The fourth input of the second node of the exchange state fixation is connected to the information input of the second information register, and the fourth input of the first node of the exchange state fixation is connected to the switch output. In addition, the Exchange state fixation node contains a register, a comparison circuit connected by an output to the first register input, and an oddity decoder. Moreover, the second and third inputs and the output of the register are respectively the second and third inputs and the first output of the node. The oddness decoder input is the first input of the node, and the output is connected to the first input of the comparison circuit and the second output of the node. The second input of the comparison circuit is the fourth input of the node.

5 The drawing shows a block diagram of the device.

It contains a matching unit 1, an interface unit 2, interconnected by lines 3 and connected to the computer by inputs 4 and 5 and outputs 6 and 7.

The matching unit 1 comprises a control unit 8, an address generation unit 9, a command register 10, a switch 11, a state register 12, an exchange state fixing unit 13, an OR element 14, a transmitter-transmitter unit 15, and a transmitter-receiver unit 16.

The interface unit 2 contains the node 17 synchronization, information registers 18, 19, the node 20 of the formation of the ready signal, the node 21 fixing the exchange status, the element OR 22 and the element 23.

Nodes 13, 21 are identical and each of them contains an odd decoder 24, a comparison circuit 25 and a register 26.

The device works as follows.

In the initial state, when there is no computer turning, the matching unit 1 does not respond to the signals of the I / O interface of the large computer, and the interface unit 2 does not generate ready or interrupt signals in the line

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A computer (an illustration of the operation of the device is carried out for a computer of the EC-computer series) (main computer) and ASVT-M6000 (mini-computer).

Depending on the functions and requirements imposed on a computer system consisting of computers of various levels, when requesting a connection coming from any of the machines, control information is first transmitted.

The structure of control words of a fixed volume for each computer may be different and contain, for example, the following information: signs, operation to be performed on the data array, array length, etc. After receiving the control words, the computers are set to receive or issue the specified array of data.

The communication initiative can come from any computer, provided that they have information exchange programs running.

The device allows you to connect to a multiplex or selector channel of a mainframe and to a programming channel or to a direct access channel of a mini-computer.

The operation of the device is shown by the example of connecting it to the multiplex channel of the mainframe and to the direct access channel of the mini-computer.

At the beginning of the work of the computer system for the exchange of program information, both computers must be configured to receive control words. If the communication initiative comes from a mainframe computer, then after issuing the address of this device to the input by the multiplex channel

5 and the node 16, the node 9 of the address and the node 8 of the control, recognizing its address, generate a response address through the switch 11 and the node 15 to the output 6. In response to this channel generates a "Record" command, which is memorized

in register 10, and node 8 generates the corresponding bits of register 12 and sends a device status byte through switch 11 and node 15 to the output

6. When the device is ready to transfer information, a zero status byte is usually issued. At this, the operation of the initial sampling by the multiplex channel is completed, and the matching unit 1 releases the channel, node 8 through node 20 and AND 23 generates a device ready signal at output 7 to the mini-computer direct access channel, which programmatically generates a signal at input 4, resetting the information register 18 and arriving at node 17. The latter removes the ready signal at node 20 and, through node 8, generates an output

6 Signal "Subscriber's Requirement" (TRB-A) for data transmission to a large computer _L

moreover, the minicomputer program starts a direct access channel to receive control words of a predetermined volume from a multiplex channel.

For TRB-A, the multiplex channel provides a sequence of I / O interface signals inputted by the subscriber (matching unit 1), after completion of which the first byte of the control word is output to input 5 through node 16 to the information register 19. At the same time, node 8 generates an output readiness signal 7 through node 20 and element 23. The direct access channel receives information from information register 19 via readiness signal, removes readiness through node 17 and signals multiplex channel 'about reception of the first byte through node 8. On this multiplex channel organizes the issuance of the next byte. After receiving the last byte, the direct access channel is restarted to form the end signal (for example, the signal "Ost"), in which the node 8 resets the register 10, sets the bits "Finished Channel", "WU Finished" in register 12 and sends the final byte to the multiplex channel states. The multiplex channel generates a sequence of signals for the end of the output of information and completes the operation on the transmission of control words of the mini-computer.

If the control word specified, for example, the operation of transferring an array of information of a certain length from a mini-computer to a larger one, then the program of the latter is configured to read information, and the program of a mini-computer. launches a direct access channel to issue the specified array. In this case, the multiplex channel provides a sequence of signals of the initial sample with the "Read" command, which is stored in register 10 for the node to generate 8 corresponding signals of the input- interface. output. Upon completion of the initial sample, node 8 generates a ready signal to exit 7. Upon receiving a ready signal, the direct access channel transmits the first byte of information to the information register 18, and node 17 removes the ready signal at node 20, affects node 8, which generates the corresponding identification signals and opens the switch 11 to transfer the contents of the information register 18 through the node 15 to the output 6.

The multiplex channel, having received the first byte of the array, generates a response signal in the device by which the next readiness signal of the information register 18 is set to receive the next byte

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information. Thus the transfer of the entire array. After the transfer of the last byte, the direct access channel is restarted to form a signal for the end of the exchange of information, on which the "Channel Finished" bits are set, * * "WU Finished" bits of the state register 12.

The matching unit 1 provides a sequence of signals for the end of the data transfer, and the communication session between the computers ends.

Each byte of information transmitted from one computer to another is re-monitored by the decoder 24 nodes 13 and 21, which produce respectively. Responsible for exits 6, 7 control. discharge accompanying byte information. At the same time, this check digit is compared in comparison circuit 25 with the check digit,. which is formed in each of the computers.

If these bits do not match, the recording is made into the register 26 and at the first output of the nodes 13 or 21 a signal is generated 'Fault' ¹ , coming through the OR 14 element into the register 12, and through the OR 22 element at the output 7 as an interrupt by mistake in the direct access channel.

By interruption, the direct access channel is started to perform the operation of the end of the exchange, and in the final status byte of the matching block 1, except for the bits "Channel Finished",

"Woo finished" transmits a byte error information.

Since both computers are informed about the failure, depending on their programs, the communication session can be continued or repeated from the beginning. Fault information may be stored in a computer or issued as a message to an operator.

Nodes 13 and 21 also control the ’sequence of identification signals accompanying the information, for example, the large-computer INF-A signals and the mini-computer EP. If their sequence is violated, i.e., when the data was transmitted between two consecutive signals, the VP did not generate an INF-A signal, or between two consecutive INFA signals, the VP signal was not generated, then the output of the register 26 of the corresponding node 13 or 21 produces a signal "Failure", which acts on each computer in the above manner.

If . communication initiative · comes from a mini-computer, it is starting ^; em from the transfer of the control word, and all other operations in the exchange of information are carried out as above.

Thus, the device allows to increase the reliability of the computing system, to simplify the program of information exchange, to extend the functionality by connecting not only to the selector, but also to the multiplex channels of the mainframe computer ·

Claims (2)

Claim 1. A device for interfacing, containing a node for preparing a ready signal, two information registers, the control inputs of which are connected to the first output of the node. synchronization, the switch, three information inputs of which are connected respectively to the output of the first information register, information input connected to the input of the synchronization node and the first input of the device, to the output of the status register and the first output of the address generation node, the first input of which is connected to the information input of the second information register, information output connected to the first output of the device and through the node of the driver-receivers to the second input of the device, 'command register, connect The first information input with the first inputs of the control node and the address generation node, and the first control input and output, respectively, with the first output and the second input of the control node, the second output of which is connected to the first input of the status register, the third input and output - respectively to the second output and the input of the address formation node, and the fourth output, to the control input of the switch, the output connected via the node of the driver-transmitters to the second output of the device, characterized in that, in order to increase the device, two interchange state fixation nodes, two OR elements and an AND element are entered, the first inputs of the exchange state fixation nodes are connected respectively to the switch output and the second information register output, the second inputs to the fifth control node output, the third input to the second output synchronization, the first outputs are respectively with the first to the second inputs of the OR elements and the second outputs are respectively to the inputs of the node of the transmitter-transmitters and the first output of the device, the output of the first element OR dklyuchen to the second input register state and a first input of AND gate, a second input coupled to an output node formation ready signal, 9 754403 ten The first input of the control unit connected to the sixth output and, secondly, to the fourth input of the control unit and the third output of the synchronization node; the outputs of the second OR element and the AND element are connected to the first information output of the device, the fourth input of the second exchange state latching node is connected to the information input of the second information register, and the fourth input of the first exchange state latching node is connected to the switch output. 2. The device according to claim 1 _; wherein the exchange status latching node comprises a register, a comparison circuit connected by an output to the first register input, and oddity decoder, the second and third inputs and the register output are respectively second and the third inputs and the first output of the node, the input of the oddness decoder is the first input of the node, and the output is connected to the first input of the comparison circuit and the second output of the node, the second input of the comparison circuit is the fourth input of the node.