SU851391A1 - Channel-to-channel adapter - Google Patents

Description

one

The invention relates to computing and can be used as a system device for the communication of digital computers in a multi-machine computing complex.

The closest to the proposed technical entity is an adapter channel EC4060, consisting of a buffer register, inputs and outputs connected to two identical communication units with a channel, each of which serves a channel connected to it through an input / output interface. Each channel communication unit contains an input signal node, a command register, a command decoder, an address register, an address comparison node, a control node, an output signal node and a status byte register},

However, such a device has a low resolution diagnostics and fault location.

Its performance can be judged only by the result of transferring data bytes and state bytes through it, which, after transferring them to RAM, are available to the program and the operator. Such a check does not allow diagnostics and localization of the malfunction with the required accuracy.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the channel-channel adapter contains two semi-adapters, each of which contains a command register, a command decoder, an address register, a block compared to 10, a control unit, a computer interface unit, a buffer register , a synchronization unit, where the information input of the semi-adapter so15 is single with the input of the command register and the first input of the address comparison block, the second input of which is connected to the output of the address register, and the output of the address comparison block is connected

20 with the first input of the control unit, the second input of which is connected to the output of the decoder command, the output of which is connected to the output of the command register, the control input of the semi-adapter

25 is connected to the third input of the control unit, the first output of which is connected to the control output of the semi-adapter, and the second, third and fourth outputs of the control unit are connected so30 responsibly to the first input of the interface block with the computer, the first input of the buffer register and the input of the byte register state, the output of which is connected to the second input of the interface to the computer, the output of which is connected to the information output of the semi-adapter / the third input of the interface to the computer, is connected To the output of the address register, the fifth output of the control unit of the first adapter is connected to the third input of the control unit of the second semi-standby fifth output control unit of the second. The semi-adapter is connected to the third input of the control unit of the first semi-adapter / output of the buffer register of the first semi-adapter connected to the fourth input of the interface unit with the computer of the second semi-adapter, and the output of the buffer register of the second semi-adapter is connected to: -. By twisting the input of the interface unit with the computing machine of the first semi-adapter, a switchboard, a junction fixation unit, a diagnostic information transfer unit and an AND element, the first input of which is connected to the output of the synchronization unit, and the output to the fifth input of the control unit, are added to each semiadapter, the sixth output of which is connected to the first input of the block fixing transitions, the output of which is connected to the second inlet of the element I and to the first input of the diagnostic information transfer unit, the second and third inputs of which are under Switched respectively to the output of the command decoder and to the output of the synchronization unit, the first, second and third outputs of the transmission of diagnostic information are connected respectively to the first input of the buffer register, to the second input of the junction fixation unit and to the first input of the switch, the second, third and fourth inputs of which are connected respectively to the information input of the semi-adapter, to the first and seventh outputs of the control unit, the switch output is connected to the second input of the buffer register, the fourth input and the fourth the output of the diagnostic information transfer unit of the first semi-adapter is connected, respectively, to the fourth output and the fourth input of the diagnostic information transfer unit of the second semi-adapter.

The goal is also achieved by the fact that the fixing block of the switches contains n elements NOT, 2n triggers and the OR element, the output of which is the output of the block, and the 1st input of the OR element (1,..., 2n) connects 4eHH to the output of the 1-flip-flop , the first input of the lock is connected to the setup inputs of 2 n triggers, the second input of the block is connected to the counting inputs of the first n triggers and to the inputs of n elements

NOT, OUT j-ro element NOT (j, .. n), is connected to the counting input of (n + + j) th trigger, and also by the fact that the diagnostic information transfer unit contains the element I, counter, decoder, trigger, generator single pulses, the OR element, the first, second, third, fourth inputs of the block are connected respectively to the first input of the AND element, to the second input of the AND element and to the first input of the OR element, to the third input of the AND element, to the first trigger input and to the fourth input element And the output of which is connected to the input of the counter, the output of which is connected It is connected to the input of the decoder, the first and second outputs of which are the first and third outputs of the block, and the third output of the decoder is connected to the second input of the trigger, the forward output of which is the fourth output of the block, and the inverse output is connected to the fifth input of the And element the input of a single pulse generator, the output of which is connected to the second input of the OR element, the output of which is the second output of the block.

FIG. 1 shows a functional diagram of the proposed adapter; in fig. 2 - functional block diagram fixing transitions; in fig. 3 is a functional diagram of one of the possible variants of the diagnostic information transfer unit; in fig. 4 - control unit block diagram.

Claims (3)

The channel-channel adapter consists of two identical semi-adapters 1 and 2, each of which contains input 3, register 4 commands, decoder 5 commands, address register 6, address comparison block 7, control block 8, computer interface block 9, register 1.0 status byte, buffer 11 register synchronization block 12, switch 13 AND 14 element, transition fixation block 15, which consists of an OR 16 element and a group of channels, the number of which is equal to the number of memory elements of the control node, each channel containing a NOT element and two trigger 18 and 18p, |, where i 1-p is the channel number. Each semi-adapter also includes a diagnostic information block 19, consisting of an AND 20 element, a counter 21, a decoder 22, a trigger 23, a single pulse generator 24, an OR 25 block. The diagnostic information transfer block 19 is connected to the adapter nodes by control input buses 26-29 and output control tires 30-33. The output signals of the trigger triggers of the control unit 8 are fed to the input of the block 15 of fixation of junctions through the bus 34. The adapter is connected to the associated channels via information lines of channels 35 and 36, control lines of channels 37 and 38, information lines of subscribers 39 and 40 and control lines of subscribers 41 and. 42. The channel-channel adapter has two modes of operation: OPERATION and CONTROL. The mode of operation is specified with a pointer (bit) in the format of an exchange command. If this bit is zero, the command is executed in the OPERATION mode, if the unit is in the CONTROL mode. The control unit (Fig. 4), which is a synchronous digital autolut, generates functional signals that ensure the adapter operates in accordance with the algorithm and input signals, received from the output of the decoder 5 commands, address comparison unit 7, control unit 8 another half-adapter and control signals to the anash, coming through lines 37 and 38. The control unit 8 contains, for example, a counter 43 and a decoder 44. The transition of the control unit from one state to another occurs on the front of the sync signals generated In the OPERATION mode, the signal on the bus 29 is equal to one and the sync signals are fed to the input of the control unit 8 through the And 14 element. The signals are co. The strands with the other semi-adapter, formed by the control unit 8 on the bus 28, are received (except for the control unit of another popadapter) to the input of the diagnostic information transfer unit 19 of the other semi-adapter. However, in the OPERATION mode, block 19 does not respond to these signals and does not output any output signals. In the CONTROL mode, the adapter works as follows. The channel (for example, channel 1 when checking the second semi-adapter) selects the adapter and enters the READ command, after which the first semi-adapter issues a wait signal of approval (OG, CR) on bus 31 to control unit 8 of the second semi-adapter. On this signal, the second half-adapter is transmitted to the 2 byte channel with an ATTENTION indicator. At the same time, its control unit 8 changes state, which leads to writing units at least to one of the triggers 18 of block 15. Let the state change of these triggers occur along the positive edge of the signal at the counting input. Then the state of the first trigger changes when moving from zero to one, and the second from one to zero of the signal at the output of the corresponding memory element of the control node. Thus, at any change in the state of the control unit 8 (the state of the memory elements of the control unit) at the output of the element OR 16, a signal is generated that prohibits the passage of sync pulses through the element 14 and enables the passage of clock signals to the counting input of the counter 21 through the element, and 20 ( Signals CONTROL and OJG SOGL on tires 26 and 31 are equal to one). Counter 21 is a sequential binary two-bit counter. In the initial state of the counter 21 at the outputs of the decoder 22, signals are not generated. On the positive edge of the signal at the counting input, the counter / 21 begins to change its states. In the first and second states, a signal is generated on the bus 32, allowing the passage of diagnostic information. Through the switch 13 to the input of the buffer register. In the second state of the counter on bus 30, a write signal is generated to the buffer register 11, according to which diagnostic information is entered into the buffer register. In the third state of the counter, a signal is generated, which is set to one trigger 23. The signal from the direct output of this trigger enters the control unit of the first semi-adapter, according to which the latter reads information from the buffer register of the second (checked) semi-adapter and transmits it to the channel. The signal from the inverse output of the trigger 23 prohibits the passage of clock signals through the element 20. After the end of the transmission cycle of diagnostic information to the channel, the second semi-adapter outputs the signal GOT CM via bus 31, which resets the trigger 23. On the next clock signal, the counter 21 returns to its initial state. When a trigger transitions from one to zero, a generator of 24 single pulses generates a signal, which triggers the fixation block of junctions 15 and, on bus 29, a signal is issued that allows the passage of sync pulses to the input of the control unit of the controlled semi-adapter and prohibits the passage of clock signals to the counter input 21. The OPERATION mode on the CONTROL signal on bus 26 generates a signal at the output of the element OR 25, which keeps the triggers of the block 15 in the zero state. Verification of the first semi-adapter is done similarly. In this case, channel 2 selects the second semi-adapter, enters the t-command READ, and in the first semi-adapter, the command is entered, the correctness of which must be checked. Based on the physical or software simulation, a dictionary of malfunctions is compiled, in which the diagnostic information obtained from the semi-adapter is matched with the Fault Code. The proposed device provides localization of the fault location with an accuracy of up to 2 interchangeable units and makes it possible to shorten the time for troubleshooting by 1-3 orders of magnitude compared to the known one. Claim 1. Adapter channel-channel, containing two semi-adapters, each of which contains the command register, command decoder, address register, address comparison block, control block, interface box with computer, state byte register, buffer register, synchronization block the information input of the semi-adapter is connected to the input of the command register and the first input of the address comparison block, the second input of which is connected to the output of the address register, and the output of the address comparison block is connected to the first input of the control unit The second input of which is connected to the output of the command decoder, the output of which is connected to the register output of the control unit of the semi-adapter is connected to the third input of the control unit whose first output is connected to the control output of the semiadapter, and the third and fourth outputs of the control unit are connected to with the first input of the interface with the computer, the first input of the buffer register and with the input of the status byte register, the output of which is connected to the second input of the interface with the computing computer the bus whose output is connected to the information output of the semi-adapter, the third input of the interface unit with the computer is connected to the output of the address register, the fifth output of the control unit of the first semi-adapter is connected to the third input of the second semi-adapter control unit, the fifth output of the second semi-adapter control unit is connected the third input of the control unit of the first semi-adapter, the output of the buffer register of the first semi-adapter is connected to the fourth input of the interface unit with the computer of the second semi-adapter, and The output of the buffer register of the second semi-adapter is connected to the fourth input of the interface unit with the computer of the first semi-adapter, characterized in that, in order to increase reliability, a switch, a junction fixation unit / diagnostic information transfer unit and an element I, the first input of which is connected, are inserted into each semi-adapter to the output of the synchronization unit / and the output to the fifth input of the control unit, the sixth output of which is connected to the first input of the transition fitting unit; the output of which is connected to the second input of the AND element and with the first input of the diagnostic information transfer block, the second and third inputs of which are connected respectively to the output of the command decoder and to the output of the synchronization block, the first, second and third outputs of the diagnostic information transfer block are connected respectively to the first input of the buffer register, to the second input of the transition fixation block and to the first input of the switch, the second, third and fourth inputs of which are connected respectively to the information input of the semi-adapter, to the first and seventh outputs of the control unit No, the output of the conductor is connected to the second input of the buffer register, the fourth input and the fourth output of the diagnostic information transfer unit of the first semi-adapter are connected to the fourth output and the fourth input of the diagnostic information transfer unit of the second semi-adapter, respectively. 2. The device according to claim 1, characterized in that the block of fixation of transitions contains n elements NOT, 2n triggers and the element OR, the output of which is the output of the block, and the i-th input of the element OR (i 1, ... n) is connected to the output of the i-th trigger, the first input of the block is connected to the setup inputs 2n of the flip-flops, the second input of the block is connected to the counting inputs of the first n flip-flops and to the inputs n of the NO elements, the output of the j-ro element (j J ,, .., n) connected to the counting input (n + j) -ro trigger. 3. The device according to claim 1, characterized in that the diagnostic information transfer unit contains an element AND, a counter, a decoder, a trigger, a single pulse generator, an OR element, the first, second, third, fourth inputs of the block being connected respectively to the first input of the element And, with the second input of the AND element and with the first input of the OR element, with the third input of the AND element, with the first input of the trigger and the fourth input of the AND element whose output is connected to the decoder input, the first and second outputs of which are the first and third exit block E / and the third output soedi- decoder. it with the second trigger input, the direct output of which is the fourth output of the unit / and the inverse output connected to the fifth input of the element And and to the input of the generator single pulse 6V | the output of which is connected to the second input of the OR element, the output of which is the second output of the block. Sources of information taken into account in the examination 1. Antonov, V.S. / Soloviev, S.P., et al. Electronic computer EC-1050, - Statistics, 1976, p. 185-190. - g 371 bye M ffut.l g / (IT / 1 G-: n: 34 I - - I J 1 five Psanal n P 57 (pUl. if CmpoSK j