SU1141418A1 - Interface for linking two computers - Google Patents

Abstract

A DEVICE FOR PAIRING TWO ELECTRONIC COMPUTING MACHINES containing the first and second buffer registers, the exchange control unit, the word state register, the switching unit, the information input of the first buffer register connected to the first information input of the device, the information output of the second buffer register connected to the first information output of the device and the word state register information entry, the output of the switching unit is the second information output of the device, the first output and. The exchange control block, respectively, is the output of the interrupt and the control input of the device, and the second, third and fourth outputs are respectively connected to the control inputs of the second and first buffer registers and the word state register, characterized in that, in order to expand the class of tasks and increase the bandwidth of the device; a communication unit with an input / output channel, an address setting unit, an address comparison unit, a data and command register, a data and status register, an order register and a block are entered into it. control, the second, third and fourth inputs of the exchange control block are connected respectively to the control outputs of the Second and First buffer registers and the word state register, and n - th inputs and outputs respectively to the first output and input of the communication block the output, the second input and output of which are, respectively, the input and output of the device synchronization, the third input and (L output are connected respectively to the control output of the second buffer register and the control input of the data and status register informational; the input and output of which are connected respectively with the information output of the first buffer register and with the information input of the switching unit, the second information and control inputs of which are connected4; here, respectively, with the first output of the address setting unit and the fourth output of the communication unit with the input and output channel, the fourth input of which EEO is single with the control output of the first buffer register, the fifth and sixth inputs, respectively, with the outputs of the address comparison unit and the control unit, input connected to the output of the register of data and commands, the information input of the second buffer register and the seventh input of the communication unit with the I / O channel, the eighth input of which is connected to the output

Description

the order register, the information and control inputs of which are connected respectively to the first information input of the device and the sixth output of the exchange control block, the second output of the address setting block to the first information input of the address comparison block, the second information input of which is the second information input of the device and connected with the information input of the register of data and commands, the control input of which and the information input of the register of the word state are connected respectively to the fifth and sixth the outputs of the communication unit with the I / O channel, the communication unit with the I / O channel contains a multiplexer, a branch trigger, a microprogram memory, a micro-command address register, a subscriber signal register, a control signal register, four AND elements and three OR- NOT, the output and the first input of the micro-command address register are connected respectively to the input and the first output of the microprogram memory, the second and third information inputs are. Respectively with the seventh block input and the multiplexer output, and the synchronization and reset inputs a - with the first input of the byok, a group of information inputs of the multiplexer is connected to the second and sixth inputs of the block, the outputs of the first element AND and the first, second and third elements OR NOT and the output of the branch trigger, and the control input - to the second output of the microprogram memory , the third and fifth outputs of which are connected

respectively, with the information inputs of the subscriber signal register, the control signal register and the branch trigger, the synchronization inputs and reset of which are connected to the first B; block stroke, the first inputs to the second,

The third and fourth elements And are connected respectively to the sixth, seventh and eighth outputs of the microprogram memory, the second inputs to the first input of the block, and the outputs constitute the sixth output of the block, the output of the signal register of the subscriber is: the second output of the block, the bit outputs of the register of signals The controls are the first, third, fourth, and fifth outputs of the unit, the first and second inputs of the first 41418

element And are connected respectively with the second and fifth inputs; block, the first and second inputs of the first element OR NOT and the first inputs of the second and third elements OR NOT. form the eighth input of the block, the second inputs of the second and third elements OR NOT are the fourth and third inputs of the block, respectively, and the exchange control block contains four OR-NOT elements, seven AND-NOT elements, a decoder, a pulse shaper, a trigger, two NOT elements and three AND elements, the output of the first element OR NOT is connected to the trigger reset input, the information input of which is connected to the logical zero bus, and the sync input and the installation input are connected to the outputs of the first and second elements AND NONE, the output of the second element ENTA OR NOT connect. The first inputs of the second and third elements of the NAND and the first element of AND are connected to the direct output of the pulse shaper, the inverse output of which is connected to the first input of the second and third elements AND, the first time of the fourth and the fifth elements of the NAND are connected respectively to the direct and inverse outputs of the trigger, the second inputs are connected to the second input of the block, and the outputs are respectively to the first inputs of the sixth and seventh elements of the NAND, whose outputs form the first output of the block, and second entrances us respectively to a fourth input of the first element and through the NOT input to a third block of the third element output

I ...

AND-NOT connected to the input of the second element NOT, the output of which and the output of the first element AND-NOT form the second output of the block, the first output of the decoder is connected to the first inputs of the second and third elements OR-NOT, the second output to the first input of the fourth element OR- NOT, the output of which is the sixth output of the block, the third output of the decoder is connected to the second input of the first element AND, the outputs of the first and second elements form the fourth output of the block, the outputs of the third element OR NOT and the element AND form the third output of the first outputs or-NOT and the pulse former form the fifth. the output of the block, the first input of the first element OR NOT, the second inputs of the second, third and fourth elements OR NOT, the input of the pulse shaper and the group, the inputs of the decoder are connected to the first

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the input of the block, the second inputs of the first element OR — NOT, the second and third elements AND — NOT, the second and third elements I AND form the fifth input of the block.

The invention relates to computing technology and can be used in multi-machine computing complexes, regional and local computer networks, and automation systems. production and research for the connection between computers of various types and functional purpose. Computer interface devices are known that contain a decoder, a switch, a control signal generating unit, amplification blocks, an exchange unit, a matcher, an interrupt execution unit, a control register. The device has a limited scope, as it provides communications of different types of computers, but related to the class of mini-computers that have simplified input-output interfaces and do not allow the creation of high-performance computing systems. In addition, the device has a number of functional limitations, such as the inability to read the control register from the main computer, which deprives it of information about the situations arising in the device, the need for the main computer to be constantly ready to receive data from the auxiliary computer due to the lack interrupt handling capabilities, computer inequality in determining the end of a data transfer operation. The closest to the invention to the technical essence is a device for interfacing a computer containing the first and second buffer registers, the exchange control block, the first and second issuing blocks, word registers, the time counting block, the first, second, third, fourth, The sixth and sixth outputs of the exchange control block are connected: respectively to the first output of the device, to the control input of the first buffer register, to the control input of the second buffer register, to the second output of the device, to the control input of the first The first block of information is connected to the first input of the device and the information input of the first buffer register, the second input of the device is connected to the information input of the second buffer register and the second information input of the register of the second word register connected to the information input of the first output unit; the output of the first buffer register and the output of the first block; connected to the third output of the device; the output of the second buffer register connected to the fourth output of the device, the third, fourth, and fifth inputs of the device are connected respectively to the first, second, and third inputs of the exchange control block, the information input of the second power block is connected to the output of the word register register, and the control input of the second power block is connected to the seventh output the exchange control unit, the output of the second output unit is connected to the fourth output of the device, the eighth output of the exchange control unit is connected to the input of the time counting unit, the output of which is connected to the fourth input the home of the exchange control block Y. The disadvantage of the known device is the limited class of tasks and the low bandwidth of the device due to its limited functionality, which means that when the computer mates with complex I / O interfaces, exchange. The purpose of the invention is to expand the class of tasks and increase the bandwidth of the device / The goal is achieved by the fact that the device containing the first and second buffer registers, the exchange control block, the word state register, the switching block, the information input of the first buffer register is connected to the first informational input of the device, the information output of the second buffer register is connected to the first information output of the device and the information output of the word register register, the output of the and the switching is the second information output of the device, the first output and the input of the exchange control unit are the output of the interrupt and the control input of the device, respectively, and the second, third and fourth. The outputs are respectively connected to the control inputs of the second and first buffer registers and word registers when a communication unit with an input / output channel, an address setting unit, an address comparison unit, a data and command register, a data register, and a status state are entered. order register and control unit, the second, third and fourth parts of the exchange control block are connected to the control outputs of the second and first buffer registers and the status word, respectively, and the fifth input and output, respectively, to the first output and the input of the communication unit with the input-output channel, the second input and output of which are, respectively, the input and output of the device synchronization, the third input and output are connected respectively to the control output of the second buffer register and the control input of the register data and states, the information input and output of which are connected respectively to the information output of the first buffer register and the first information input of the switching unit, the second information and control inputs of which are connected respectively to the first output of the address setting block and the fourth output of the communication unit with the input / output channel, the fourth input of which is connected to the control output of the first buffer register, the fifth and sixth inputs, respectively, with the outputs of the address comparison unit and the control unit, I / O. the house of the data and command register connected to the output, the information input of the second buffer register and the seventh input of the communication unit with an input and output channel, the eighth input of which is connected to the output of the order register, the information and control inputs of which are connected respectively to the first information input of the device and the sixth the output of the exchange control unit, the second output of the address setting unit is connected to the first information input of the address comparison unit, the second information input of which is the second information input the input of the device and connected to the information input of the data and command register, the control input of which and the information input of the word condition register are connected respectively to the fifth and sixth outputs of the communication unit with the input / output channel, the communication unit with the input-output channel contains a multiplexer , branch trigger, microprogram memory, micro address register; commands, subscriber signal register, control signal register, four AND elements and three IHR-NOT elements, the output and the first information input of the micro-command address register are connected respectively to the input and the first output of the microprogram memory, the second and third information inputs are respectively with the seventh input of the block and the output of the multiplexer, and the synchronization and reset inputs with the first input of the block, the group of information inputs of the multiplexer is connected to the second and sixth inputs of the block, the outputs of the first element And the first, second of the third and third elements of the IPI-NOT and the output of the trigger of the branch: events, and the control input to the second output of the microprogram memory, the third to the fifth outputs of which are connected respectively to the information inputs of the subscriber signal register, the control signal register and the branch trigger The sync11 and sync inputs are connected to the first input of the block, the first inputs of the second, third and fourth elements of And are connected respectively to the sixth, seventh and eighth outputs of the microprogram memory, the second inputs to the first input of the block ka and the outputs form the sixth block of the block, the output of the subscriber signal register is the second block output, the bit outputs of the control signal register are the first third, fourth and fifth block outputs, the first and second inputs of the first And element are connected to the second and If the inputs of the block, the first and second inputs of the first element OR NOT and the first, the inputs of the second and third elements OR NOT form the eighth input of the block, the second inputs of the second and third elements OR NOT are respectively the fourth and third the block inputs, the exchange control block contains four OR-NOT elements, seven N-elements, decrypts, a pulse shaper, a trigger, two NO elements and three AND elements, and the output of the first OR element is not connected to the trigger reset input whose information input is connected to the logical zero bus, and the synchronous input and installation input is connected to the outputs of the first and second AND-NOT elements, the output of the second OR-NOT element is connected to the first input of the first AND-NOT element, the first inputs of the second and third AND elements NOT the first element And are connected to the direct output of the pulse former, the inverse output of which is connected to the first inputs of the second and third elements AND, the first inputs of the fourth and fifth elements AND-NOT are connected respectively to the direct and inverse outputs of the trigger, the second inputs - to the second the input of the block and the outputs, respectively, with the first inputs of the sixth and seventh elements AND-NOT, the outputs of which form the first output of the block, and the second inputs are connected respectively to the fourth input of the block and through the first element NOT to the third input of the block, the third output element AND-NOT connected to the input of the second element NOT, the output of which and the output of the first element AND-NOT form the second output of the block; the first output of the de-encoder is connected to the first inputs of the second and third elements OR-NOT, the second output to the first input of the fourth element OR -NON, the output of which is the sixth output of the block, the third output of the decoder is connected to the second input of the first element AND, the outputs of the first and second elements AND form the fourth output of the block, the outputs of the third element OR NOT and the element AND form the third output of the block the OR element and the pulse generator form the fifth output of the block, the first input of the first element OR NOT, the second inputs of the second, third and fourth elements OR NOT, the input of the pulse shaper and the group of inputs of the decoder are connected to the first input of the block, the second inputs of the first the element OR NOT, the second and third elements AND-NOT, the second and third elements AND. form the fifth input of the block. FIG. 1 shows a block diagram of the device; in fig. 2 is a functional block diagram of the exchange control unit; in fig. 3 is a functional diagram of a communication unit with an I / O channel; in fig. 4 is a flow chart of the operation of the communication unit with an I / O channel. The device (Fig. 1) contains the first buffer register 1, the second buffer register 2, the exchange control unit 3, the word register 4, the order register 5, the switching unit 6, the data and status register 7, the communication block 8 with the input channel outputting the data and command register 9, the address comparison block 10, the address setting block 11, the control block 12. Figure 1 also shows the auxiliary computer 13, the main computer 14, the bus 15 of the first information input of the device, the bus 16 of the first information output of the device, the bus 17 of the control input of the device, the bus 18 of the interrupt output of the device, the bus 19 of the second information output of the device, bus 20 of the synchronization output device, bus 21 input device synchronization, bus 22 of the second information input device. The exchange control unit 3 (FIG. 2) contains the elements OR-NO 23 and 24, the element AND-NOT 25, the decoder 26, the pulse former 27 (one-shot), the trigger 28, the elements AND-NOT 29 and 30, the element 31, the elements AND-NOT 32-35, 7 element NOT 36, elements OR-NOT 37 and 38, elements AND 39-41, tires 42-45 of the second, fourth and third: its inputs of the block, bus 46-50 of the second, the third, sixth and fourth exits of the block. The communication unit 8 with an input-output channel (FIG. 3) contains an AND 51 element, an OR-NOT 52-54 element, a multiplexer 55, a microinstruction address register 56, a branch trigger 57, a microprogram memory 58, a subscriber signal register 59 , a register 60 of control signals, elements 61-163, tires 64-69 of the seventh, fifth, eighth, fourth, third and sixth inputs of the block, bus 70-73 of the fourth, third, fifth and sixth outputs of the block. The tires in FIG. 1-3 are intended for the passage of signals having the following meaning. The buses transmit control signals from the auxiliary computer 13 arriving at the first input of the exchange control unit 3, including; line 17, - signal Reset MM, produced by the auxiliary computer 13 and necessary for resetting the device registers from the side of the auxiliary computer 13; lines {17j. - the address bus of the auxiliary computer 1 line - the signal of the strobe of the address of the auxiliary computer 13 informing the device that the address of the external device is on the address bus 172-17d; line 17 (- signal Issuance of an auxiliary computer 13, indicating that the tires 15 from the auxiliary computer 13 contain information bytes; the synchronization signal lines Bus 18j and IBj transmit interrupt signals coming from the first output of unit 3 to the auxiliary computer 13, and a message stating that a command or data byte is located in the device, including: line 18, signal on command, line 18 — data interruption signal. Tires 20 | -20g transmit subscriber control and identification signals to main computer channel 14 including: line 20 - with Ignal RAB-A subscriber operation; line 20 ADR-A signal — address from the subscriber; line 20z — VBR-A signal — sample 18/8 from the subscriber; line 20 — INFA signal — information from the subscriber; line 20 — UPR signal -A - control from the subscriber; line 20g - signal TRB-A - subscriber's requirement. Tires 21 (-21ts broadcast control and identification signals from the main computer channel 14, including: line 21 - - VBR-K signal sampled from main computer channel 14; line 21 - signal UPR-K - control from the main computer channel 14; line 21J - signal INF-K - information from the channel of the main computer 14; line 21 - signal ADR-K - the address from the main computer channel 14. Tires. transmit control signals from the first output of block 8 to the fifth input of block 3, including: line 42 - signal Reset generated by block 8 and reset all device registers; line 42 ,, is the command signal generated by block 8 and necessary for generating an interrupt to the auxiliary computer 13 at the appropriate level when receiving a command from the main computer 14; - line 42., - receive strobe signal, used to generate a recording signal in buffer register 2; line 424 is the signal of the word state strobe used to generate a recording signal in register 4.; line 425 is a write confirmation signal used to generate a read signal for buffer register 1. Busbars 43 and 68 transmit a signal of the fill indicator, buffer register 2, coming from the control output of the buffer register 2 to the second input of block 3 and to the third input of block 8 and indicating that a byte or data is written to register 2. The bus 44 transmits the sign of the sign of the filling of the register 4 of the word state, coming from the control output of the register 4 to the fourth input of block 3 and informing about the writing to the register 4 of the state word byte with the following indicators (End of exchange, Error on the buses, Failure ). Tires 45 and 67 broadcast a buffer register full signal. a 1 arriving at the fourth entry

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block 8 and the third input of block 3 and informing about writing to the register 1 data byte or status from the auxiliary computer 13..

The buses are used to transmit control signals from the fifth output of block 3 to the first input of block 8, including: line 46 transmits a master reset, resetting all device registers to their initial state (except for the word state register 4, which is reset by reading ); line 46, the synchronization signal supplied to the registers of block 8; line 463 - the synchronization signal of the register 56 block 8.

Tires 47, and 47 transmit signals controlling the operation of the buffer register, 2, including: line 47, the entry signal to buffer register 2, coming from the second output of block 3 to the control input of buffer register 2; line 472 is the read signal of the buffer register 2, coming from the second output of block 3 to the control input of buffer register 2, while the signal at the control output of register 2 is reset (i.e., the fill indicator is reset).

Tires 484 and 48j transmit signals that control the operation of buffer register 1, including: line 48, —a signal to buffer register 1, coming from the third output of block 3 on, controlling the input of buffer register 1; line 48 is the read signal of buffer register 1, coming from the third output of block 3 to the control input of buffer register 1.

Bus 49 transmits a recording signal to the register of 5 orders, coming from the sixth output of block 3 to the control input of the register 5 of orders. ...

Tires 50 and 50j transmit signals controlling the operation of register 4 word states, including: line 50 — a signal of recording to the register of 4 word states, coming from the fourth output of block 3 to the control input of the register 4 word states; line 50 ,, is the read signal of register 4 of the word state, coming from the fourth output of block 3 to the control input (read) of the register of the 4 word state, while the signal

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at the control output (sign of filling) is reset.

Bus 64 transmits a command code signal recorded in register 9 of data and commands and coming from the output of register 9 of data and commands to the seventh input of block B.

Bus 65 transmits a device address recognition signal generated by address comparison unit 10 and fed to the fifth input of block 8.

Tires broadcast flag signals from the register 5 output of orders to the eighth input of block 8 and setting the device operation modes, including: line (tdj is the BSIN flag (initiative state byte), indicating that the status byte is loaded into the main computer 14 ; line 66 Start recording flag; specifies the mode of recording information from the auxiliary computer 13 into the buffer register 1 followed by it into the main computer channel 14; line 66 is the Start start flag specifying the mode of reading information from the device to the auxiliary computer 13.

Bus 69 transmits an Error signal on the Inna, arriving at the sixth input of block 8 from the output of block 12 of the control, and reporting an error in the information byte.

(Tires 70 and 70 Transmit control signals from switching unit 6, coming from the fourth output of block 8 to the control input of block 6, including: line 70 — a signal that allows 19 bytes of data or status to be sent to buses (data enable); line 70 is a signal that permits device addresses to be transferred to buses 19 (Address Resolution).

Bus lines 714 and 712 transmit data control and data condition register 7 signals to the control input of register 7 from the third output of block 8, including: line 71, information entry signal to data and status register 7; line 71 jsignal of installation of modifiers KK, UK (Channel finished, Device finished) in the status byte.

Bus 72 transmits a signal to register 9 data and commands from the fifth output of block 8 to the control input of register 9.

Tires 73 | -73z transmit informational signals informing auxiliary II computer 13 about the features of the last exchange, as well as about the end of the exchange from the host computer 14 and coming from the sixth output of block 8 to the information input of the register of 4 status words, including: line pointer End of exchange; line 73 pointer Data error .; line 73j - pointer Failure in the device The device works, as follows. Information is exchanged between the I / O channel of the mainframe 14 and the common bus of the auxiliary computer 13. Any computer can be the initiator of the exchange. The exchange procedure can be divided into four stages: the first stage is the receipt of a command code from the main computer channel 14 and its analysis by the device; the second is the transfer of the command code to the auxiliary ZIM 13 and the initiation on its part of the corresponding operation; the third is the transfer of data; the fourth is the transfer of a state byte to the main computer 14. When initiating the exchange from the side of the auxiliary computer 13, the latter initiates an initiative state byte, which is transmitted to the channel of the main computer 14 and then follows the same steps as in the previous case. commands are commands of the three types of exchange command - Read, Write. Clarify status, control commands — Work control, Sham control, and device check commands. Moreover, the control and verification commands require only two stages of the exchange: the first and the fourth. Consider the operation of the device initiated by the main computer 1 When accessing the device, the main computer 14, entering the initial sampling sequence (HB), on buses 21 exposes a VBR-1 signal To (line 21, and on tires 22, sets the device address, accompanied by the identifier ADR-K (line 214), coming in. Like the signal VBR-K (line 21),, on buses 21 the main computer 14 to the second input of block 8 (the algorithm of operation of block 8 in Fig. 4). The address of the device arrives on the first The information input of the address comparison unit 10, the second information input of which receives the device’s own address specified by the address setting block 11 1812. In case of incoming addresses, unit 10 generates a signal Address recognized (ADAP), arriving via bus 65 to the input of block 8. Last , having determined the identification of the address, exposes a RAB-A signal (Subscriber operation), informing the main computer 14 about connecting the device to the I / O channel. The RAB-A signal (line 20,) comes from the second output of block 8 to bus 20 and is reset only when the device is disconnected from the interface. Then block 8 sets the address resolution signal (Allow A, line 702 coming from the fourth output of block 8 to the control input of block 6 and allowing the device address from the output of block 11 to the main computer channel 14. The device address is accompanied by the ADR-A identifier (line 20), arriving from the second output of block 8 to buses 20. The main computer channel 14, having received the address, sets the command code on buses 22, accompanied by the UPR-K identifier (line 21), coming through line 21 to the input of block 8. Next, block 8 signals the registration signal Tr of data and commands (ZNS RDK, line 72), arriving at the control input of register 9 and entering the command code from the bus 22. From the output of register 9, the command code goes to the input of block 12, to the seventh input of block 8 and to the information the input of the second buffer register 2. In block 8, the command code is analyzed and then a series of operations are performed. For example, consider the Write command (BOD). Block 8, having defined the code of the BOD command, sets the signal (COM) (line 42) and Receive Gate (Strobe PM) (line 42j-) j arriving at the fifth input of block 3, Next, the operation of block B and block 5 p takes place in parallel: block 8 completes the HB procedure, block 3 generates a stop signal to the auxiliary computer 13. Consider first the end of the initial sample. Block 8 sets the data resolution signal (Allow D, line 70), which is connected to the control input of block 6 and enables the state byte from register 7 to the main computer 14. In addition to 13, in addition, block 8 sets the UPR signal on buses 20 A (line 265), together with the fact that the bus 19 has a device status byte. Then, receiving in response from the mainframe 14 via buses, 21 signals INF-K (line 21z), block 8 suppresses the signals of UPR-A (line 20) and RAB-A (line 20) on tires 20 and disconnects from the channel of the main computer 14. This procedure does NOT end there. Now consider the operation of block 3, which is carried out in parallel with the operation of block 8. The Strobe PM signal (line 42j) in block 3 is used to generate a recording signal in the buffer register 2, which is fed from the second output of block 3 to the control input of the buffer register 2. After entering the command code into the buffer register 2, from its control output, the second input of block 3 receives a signal, which in block 3 produces a trap signal, which then enters the auxiliary computer 13 via bus 18. The device uses two levels of interrupt ogatelnuyu computer 13 to command and data. The command interrupt (line 18,) informs the auxiliary computer 13 that the buffer code 2 contains the command code. Interruption by data means (depending on the code of the command received) that either the buffer register 2 contains the data byte for transmission to the auxiliary computer 13 (with the Write command) or the buffer register 1 is empty and requires the next byte from the auxiliary computer 13 (in the case of the commands Read Ref. The signals of the corresponding interrupt levels are generated by block 3 using the signals from the control outputs of the buffer registers 1 and 2. Since data and commands can be transmitted through the buffer register 2, this command is used to generate an appropriate interrupt level. If a command signal is received from block 8, a command interrupt signal is generated (line 18). The auxiliary computer 13 processes the received new interrupt 5, then reads the command code from buffer register 2 and analyzes it. To read the buffer 1814 register 2, an auxiliary computer 13 sets on bus 17 the address of buffer register 2, arriving at the first input, of unit 3j which generates a read signal. The read signal comes from the second output of block 3 to the input of buffer register 2. Auxiliary computer 13, after analyzing the code of the command received, writes one of the flags into register 5 of orders (Start of reading at command 3 write, Start of recording at command Read, initiating state or BSIN when initiated from the side of the auxiliary computer 13. The flag refers to a pointer specifying the mode of operation of the device and providing a branching of the operation algorithm (Fig. 4) of block 8. In the case considered, the auxiliary computer 13 sets the flag on the tires 15 Start reading (Start THU), and the address of register 5 on tires 17 and the signal Vshchach. On these signals, block 13 generates a signal entry, received on bus 49 to the input of register 5 and bringing flag into it from bus 15. With register output 5 flag The start of the THB goes to the eighth input of block 8, informing him that the auxiliary computer 13 is ready to receive the information byte, and sets the information output mode from the device to the auxiliary computer 13. Next, block 8 exposes the TRB-A signal on buses 20 (line ZOg) required from the mainframe 14 the next byte of information. In response, the host computer 14 exposes a VBR-K signal (line 21) without a device address to the buses 21, thereby sampling the device requiring service, f Block 8, determining the presence of the VBR-K signal, checks whether the device requires maintenance ( by the presence of one of the flags Start ThU, Start BF, BSIN), and if maintenance is not required (none of the flags), then the VBR-A signal (line 20) is set on the tires 20. If maintenance is required (in the case considered, the Start ThU flag is set), i.e. The TRB-A signal was set by the device, then the block 8 suppresses the TRB-A signal on the tires 20. Then the block 8 to the bus 20 outputs the RAB-A signal (line 20; j), to the control input of the block 6 - the address resolution signal .A, line 70j), and on tires 20, an ADPA-A identifier (line 20), indicating that the bus 19 contains the device address. The main computer channel 14, having received the address of the device, exposes the UPR-K signal on the buses 21 (line -21 .;); thus allowing the device to continue the operation. After this, block 8 removes the ADR-A signal (line 20 and suppresses the address resolution signal (Allow A)), blocking the device’s address output to the main computer channel 14. Next, block 8 sets the INF-A signal (line 20x) at the second output, arriving on reception buses 20 on the main computer channel 14 and informing it that the device wants to receive data bytes. In response, the bases on computer 14 expose data bytes on buses 22, and on buses 21, the INF-K identifier (line 21) informs block B, that the data byte is on buses 22, with the second output of block 8 to the control register code 9 a signal enters the data byte in register 9. Block 8 generates a receive gate signal (PM gate, line 42), which accesses the fifth input of block 3. Next, as in the HB procedure, parallel blocks work 3 and 8 Block 3 sends a signal to the control input of the buffer register 2 that sends the data byte from the output of register 9 to buffer register 2 (line 47). As a result, the control output of buffer register 2 produces a signal (lines 43 and 68), arriving at the second input of block 3 to generate an interrupt according to the data during the auxiliary solder computer 13, Data interrupt signal (line 18) indicates that buffer register 2 contains data bytes for transmission to auxiliary computer 13. Reading a data byte from the buffer register is the same as reading a command byte in the preceding procedure HB, Block 8. In parallel with the operation of Block 3, the algorithm works with the main computer channel during data transmission, i.e., Block B removes INF-A signals (line 20) from the bus 20 (with the device being received byte) and RAB-A (line 20,) (together with disconnecting the device from the interface) After reading the auxiliary computer 13 byte of information on the control output of the buffer register 2, the sign of the filling indication disappears, and block 8 will record that the information byte is read by the auxiliary computer 13 and the device is ready to receive the next byte. Then block 8 again exposes the TRB-A signal (line 20), and the entire transmission cycle is repeated again. The exchange can be completed either on the initiative of the main computer 14 or on the initiative of the auxiliary computer 13. In the first case, the main computer 14 completing the transmission, when exchanging control signals on buses 20 and 21, in response to an INF-A signal (line 20x) (i.e. a request by the subscriber of the next byte), it responds with an UPR-K signal (line 21j) (when transmitting data, the response signal INF-K), which for the device means the completion of the exchange operation. Then block 8 removes the signals INF-A (line 20) and RAB-A (line 20j) from tires 20, sets the End of exchange indicator (KO, line 73; |) arriving at the information input of register 4, and the word strobe register signal (line 42), arriving at the fifth input of block 3. In block 3, the signal from the word state register strobe signals the entry into register 4 (line 50). After recording in the data register 4, the signal of the filling sign (bus 44) arrives at the control output on the fourth input of the unit 3, where it is used. is generated to generate an interrupt upon command. If the fill flag signal from buffer register 2 can cause an interrupt both on command and on a given, then the register 4 sign on the interrupt generates an interrupt only on command. The auxiliary VM 13, having received an interrupt on a coman (line 18 |), determines that it is an interrupt from register 4, since an interrupt on a command from buffer master 2 cannot come in the device occupation with the current operation. The auxiliary computer 13, after processing the interrupt, reads register 4 (similar to reading buffer register 2). The read signal of register 4 (line SOj) comes from the fourth output of block 3, and as a result, the signal at the control output of register 4 disappears, thereby indicating that the information has been read.

The auxiliary computer 13, having determined the CO pointer in the byte read from register 4, suppresses the Start flag in register 4 (blanking is performed by writing 5 zero flags to the register). Then it forms the final byte of the device state and puts it into the buffer register 1. For this, the status byte is set on the buses 15, and on the buses 17, the address of the buffer register 1 and the output signal arriving at the first input of the unit 3 are set. The signal in block 3 generates a signal in buffer register 1 (line 48,), then arrives at the control input of buffer register 1. After the status byte is written in buffer register 1, a signal of a sign of filling appears in its control output (line 45 and 67), n Block 8 and B, 3, and block B. Determining the presence of the BSIN flag at the eighth input and the sign of filling in buffer register 1 at the fourth input, sets the TRE-A signal (line 20) on buses 20.

In response, the mainframe computer 14 begins the sequence of sampling the device requiring service, i.e. sets the signal VVR-K (line 21f) the device responds with the signal RAB-A (line 21). Thereafter, block 8 sets a recording signal to register 7 (line 71), rewriting the byte state from buffer register 1, and a record confirmation signal (Confirm CAP) (line 425). In the block:. The Confirmation signal of the RFP generates a readout signal of the buffer register 1. As a result, the control sign of the buffer register disappears at the control output of the buffer register 1. This will be fixed by block 3, after which it generates an interrupt signal from the data into the auxiliary computer 13. For the latter, it will be a message that the status byte is received by the interface device and buffer register 1 is free.

g

Next, the auxiliary computer 13 resets the register 5 (extinguishes the BSIN flag)

and writes into the buffer register 1 fictitious bytes. The latter is necessary so that the signal of the indication of the filling of the buffer register 1 does not abate in block 3 of the interrupt signal by data, i.e. This is the prohibition of interruption from the buffer register 1. Block 8 after signaling. Confirmation of the signaling signal Allows data resolution (Allow E, line 70) arriving at the control input of block 6 and allowing the end state byte of the device to buses 19 and UPR-A signal (line 205). The main computer channel 14, having received the UPR-A signal, responds with an INF-K signal (line 21j) on buses 21, thereby indicating that the final status byte is received. After block 8, it suppresses the UPR-A and RAB-A signals and considered complete. In the case of the completion of the operation initiated by the auxiliary computer 13, the latter suppresses the Start THU in register 5, writes 1 state byte into the buffer register, and the BSIN flag into register 5. Further operation of the device is the same as in the case of termination of the operation on the initiative of the main computer 14. The exchange control unit 3 (Fig. 2) operates as follows.

The input element OR-NOT 23 on lines 17 and 42, respectively, receive signals Reset MM from auxiliary computer 13 and the signal Reset from block 8. Thus, a signal is generated General reset, i.e. when a logical unit signal appears at any of the inputs of the OR-NOT 23 signal, a logical zero signal is generated at its output, by an extra 46 in the block 8 input reset trigger 28. This signal also resets all device registers. When writing a byte to the buffer register 2 (as noted when considering the operation of the device as a whole), block 8 generates a receive gate signal on line 42, which arrives at the input of the AND-30 element, to the other input of which clock pulses are received from the one-oscillator 27, operating from of the master frequency supplied by the line from the auxiliary computer 13. As a result, a negative pulse is generated at the output of the element NE-30, which is then inverted by the element HE 36, and the positive pulse of the recording in the buffer register 2 is fed to the control 47 via line 47 the auxiliary input of the buffer register 2,

After the byte of information has been entered into the buffer register 2, the control output of the latter appears on the signal of the fill indication via the bus 43 to the inputs of the AND-NE elements 32 and 33. If a byte, written to the buffer register 2, is also command, the block 8 sets the signal. A command arriving on line 42 to the input element AND-NOT 29. When a sync pulse from the one-oscillator 27 arrives at the other input of the AND-NOT 29 element, a negative pulse is generated at its output, which sets it to 1 forward state trigger output 28 As a result, opens the IS-NE element 32 (at both inputs is a logical unit signal), and the logical zero signal is fed to one of the inputs of the IS-NE element 34, causing at its output an interrupt signal on the command received on line 18 to the auxiliary computer 13. On the other the input of element 34 receives a signal of the sign of filling from the word condition register 4, causing a similar fault, if information was recorded in register 4. If the trigger 28 is cleared, then a logical zero from the output of the AND-HE element 33 will cause an interrupt signal at the output of the AND-HE element 35, which will go to the auxiliary computer 13 via line 182.

Thus, the trigger 28 switches the sign of the fill flag from the buffer register 2 to the interrupt level by command or by data, depending on the contents of the buffer register 2. The fill sign signal from the buffer register 1 only triggers the data interrupt. This signal is fed through line 45 to input element I 31 and further to input element I-NO 35. Thus, if buffer register 1 is empty, then on bus 45 there is a signal of a logical unit that is inverted by element 31 and i-line 182 a data interrupt signal appears. The trigger 28 must be reset after reading a command from buffer register 2, i.e. The switching of the next signal of the filling indicator from buffer register 2 to the data level is prepared in advance. Reading the buffer register 2 and 5, resetting the trigger 28 is organized by the elements OR NOT 24 and AND-NOT 25. When reading the buffer register 2, the auxiliary computer 13 sets the register address 2 on the buses;

 accompanied by the signal Strobe addresses along the line 17jQ, allowing the operation of the decoder 26 (ROM). At the first output of the decoder 26, a logical zero signal appears, arriving

5 to one of the inputs of the element circuit

OR-NOT 24. Due to the fact that the first output of the decoder 26 is also used to generate a signal to the buffer, register 1, to generate a read signal of the buffer register 2, two lower-order bits of the address are used, respectively, at the inputs of the elements OR NOT 24 and AND-NOT 25. Then when referring to

5 buffer register 2 (on lines 17217 is the address) at the input of the YLI-NE 24 element will be a logical zero signal and, accordingly, the output of a logical unit signal input to the AND-NE element 25. The second input of the AND-25 element contains a signal logical unit from the low bit of the address, and as a result a negative impulse is formed at the output, the falling edge of which flushes the trigger 28, and on line 47 enters the input of the buffer register 2. If the tires 17 have the address of the buffer register 1, then the low bit d addresses on line 17 will not allow the generation of a pulse for reading the buffer register 2. In the case of recording information into the buffer register 1, the auxiliary computer 13 (except for the address on the lines) exposes on the line P a Vsdach signal arriving with a logic zero level at the input of the W-HCH element 37 which, on the output of line 48, sends a signal to buffer register 1,

Similarly, a signal is generated in the register-5 order register, received via bus 49 to the control input of register 5 (the second output of the decoder 26 is used to form this signal). The third output of the decoder 26 is used

To produce a reading signal of a gyroscopic, 4 word condition, When the adder 26 decoder input busses 26, the register 4 registers at its third output, the logical signal of the unit arriving at the second input of the element 39, the other input of which sync pulses from the direct output of the one-shot 27. As a result, the positive pulse from the output of the element E39 is taken along the line 50 | on the input of the reading of the register 4 word states. Element AND 40 is used to generate a recording signal in register 4 of the word state. A signal from the register of the word state is sent to one of the inputs of the element 40 through the lines 424 of the block 8, to the other input comes a pulse from the direct output of the one-shot 27 and as a result of. the output of element 40 is removed; the signal of entry is inputted through line 50 to the control input of register 4. Finally, the input of element I 41, along line 42g, receives a signal to confirm the recording from block 8, the signal arriving through line 48 is also generated read buffer register 1. In addition, along lines 46 and 46., in block 8, two synchronization signals are received.

The communication unit 8 with the input / output channel (Fig. 3) operates as follows:

The operation algorithm of block 8 is shown in FIG. 4. The elements 51, 61, 62 and 63 and the elements OR-NO 52, 53 and 54, together with the multiplexer 55, select the next address of the micro-command through the register 56.

At each operation cycle (synchronization is performed by a signal coming from block 3 via line 463) at the address contained in register 56, a microcommand is selected from memory 58 containing the following field: control field (bit; s; s; MxQ-Mxj ), the subscriber signal field:. (line signals), control signal field (line signals 2t.21c.), word register registers (line signals), flag HB (flag of the initial sample). Next, the bits from the first access of memory 58 go directly to the input of register 56, and the bits of the second memory output 58

arrive at the control input of the multiplexer 55, connecting the desired input of the multiplexer 55 to the input of the register 56. The signal from the output of the multiplexer 55 together with the bits forms the address of the next micro-command.

Thus, depending on the output state of the multiplexer 55, a transition can be made to one or another memory cell 58, which ensures the branching of the algorithm (Fig. 4). The contents of the micro-operation are entered, respectively, into the subscriber signal register 59 (provides signal exchange with the mainframe 14), into the control signal register 60 (provides control of the remaining units of the device) and, if necessary, is output via elements 61, 62 and 63. register information input 4 word states pointers End of exchange (KO), Error in data (Error. bus), Failure in device. All registers are entered by a clock signal coming in on line 46, and a reset by a general reset signal on line 46. Branch trigger 57 sets the flag HB, which is necessary for the branching algorithm (Fig. 4). To better understand the mechanism of operation of block 8, consider for example a few short branches of the algorithm depicted in FIG. four. .

The initial mode of block 8 is the standby mode, when successively checking the presence of one of the BSIN, Start GAT, Start ChT flags at the input of multiplexer 55. This is done in the following way: From memory 58, a microinstruction is read, in which the bits of the control field select the input of multiplexer 55 to which the BSIN flag arrives. If the flag is absent (BSIN-0), then in the next micro-command, the flag, Start PF and so on, is similarly checked. If the BSIN flag is present at the input, then in the next world command, a TRB-A signal is set, which is then entered into the 59 sig register; the control signal and through line 20 enters the main computer channel 14. Consider the case of the spreading, injury of the FBG-K signal in case When the device does not require servicing. In this case, after the FBG-K signal at the input of the multiplexer 55 is modified, the contents of the register 56 are modified, and the next microcommand is selected, in which the presence of the ADAP signal (Address recognized) is checked. In this case, the input of the multiplexer 55 is selected, to which the signal from the output of the element is received, AND 51. At one input of the element 51, the line 21 receives the signal ADR-K from the main computer channel 14, and the other input receives the signal ADAP via bus 65. from block .10 address comparison. If the address is not recognized by the device or there is no ADR-K signal, then the output of element 51 will be a logical zero signal and the next microcommand will check the flag, Start Th, then Start Back, BSIN If none of the flags is present at the input of multiplexer 55, then this means that the device is not serviced. it is required and it should propagate the FBG-K thread of the BtiF-K signal further down the interface. This is done by installing in the subscriber signal register 58 a VBR-A signal arriving on line 20 into the main computer 14. Then a microinstruction is accessed selecting the input of multiplexer 55, on which on line 21 it sends a signal, VBR-K. When the host computer 14 removes a VBR-K signal from line 21, the next micro-command, is selected, is. From the memory of 58 microinstructions, the VBR-A signal in the register 59 of control signals will cancel. Then, it goes from the beginning to the beginning, and the block 8 works in the standby mode until there is no initiative from anyone, i.e. Until the Wits VBR-K signal or the BSIN flag. Note that all flags arrive at the input of the multiplexer 55 not directly. From the output of the register 5 orders, and from the output of the OR-NOT element 52, 53 and 54. At the inputs of the elements OR-NOT 52 53 and 54 respectively, from the output of the terminal 5 signals (level of logical zero) are received signals BSIN Start GAT, Start THU. The other inputs of the OR-NOT elements 52 and 53 are fed through the bus 67 by the signal of the filling indication from the buffer register 1, and to the other input of the element OR-NOT 54 by the bus 68 the signal of the filling indication from the buffer register is received. 2 This is done so that the flags are only perceived when information is in the registers. For example, an auxiliary computer 13 has set the Start status flag in the register 5, and the buffer register 2 is empty. Then at the output of the signal of the filling of the buffer register 2 there is a signal of the logical zero level, coming from the control output of the buffer register 2 via the bus 68 to the input of the OR-NOT 54 element. As a result, the output of the OR-NOT element 54 is the signal of the logical unit , called Start Reading (Start ThU). Thus, the Start Start flag is the Start Start register read signal, mixed with the signal of the buffer register 2 fill signal. The same applies to the Start Start and BSIN flags, the only difference being that the Start Start signals, the BSIN of the 5 orders register are mixed on elements IL-NOT 53 and 52 with a signal of the sign of filling the buffer register 1. Elements 61–63 allow to enter 4 word states into the register 4 — characterizing the quality and features of the conducted smelling, as well as making both computers equal in production the end of exchange procedure (pointers End of exchange, Error in the data, Failure in the device). Thus, the device provides the possibility of autonomous generation of various indicators and signals in accordance with the procedures of interfaces of the interfaced computers, which makes it possible to reduce the amount of work of the computer during the exchange and to increase the throughput of the device.

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Claims (1)

A device for interfacing two electronic computing machines, comprising first and second buffer registers, an exchange control unit, a state register, a switching unit, wherein the information input of the first buffer register is connected to the first information input of the device, the information output of the second buffer register is connected to the first information output of the device and information output of the word state register, the output of the switching unit is the second information output of the device, the first output and the input of the unit exchange controls are respectively the interrupt output and the control input of the device, and the second, third and fourth outputs are respectively connected to the control inputs of the second and first buffer registers and state register, characterized in that, in order to expand the class of tasks and increase the throughput of the device, a communication unit with an input / output channel, an address setting unit, an address comparison unit, a data and command register, a data and state register, an order register and a control unit are introduced, the second, third and fourth inputs of the exchange control unit are connected respectively to the control outputs of the second and first buffer registers and state register, and the fifth input and output, respectively, with the first output and input of the communication unit with the input-output channel, the second input and output of which are respectively, the synchronization input and output of the device, the third input and output are connected respectively to the control output of the second buffer register and the control input of the data and state register, information input and output which are respectively connected to the information output of the first buffer register and a first data input of the switching unit, the second information and the control inputs of which are respectively connected to the first output with the address setting unit and the fourth output of the communication unit with the input-output channel, the fourth input of which is connected to the control output of the first buffer register, the fifth and sixth inputs, respectively, with the outputs of the address and block comparing unit 1141418 A control input connected to the output of the data register and commands, the information input of the second buffer register and the seventh input of the block> communication with the input-output channel, the eighth input of which is connected to the output of the order register, the information and control inputs of which are connected respectively to the first information input of the device and the sixth output of the exchange control unit, the second output of the address setting unit is connected to the first information input of the address comparison unit, the second information input of which is the second information input of the device and is connected to the information input of the register of data and commands, the control input of which and the information input the word state register is connected respectively to the fifth and sixth outputs of the communication unit with the input / output channel, the communication unit with the input / output channel comprising a multiplexer, a branch trigger, a microprogram memory, a micro command address register, a subscriber signal register, a control signal register, four AND elements and three OR-NOT elements, the output and the first input of the micro-command address register being connected respectively to the input and the first output of the microprogram memory, the second and third information inputs, respectively, with the seventh input block and the multiplexer output, 'and the synchronization and reset inputs are with the first block input, the group of multiplexer information inputs is connected to the second and sixth block inputs, the outputs of the first AND element and the first, second and third elements OR-NOT' and · the branch trigger output, and the control input - to the second output of the firmware memory, from the third to fifth outputs of which are connected respectively to the information inputs of the subscriber signal register, register of control signals and branch trigger, synchronization and reset inputs of which ryh are connected to the first input of the block, the first inputs of the second, third and fourth elements And are connected respectively to the sixth, seventh and eighth outputs of the firmware memory, the second inputs to the first input of the block, and the outputs form the sixth output of the block, the output of the subscriber signal register is the second output of the block, the bit outputs of the register of control signals are, respectively, the first? <, third, fourth and fifth outputs of the block, the first and second inputs of the first element AND are connected respectively to the second and fifth inputs of the block, first and second inputs of first OR-NO element and to first inputs of the second and third elements OR-NO. form the eighth input of the block, the second inputs of the second and third OR-NOT elements are the fourth and third inputs of the block, respectively, and the exchange control unit contains four OR-NOT elements, seven NAND elements, a decoder, pulse shaper, a trigger, two elements NOT and three elements · AND, with the output of the first element OR NOT connected to the trigger reset input, the information input of which is connected to the logical zero bus, and the clock input and installation input are connected to the outputs of the first and second elements NAND, the output of the second element OR NOT connected to the first input of the first AND-NOT element, the first inputs of the second and third AND elements and the first AND element connected to the direct output of the pulse shaper, the inverse output of which is connected to the first inputs of the second and third AND elements, the first inputs of the fourth and of the fifth AND-NOT elements are connected respectively with direct and inverse trigger outputs, the second inputs are with the second input of the block, and the outputs are respectively with the first inputs of the sixth and seventh AND elements, the outputs of which form the first output of the block, and the second inputs connected respectively to the fourth input of the block and through the first element NOT to the third input of the block, the output of the third element I AND-NOT connected to the input of the second element NOT, whose output and the output of the first element AND NOT form the second output of the block, the first output of the decoder is connected to the first inputs / of the second and third elements OR, NOT, 1 second output - with the first input of the fourth element OR - NOT, the output of which is the sixth output of the block, the third output of the decoder is connected to the second input of the first element AND, the outputs of the first and second elements AND form the fourth output of the block, the outputs of the third element OR NOT and the element AND form the third output of the block, the outputs of the first elem NTA NOR and pulse shaper form the fifth. block output, first input of the first element OR-HF, the second inputs of the second, third and fourth elements of IPI-NOT, the input of the pulse shaper and the group of inputs of the decoder are connected to the first input of the block, the second inputs of the first element of OR-HE, the second and third elements · Comrade NAND, second and third elements | And form the fifth input of the block.