SU1667089A1 - Device for computers interfacing - Google Patents

Abstract

The invention relates to computing and can be used to create computer systems. The aim of the invention is to extend the functionality by providing automatic assignment of interface addresses. The goal is achieved in that the device containing the generalized unconditional transition trigger, the exchange start trigger, the exchange end trigger, the generalized conditional transition trigger, the interrupt trigger, two AND elements, the address decoder, the individual interaction trigger, the OR element, are entered four output shapers, four input shapers, eight NOT elements, address register, counter, four flip-flops, OR element, three delay elements, three AND elements, clock generator. 2 Il.

Description

The invention relates to computing and can be used to create computer systems.

The purpose of the invention is to expand the functionality by providing automatic assignment of interface addresses.

Figure 1 shows a block diagram of a computer connection to a homogeneous computing system; Fig. 2 is a block diagram of a device for interfacing computers.

A homogeneous computing system (FIG. 1) contains I computer 1 and its corresponding I 2 interface devices, each computer 1 of a homogeneous computing system being connected to its interface 2 device by a multi-bit bi-directional bus, the inputs / outputs of each interface 2 are connected to multi-bit bi-directional bus 3 (non-commutable system channel) using bi-directional multi-bit buses,

A device for interfacing computers (Fig. 2) contains a generalized unconditional transition trigger 4, an exchange trigger 5, an exchange termination trigger 6, a generalized conditional transition trigger 7, an interrupt trigger 8, an AND 9 element, an address decoder 10, an individual interaction trigger 11 , Element 12, Element OR 13, And 14 group of elements. Control input 15, reset input 16, system synchronization input 17, generalized conditional branch input 18, interrupt output 19, interrupt input 20, exchange control input 21, input 22 information

0 (VJ

About 00

ABOUT

information bus 23, individual interaction bus 24, generalized unconditional transition bus 25, exchange start bus 26, exchange termination bus 27, interrupt bus 28, generalized conditional branch bus 29, clock synchronization bus 30, input formers, 31-34, output drivers 35- 37, element 38, address register 39, counter 40, trigger 41, element 42, element OR 43, element 44, delay element 45, element 46, element 47 and 48, triggers 49 and 50, delay element 51 , element NOT 52, generator 53 clock pulses, output driver 54, elements NOT 55, flip-flop 56, NOT element 57, AND gate 58, delay element 59, NOT element 60, bus

61 initialization, identification bus 62, selection bus 63, computer number code output 64, computer number code output 65, start input 66 and initial setup input 67.

The device works as follows.

The addresses of the interface 2 devices are set up from any computer 1 of the computer system before the computer system starts operating or when new computer 1 is connected. The active computer 1 outputs an active signal to input 67 of the initial installation, which is fed to the input of the HE element 47 and the first input of the And 44 element At the output of the element I 44, a positive impulse appears, coming through the element NO 42 to the input of the imaging device 37, from the output of which the inverse impulse is fed to the system initialization bus 61 and through the imaging device 32 to the reset inputs the trigger 40 and the trigger 41 of all the devices 2 of the interface, which causes the counter 40 to be reset and 0 installed at the output of the trigger 41. The computer 1 outputs a high level signal to the start input 66, which is fed to the first input of the element 58 and to the second input element And 58 through the element NOT 60 and the element 59 delay. As a result, a positive pulse appears at the output of element 58. It enters the input of element 57, from the output of which the inverted pulse is fed to the inputs of the installation of flip-flops 49 and 56, causing the appearance of their outputs 1. Data 1 from the flip-flop 49 enters through the element OR 43 and the driver 35 to the bus 63 of choice, which is fed to the input of the installation of the trigger 41 of the adjacent interface 2, and 1 from the output of the trigger 56 enters through the driver 54 to the bus

62 identification, signaling the beginning of the process of setting the address of the device 2 interface, and the input of the installation of the trigger 50. The clock pulses from the generator output 53 clock pulses arrive through the element HE 52 and the element 51 of the trigger input 50 trigger 50. On the positive front of these inverse delayed clock pulse 1 from the output of the trigger 50 is fed to the input element And 46, allowing the passage of clock pulses from the generator output 53 clock pulses through the shaper 36 on the bus 30 clock synchronization, with which They come through the imaging unit 34 and the NOT 38 element to the synchronization input of the triggers 41 of all devices 2 of the computer system interface, and through the imaging unit 31 to the counting input of the counters 40 of all the devices of the two interfaces. The positive edge of the clock pulse at the counting input of the counter 40 increases its contents by 1, and the negative edge of the clock pulse entering the synchronization input of the triggers 41 through the HE 38 element passes 1 through the bus 63 of the choice from this device 2 to the next . On the positive edge of the second clock pulse, a binary code appears at the output of counter 40, corresponding to 2, which means that the second counter of counter 40 is 1, which is fed through a corresponding connection through the NOT element 48 to the input of the trigger 49, resetting it in O, which prevents the reproduction of 1 in the bus 63 of choice. Upon receipt of the 1st clock pulse (the value of i is equal to the number of computers 1 in the computing system, Fig.1), the binary code of the number i appears at its positive front, and its negative front G from the output of the trigger 41 enters the control input of the address register 39, which causes the contents of the counter 40 to be written to the address register 39, as well as the cut element NOT 55 - to the installation inputs of the flip-flops 56 and 50. dropping them into O, thereby prohibiting the passage of clock pulses from the generator 53 clock pulses through element And 46 per bus 30 tact new sync. The output of the flip-flop 56 also goes through the imager 54 to the display bus 62, a certificate of completion of setting the addresses of the interface devices.

Thus, in counters 40 of each device 2 interfacing, the binary code of the number of computers 1 is stored in this computer system, and in the address register 39 the number of this device 2 interfacing (and the corresponding computer 1) is stored. These values

can be read by the computer 1, respectively, at outputs 65 and 64.

Claims (1)

Claims An interface device for computers containing a generalized unconditional transition trigger, an exchange start trigger, an exchange end trigger, a generalized conditional transition trigger, an interrupt trigger, first and second AND elements, an address decoder, an individual interaction trigger, the OR element, the first inputs of the AND elements of the group being the information input of the device, and the outputs being the information output of the device and connected to the input of the address decoder, the output of which Connected to the setup input of the individual interaction trigger, the reset inputs of the individual interaction triggers, the generalized unconditional transition, the end of the exchange, the interrupt, and the generalized conditional transition are connected to the device reset input, the output output of the individual interaction trigger is connected to the first input of the first element, the second input of which is the input individual interaction of the device, the output of the first element AND is connected to the first input of the element OR, the second inputs of the elements AND groups of the subconnect Encoded to the output of the OR element, the second input of which is the device control input, the generalized unconditional trigger trigger input is the device control input, the start of the exchange start and the end of the exchange trigger input are the device's system synchronization inputs, the device interrupt input, the trigger setup input of the generalized conditional transition is the input of the generalized conditional transition of the device, and its output is the output of the system general A conditional transition, the output of the start of the exchange trigger is the output of the system start of the device exchange, the output of the exchange end trigger is the output of the system end of the device exchange, the inverse output of the interrupt trigger is connected to the first input of the second element AND, the second input of which is the interrupt input of the device, the second input element I is the interrupt output of the device, the forward output of the interrupt trigger is the output of the system interrupt of the device, the trigger output of the generalized unconditional transition is The output of the system generalized conditional transition of the device, characterized in that, in order to expand the functionality by ensuring the automatic setting of addresses of the interface devices, four input shapers, four output shapers, eight HE elements are entered into it. address register, counter, four flip-flops, an OR element, three delay elements, three AND elements, a clock pulse generator, the input of the first input shaping body being connected to the input of the second input driver, the output of the first output driver, and the input of the third input shaper connected 5 with the input of the second output driver and is the device initialization input-output, the output of the third output driver is the device identification output, the output of the fourth 0 output driver - output device sampling, input of fourth input driver - device sampling input, output of first input driver connected to counting counter input, output of third input driver - with counter reset inputs and first trigger, output of fourth input driver connected to installation input of first the trigger, the output of the second input driver - with the input of the first element NOT, the output of the second element OR - with the input of the fourth output driver, the output of the third element And - with the input of the first output driver, the second output 5 element NOT - to the input of the second output driver, the output of the second trigger is connected to the input of the third output Shaper; output of the first element NOT - to the synchronization input of the first 0 flip-flop, the output of which is connected to the control input of the address register, the first input of the second element OR, and the input of the third element NOT; the output of the address register is connected to the second input of the decoder 5 is the output of the device number code of the computer, the output counter is connected to the information input of the address register and is the output of the code number of the computer of the device, the second bit of which is connected to the input of the fourth element NOT. the output of which is connected to the reset input of the third trigger, the output of which is connected to the second input of the second element OR, the input 5 of the initial installation of the device is connected to the first input of the fourth element I and the input of the fifth element NO, the output of which is connected to the input of the first delay element whose output is connected to the second input of the fourth element I, the output of which connected to the input of the second element NOT, the device start input is connected to the first input of the fifth element I and the input of the sixth element NO, whose output is connected to the input of the second delay element whose output is connected to the second input of the fifth element And whose output is connected to the installation inputs the second and third triggers, the reset input of the second trigger is connected to the output of the third element NOT and the reset input of the fourth trigger, the output of the second 0 trigger - with the installation input of the fourth trigger, the output of which is connected to the first input of the third element AND, the output of the clock generator is connected to the input of the eighth element NOT and the second input of the third element AND, the output of the eighth element NOT to the input of the third delay element whose output is connected to the synchronization input of the fourth trigger, the output of the second trigger is connected to the input of the third output driver. and about about FIG. f Yu