SU1304031A1 - Interface for linking in redundant multiprocessor system - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in highly reliable multi-machine complexes and computer networks, while reducing the system recovery time in the case of jj 1J two of the three redundant processors connected via the device to the system backbone. Three processors 1, 2, 3 are connected to a device 4, which contains a block of 5 majority elements, four bus drivers 6, 7, 8, 11, a control unit 9, a first synchronization unit 10, a second synchronization unit 12. In the process of synchronous operation of processors 1, 2, 3, random data corruption may occur, which will cause the device to stop. To prevent it, block 12 serves to generate local control signals and organize repeated cycles of information transfer to the address of the corresponding trunk device. 1 z.p, f-ly, 2 ill. S (L oo 4

Description

113040312

The invention relates to computing the same time signal 1 according to the second input technique and can be used by block 12 to prohibit double passage of the synchronization signal by the processors, confirmed by highly reliable and distributed receiving data from the passive computer systems. x computers. 5 (C CIP B) to processors from

The aim of the invention is to reduce the external passive device, mowing the recovery time, working in accordance with the discipline ability aa account of the organization of the exchange, should arrive in the process-second cycles of displaying information in 10 second micros after accessing the trunk or external device. Every case

Figure 1 shows the functional distortion of information is accompanied by

device layout; FIG. 2 shows the function of the second input of the block 12.

The second circuit of the sync signal O, the number of which has been counted, is counter by counter 19. For overflow, Processors 1-3 are connected via counter 19 at its output in device 4 for. conjugation to reserve a Overflow (O) signal,

in a multiprocessor system, the standard signal duration of the oscontaining (fig.G) majoritarian 5 block is as follows (K OST N) the elemental elements are formed, the busbar delay 20 formers, the output of which

6-8, control block 9, first block 10 0 on the rising edge of the signal counter

synchronization, the bus driver 19 is set to its original state 11 and the second synchronization unit 12, the latter. Signal O from counter 19

backbone system. through the element OR 15 enters

The second block 12 synchronizationprocessors 1, 2, 3, as a signal K OSTN

(FIG. 2) contains three elements OR 13-and converts the processors 1, 2, 3 into pe15, two pulse formers 16, the communication with the console terminal. 17, element 18, counter 19, the element. In the event that during a process of 20 delays of the gram re-output cycle, the device operates as follows: formation from processors 1, 2, 3,

external device distorting the information in the initial state, the bus formations in two or more processors are not translators 6-8 in the Input mode, replenished counter 19, then after the half-width driver 11 closes the data device the external device is higher Because of the standard signal in a synchronous manner. The 355 K CIP N, which by the first

In case of distortion of information in the input of block 12, the counter 19 is reset.

two or more processors 1, 2, 3 blocks in the initial state and completes the cycle

9 forms direct and inverse signal-exchange with processors 1, 2, 3.

ly sign of failure. In the block in the prototype, when the number of a signal is produced, prohibiting 40 faults of each of the processors from transmitting information to the bus (but not two) at the same time, while keeping the former 11, their overall health will simultaneously increase. there is a rapid perepolp the first and second inputs from the block 9neniya counters random failures, that

45 signals will lead to stopping of the entire device and

1 and O. Signal O in case of failure, decreases its reliability (operating time

formations formed formate-failure). In the proposed device

Lem 16, having passed through the element OR 13, the counters of random failures are eliminated and prevent the formation, the number of random failures

Signal failure Channel failure and output 50 of each processor do not affect the operation of the device communication with the console terminal.

At the time of time, having passed through the formation In the prototype, with a random distortioner and an OR element, it exposes information in two processors

processors low level signal Pre-stops the device and interrupts the timer (C PRT H), which puts the processors in communication with the controller to initiate a program cycle on terminal terminals, which, when operating in real time of time

sors to an external device. In this case, in the proposed device, with random information distortion in two processors, repeated cycles of outputting information to an external device are organized.

Claims (2)

1. A device for interfacing in a redundant multiprocessor system, containing four bus drivers, a majority element block, a control unit, and a first block synchronization, information inputs from the first to the third bus drivers are information inputs-outputs from the first to the third device processors, respectively; information inputs from the first to the third bus drivers are randomly combined and connected to the information output of the fourth bus driver, information input-output which is the same as 1m input-output device, connected to the system mains, information outputs from the first to the third bus drivers dklyucheny to the inputs of the first to third control unit and the majority block elements, respectively, whose output is 30 and, the first and second inputs of which are connected to the information input of the fourth bus driver, the input and output groups of the first synchronization unit are a group are united with the first input of the group and the first input of the block, respectively, the first input of the element I is connected to the first input of the counter reset, the first inputs inputs of synchronization signals from the pro-35 of the second and third elements OR of processors and a group of outputs of the synchronization signals of the device trunk, respectively, the inverted output of the control unit's fault sign is connected to the input of the first synchronization block from the first to the third, whose outputs are connected to the chip sample input, to the input control information output of the fourth bus driver and The second and third inputs of the unit block are overflowed, the overflow output ka is connected to the second input of the OR element, and through the gate element to the second reset input of the second input of the block is connected by a pulse generator with the input of the second OR element, from the first to the third items information control inputs are outputs of a group of a block. The first to third bus drivers, the crystal sample inputs of which are connected to the logical input zero of the device, characterized in that, in order to reduce the recovery time by organizing repeated cycles of outputting information to the highway, a second synchronization block is inserted into it whose input and output groups are a group of sync signal inputs from the trunk and a group of sync signal outputs to the device processors, respectively, The direct and inverse outputs of the control unit failure flag are connected to the first and second inputs of the second synchronization unit. 2. The device according to claim 1, wherein the second synchronization unit comprises three OR elements, an AND element, two pulse formers, a delay element and a counter, the counting input of which is the second input of the block and connected via the first pulse shaper to the first input of the first an OR element whose second input is connected to the output of the element and, the first and second inputs of which are are united with the first input of the group and the first input of the block, respectively, the first input of the element I is connected to the first input of the counter reset, the first inputs are the second and third inputs of the block group, the counter overflow output is connected to the second input of the third OR element and through the delay element to the second counter reset input, the second input of the block is connected through the second pulse shaper to the second input of the second OR element, first to third outputs elements OR in Editor M.Tsitkina Compiled by A. Ushakov Tehred V. Kadar Proofreader, Cherni Order 1313/50 Circulation 673 Subscription BNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4