SU934466A1 - Microprocessor communication device - Google Patents

Description

(5) MICROPROCESSOR COMMUNICATION DEVICE

I

The invention relates to computing, in particular to the means of microprocessor control, and can find application in control systems for collecting and processing information and measuring systems.

A device containing switches, triggers, drivers and register P} is known.

The disadvantage of this device is a large amount of equipment.

Closest to the proposed technical entity is a device containing a status register, a first switch, a bidirectional switch, three flip-flops, three signal conditioners, seven AND elements and a GZ delay element.

A disadvantage of the known device efficiency and reliability in the organization of the exchange.

The purpose of the invention is to increase the utilization rate of the equipment and its reliability.

The goal is achieved by

that the microprocessor communication device containing the first switch, the input group of which is connected to the first group of inputs of the device, the output group of which is connected to the outputs of the first switch, the bi-directional switch connected by two-way communication to the microprocessor data bus and the common bus, state register, the group of inputs of which is connected to the second group of inputs of the device, three flip-flops, three signal conditioners, seven elements AND, and a delay element whose output is connected to the first input of the first trigger , The outputs of the first and second signal generators are connected respectively to the first and second v1hodami device outputs the first, second, third and fourth AND gates respectively connected to the third, Thu Werth, fifth and sixth outputs of the device, two kbmmutatora introduced. a counter, five OR elements and three AND elements; moreover, the first input of the device is connected to the input of the first switch and the first inputs of a bidirectional switch and the first, second, third and fourth elements of AND, the second input of the device is connected to the second input of the first trigger and the first inputs of the second trigger and the state register, the first output of which is connected to the second inputs of the first and second elements I, the third inputs of which are connected to the second output of the state register, the third and fourth outputs of which are connected to the second inputs of the third and fourth elements AND, the third input of the device are connected to the input of the first signal conditioner and the first input of the first OR element, the output of which is connected to the input of the delay element, the fourth input of the device is connected to the second inputs of the bidirectional switch and the first OR element, the fifth the input of the device is connected to the second input of the status register and through the second signal conditioner to the first input of the third trigger, the output of which is connected to the first input of the second element OR, the output of which is connected to the seventh output of the device, the sixth input of which is connected to the second input of the second trigger, the output of which is connected to the input of the eighth element AND, the seventh input of the device through the eighth element AND is connected to the second input of the second element OR, the outputs of the first switch are connected to the inputs the second and third switches, the output of the second switch is connected to the first inputs of the fifth, sixth and seventh elements And, the outputs of which are connected to the eighth, ninth and tenth outputs of the device, respectively, The first, second and third outputs of the third switch are connected respectively to the first inputs of the ninth and tenth elements AND of the second switch, the outputs of the first and second elements AND through the third element OR are connected to the input of the fourth element OR and the second input of the fifth element AND, outputs the third and fourth elements AND through the fifth element OR are connected to the second inputs of the sixth and seventh elements AND and the fourth element OR, the output of which is connected to the first input of the counter and is connected in series through The ninth And and the third third signal conditioner are with the third input of the second OR element, the eighth input of the device is connected to the second input of the tenth And element, the output of which is connected through the counter to the second input of the third trigger And the third formating element the signal is connected to the third input of the seventh element I. the drawing shows the block diagram of the device. The device contains a register of 1 states, switches 2-Ts, bidirectional switch 5, counter 6, triggers. the OR 10-14 elements, the AND elements, the delay element 25, the signal conditioners 26-28 and the external device 29. Switch 2 is provided for separating and interfacing the internal bus of the microprocessor trunk with the external trunk, as well as for generating levels and edges of address signals. In addition, the switch is used to disconnect the device from the common line in the event that it is transferred to another master module in the multiprocessor mode. Bidirectional switch 5 is used to interface the microprocessor data buses with a common highway. Register 1 is provided for capturing a microprocessor state word byte. External data exchange 29 is a memory location (RAM, ROM, PROM, etc., or read or write information from external input / output devices and denotes a functional combination of memory and ports. The proposed device works as follows In the first machine cycle, the microprocessor exposes the next command address on switch 2. The microprocessor sets the status word code on register 1. This word is a microprocessor state byte that determines the type of computer cycle to which the microprocessor starts at the moment.Type of the processor's computer cycles can be: writing or reading from memory, accessing the stack memory, writing or reading external input-output devices, enabling interrupts and enabling stops.By the state of the microprocessor from register 1 received at the inputs of elements 15-18, in which trunk read or write commands are formed. There are four types of trunk commands: writing information to an I / O device, writing information to a memory device, reading Information from an I / O device, reading information from a memory device through which the device accesses other modules of the system by means of a bus. The interaction of the microprocessor on the one hand and the common highway is interactive. When accessing the external device 29, the microprocessor in any case awaits the response of this device: readiness. A general availability signal is generated as follows. After the occurrence of one of the reversal commands, one of the inputs OR 12 and AND is activated, the element 12 functionally groups the write commands, and the element 14 reads the commands. Both groups are further integrated at the inputs of the OR 13 element and from its output arrive at the element AND 23. At its other input, the enable signal for the address groups of high-speed external devices comes from the switch 4. The signal thus generated from AND 23 enters through the driver 28 to the OR element 1 and from its output to the device output. At the same time, the reading signal arrives at the element OR 10 and then through element 25 to the trigger 7. At the same time, a command is generated for reading information from an external data exchange device. For this purpose, from the input of the element OR AND the reading command is fed to the input of the element And 19, and from the output of the switch 3 receives the enabling signal. If in switch t, external addresses are determined by its speed, then in switch 3, a resolution signal is generated for a specific address, or an array of addresses of subsets of speed groups. When these signals coincide at the output of the element 19, a reading command appears and the output of the external device 29 exposes the selected data that arrives at the switch 5. The delayed readiness signal is generated if the switch 4 determines that that this address belongs to the group of slow-acting devices. In this case, the output of the switch is activated, the signal from which is fed to the input of element 2. Through the open element 2k, pulses pass to counter 6, which starts counting. After counting the number of impulses to which counter 6 is programmed, a readiness signal appears at its output, which is fed to the input of the prohibition of the AND 24 element and to the input of the trigger 9. As a result of the prohibition of the AND 24, the pulses to the input of the counter 6, which stops at this fixed position. In order to synchronize with external sync pulses, the main sync pulses are fed to the other input of trigger 9. The signal of delayed readiness arrives at the element OR 11 and further to the input of readiness of the microprocessor. the formation of readiness from the write command is as follows The write commands are functionally combined in the OR 14 element and through the OR 13 element arrive at the input of the AND 23 element and at the input of the AND 24 element. Depending on which of the outputs of the switch 4 is activated, in a similar way as when reading, a forward signal or delayed readiness. The basic commands for writing to the external communication device 29 in conjunction with the permissive signal of the switch 3 are formed in the element AND 20. Through the element 21, an additional command to write to the conjunction with the signal of the switch 3 is fed to the input of the external device 29. element 25 enters the input of the trigger 7, which switches and resets register 1 to the initial state, therefore, the main write command ends. As a result of the action of the element 25 between the falling edges of the main recording command and the additional recording command, a time shift T is formed. It's necessary

to eliminate the transient effect that is caused in the data buses by the falling edge of the main write command in the event of a falling edge from the additional write command. These transients may be fixed in the memory cell or the output register of the external data exchange device and cause the entry of corrupted information. A specific mode of delayed readiness is the microprocessor operation in the step mode.

To switch to step mode, the device receives an active signal, which removes the prohibition from AND 22 element. At its other input, a signal is received from the output of trigger 8, which is activated by the leading edge of the sync pulse at the beginning of each machine cycle. The active signal from the output of the trigger 8 through the open element AND 22 enters the input of the prohibition of the element OR P, as a result of which the latter closes and blocks the flow of ready signals of the external device. The processor goes to the next machine cycle when the resolution signal is applied to the trigger B. On the leading edge of this signal, the 3-ger 8 is set to the position where the output signal is set to AND 22 at its output. As a result, the ban is removed from the OR element 11 and readiness signals from the other inputs of this element are passed to the seventh output of the device. The trigger 8 is returned to the blocking position of the next step on the leading edge of the sync pulse of the subsequent machine cycle, in which the microprocessor enters the idle state.

To exit the stepping mode, it is necessary to remove the active signal from. device input and thereby prohibit the input element And 22.

Thus, the proposed device allows to increase the efficiency of the exchange of the microprocessor with the bus at high speeds of its operation and reliability due to the compensation of the delay of signal propagation.

Claims (2)

Invention Formula A microprocessor communication device containing the first switch, the group of inputs of which is connected to The first group of inputs of the device, the group of outputs of which is connected to the outputs of the first switch, a bi-directional switch connected by two-way communication with the microprocessor data bus and the common bus, a status register, a group of inputs of which are connected to the second group of inputs of the device, three flip-flops, three signal conditioners , seven elements And a delay element, the output of which is connected to the first input of the first trigger, the outputs of the first and second signal conditioners are connected respectively to the first and second outputs us The three, first, second, third and fourth elements of And are connected respectively to the third, fourth, fifth and sixth outputs of the device, characterized in that, in order to increase the equipment utilization rate and its reliability, two switches are inserted into it, a counter, five OR elements and three AND elements, the first input of the device is connected to the input of the first switch and the first inputs of a bidirectional switch and the first, second, third and fourth elements of AND, the second input of the device is connected to the second input m of the first trigger and the first inputs of the second trigger and state register, the first output of which is connected to the second inputs of the first and second elements I, the third inputs of which are connected to the second output of the status register, the third and fourth outputs of which are connected to the second inputs of the Third and Fourth, respectively elements And, the third input of the device is connected to the input of the first signal conditioner and the first input of the first OR element, the output of which is connected to the input of the delay element, the fourth input of the device is connected with the second inputs of the bidirectional switch and the first element OR, the fifth input of the device is connected to the second input of the state register and through the second signal conditioner to the first input of the third trigger, the output of which is connected to the first input of the second OR element, the output of the last is connected to the seventh output of the device whose sixth input is connected to the second input of the second flip-flop, the output of the last is connected to the input of the eighth element And, the seventh input of the device through the eighth element And is connected to the second input of the second floor OR outputs of the first switch are connected to the inputs of the second and third switches, the output of the second switch is connected to the first inputs of the fifth, sixth and seventh elements AND, the outputs of which are connected to the eighth, ninth and tenth outputs of the device, respectively, first, second and third outputs The third switch is connected respectively to the first inputs of the ninth and tenth elements And and the input of the second switch, the outputs of the first and second elements And through the third element OR are connected to the input of the fourth element AND THE LI and the second input of the fifth element AND, the outputs of the third and fourth elements AND through the fifth element OR are connected to the second inputs of the sixth and seventh elements 93 6 AND and the input of the fourth element OR, the output of which is connected to the first input of the counter and through the series-connected ninth element I and the third signal conditioner - with the third input of the second element OR, the eighth input of the device is connected to the second input of the tenth element I., the output of which is connected through the counter to the second input of the third trigger and. the third input of the tenth element I, the output of the first signal conditioner is connected to the third input of the seventh element I. Sources of information taken into account in the examination 1. US patent K A0902i 8, cl. 36i "-90fl, published. 1978 2. USSR author's certificate №, cl. C About F 3/04, 1978 (prototype).