SU798998A1 - Storage cell for buffer storage - Google Patents

Description

The invention relates to automation and is intended to accumulate information signals in the order of their arrival. A device is known that contains groups of memory cells connected in series and control cells corresponding to each such group. one . The disadvantage of this device is the sequential passage of the information signal through groups of memory cells into the corresponding memory cell, which reduces the speed of such a device. A buffer memory device containing a group of series-connected cascades, each of which includes a memory cell and a control cell 2, is known. ycTpoftcjBa is a low speed. due to the transmission of information to the corresponding memory cell through the preceding Menus and low in reliability due to possible loss of information mation when transferring it to the corresponding conductive zapominoioschuyu cell due to the independent operation of the storage and yn ravl yuschih- cells. The closest in technical essence to the present invention is a buffer storage device, contains control cells and memory cells consisting of four T1 EX input elements AND-NOT, and the control cell consists of element 3 ai-OR, first and VTO. OA inputs of the first group whose inputs are connected to the corresponding elements of the IS-NOT storage cell of this cascade, the third input of the first group of inputs is connected to the corresponding input bus, and the output of the element 3-2И-2ИЛИ is connected to the first input of the second group of inputs by this element nta, with the preparation input and the second input of the second group of inputs of the 3-2И-2ИЛИ element of the previous cascade, and the installation input of the last cascade is the installation input of the entire device 3. The disadvantage of this device is its complexity, which is significant in cost elements and a large number connections between them. The purpose of the invention is to simplify a memory cell for a buffer storage device (RAM). This goal is achieved by the fact that in the memory cell for a buffer memory device containing memory elements, performed on LCK triggers, is a control element made on an NAND element, two information buses, a reset bus, and a formation bus O, in it K - inputs of ZK-flip-flops are connected to the formation bus -O., zero output of the first ZK-flip-flop is connected to ONE of the inputs of the NAND element and O-input of the second ZK-flip-flop, C-input of Q DK-flip-flops are connected respectively to information buses, R-whrdy OK-triggers subkey us to reset the bus, the other input of AND-NO element is connected to the zero output of the second flip-flop and ZK-U-ZK- input of the first flip-flop 5, an output of AND-NO element is connected to the output of the memory cell.

The drawing shows the functional diagram of the proposed memory cell.

The device connects the first and in the last 20K-triggers 1 and 2, the element AND-NOT 3, information buses 4 and 5, the dump bus b, the bus O 7 and the bus 8 overflow signal. The drawing shows one of the variants of the buffer memory, 25 performed on the proposed memory cell.

The device works as follows.

In the initial state, the triggers 1 30 and 2 are reset. On bus 7 there is a signal, PC triggers 1 and 2 of the first cell are ready to receive information on information buses 4, 5, on which there is, a signal O,

DK-triggers 1 and 2 of the next cells are closed by the signal O, coming from the NAND elements of 3 previous cells, on two inputs of which signals 1 are received from the inverse outputs of two for ZK-triggers 1 H 2 of each memory cell.

Upon receipt of the first impul | Spo information

signal

Bus 4 or 5 is triggered by the corresponding LSCI ZK-trigger 1 of the first cell of the 5th package and by its signal from the inverse output on the 3-input prohibits the operation of another ZK-trigger 2 of the same memory cell, and through the element AND-NOT 3 with a signal, from its exit to the zeroed, you can enable the PC flip-flop 1 of the next memory location to work. The arrival of the following impulse signals on the DK-trigger 1 triggered does not change the saves, since the K-input of each ZK-flip-flop 1 is connected to the bus b. In the future, the device works in a similar way. When the information arrives at the last memory location from the output of its IS-NOT 3, the device overflows a signal.

Thus, the proposed memory cell for a buffer storage device, the storage elements of which are made on UK-type triggers type 134TV14 with the necessary connections, and the control element on a simple NANDE element, compared to the prototype, is simpler and requires 50 chips. % less, and communications - by 40%.

Claims (3)

1. US patent 3588847, cl. G 11 C 7/00, published. 1971. / 2. UK Patent 129303 Cl. G 11 С 9 / рО, published. 1972. 3. USSR author's certificate in application number 2640143, cl. G 11 C 9/00 07/10/79 (prototype).