SU913359A1 - Interface - Google Patents

Description

The invention relates to computing and information-measuring equipment and can be used in systems for collecting and processing information that require the organization of the exchange of information between devices operating at different speeds, for example, between a measuring device that irregularly transmits data arrays and a computer.

A device for interfacing is known, which contains a buffer storage unit, a decoder, a marker register, a trigger, two delay elements, two gates, an OR — NOT element, and a driver [1].

It is also known a device for interfacing, which contains a memory device on shift registers, valves at the input of each memory cell, a reversing clock distributor, a shift pulse driver, a delay element and a trigger [2].

The disadvantages of the known devices are a large number of connections when switching vhbdnyh and output information buses with storage cells, the complexity of the control 2

Our scheme, heterogeneity of the device structure.

The closest in technical essence and the achieved result to the invention is the ^5th device for pairing, containing memory on p-bit shift registers, one of which is a service, η elements And and the synchronization node, to the first input of which the bus clock is connected

¹⁰ pulses, and the second - input Reading device information; the outputs of the ηth digits of the memory shift registers are the informational * outputs of the device, the information inputs of which are connected to the first ¹⁵ bits of the shift registers of the memory, the input of the indication of information availability is connected to the first digit of the service shift register; devices, sync robots

^and bits of the shift registers of the same name

memory is connected to the output of the corresponding element And, one of which inputs are connected to the bus clock (31.

3

° A disadvantage of this device is the low speed due to the fact that the analysis of the presence of free cells is conducted sequentially. This leads to the fact that the maximum allowed clock frequency is inversely proportional to the number of memory cells.

The purpose of the invention is to increase the speed of the device.

This goal is achieved by the fact that in the device for pairing, containing memory on p-bit shift registers, one of which is a service, n elements And and the synchronization node, to the first input of which is connected bus clock pulses, and to the second - input Read device information , the outputs of the ηth digits of the shift memory registers are information outputs of the device, the information inputs of which are connected to the first digits of the shift memory registers, the input of the sign of information availability is connected to the first p zryadom service shift register, η-th bit of which is connected to the output of the device is ready, the clock. similar bits of the shift memory registers are connected to the output of the corresponding element AND, one of the inputs of which is connected to the clock bus, additionally introduced η elements AND — NOT, and the inputs of each ί-th element AND — NOT connected to the-th and (ί + 1) -th digits of the service shift register and the output of the synchronization node, and the output of each of the AND-NOT elements is connected to the second input of the element I.

The drawing shows a functional diagram of the proposed device for pairing.

The device contains memory 1 on the shift registers 2 and 3, and register 3 is a service one, one IS-NO 4 and one AND 5 for each discharge of register 3 and synchronization node 6 consisting, for example, of synchronous trigger 7 and asynchronous trigger 8, as well as the bus 9 clock pulses, the input 10 is a sign of the presence of information, input 11 Reading information, the output 12 readiness of the device, information inputs 13 and information outputs 14.

The device works as follows.

Before starting all the bits of the register 3 and the triggers 7 and 8 are set to zero. Clock pulses are continuously fed to the bus 9 clock pulses. The code arriving at the input buses is accompanied by a unit on the bus indicating the presence of information connected to input 10 and entered into the first memory location 1 by sig913359

on bus 9. Then, in each clock cycle, the code entered is sequentially pushed into the output cell, and the entire contents of the memory is shifted. As soon as the information code reaches the output cell, the unit in the service discharge of this cell will establish a single signal at the output 12 of the device’s readiness and a zero signal at the output of the corresponding AND-NO 4 element, which will prohibit the passage of clock pulses through the And 5 element connected to it, resulting in the recording of new information in the output cell will stop. In a similar way, all the memory cells 1 are filled. In this case, the information inputs 13 of the device should receive codes with a frequency not exceeding half the frequency of the clock pulses. If this condition is met, the unit moving in shift register 3 is followed by zeros in the adjacent digits.

In this case, the analysis of employment of senior bits of the service shift register 3 is reduced, since only one subsequent discharge is analyzed.

Reading information from the output cell can occur at any time. Signal input 1! Reading the information sets the trigger 8 in one state. The first clock pulse that arrives after that sets trigger 7 to one state, which leads to the appearance of an enabling signal at the outputs of all AND – NOT 4 elements and resetting trigger 8. The next clock pulse shifts the contents of all shift registers by one bit to the right, i.e. the contents of all memory cells, and sets trigger 7 to the zero state. As a result, the following code to be read appears in the output memory cell. After this, the reading procedure can be repeated.

In case of memory overflow when recording information, a signal about the occurrence of this event can serve as a zero signal level at the output of the first element AND (the leftmost one in the drawing) at the time of arrival of the clock pulse.

Analysis of the proposed device shows that the independence of the minimum recording time for one code from the number of memory cells leads to an increase in speed, especially with an increase in the number of memory cells.

This device is simple in its organization and management, homogeneous in structure, which allows its implementation in the form of a large integrated circuit (LSI).

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The device can be most effectively used in cases when intermediate storage of a large amount of information is required, while it is possible to increase the number of memory cells without reducing the speed of operation.

Claims (1)

Claim ten A device for interfacing, which contains memory on p-bit shift registers, one of which is a service one, η elements I and a synchronization node, to the first input of which a 15-clock bus is connected, and to the second - an input Reading device information, outputs of the n-th bits shift registers are information memory device outputs data inputs of which are connected with the first of the discharge ₂₀ of the shear storage registers presence information attribute input connected to the first discharge service shift register , Nth 9 6 the discharge of which is connected to the device readiness output, the synchronous inputs of the same-named bits of the memory shift registers are connected to the output of the corresponding element I, to one of the inputs of which the clock bus is connected, which means that; in order to improve performance, η elements AND –NE are entered into it, with the outputs of the 1st and (ϊ + 1) -th digits of the service shift register and the output of the synchronization node being connected to the inputs of each 1st element AND –– and of the elements AND-NOT connected to the second input one of the nominal element I.