SU905860A1

SU905860A1 - Storage cell for buffer register

Info

Publication number: SU905860A1
Application number: SU802908505A
Authority: SU
Inventors: Борис Соломонович Цирлин
Original assignee: Институт Социально-Экономических Проблем Ан Ссср
Priority date: 1980-04-11
Filing date: 1980-04-11
Publication date: 1982-02-15

Description

Изобретение относитс к запоминакхдим устройствам.This invention relates to memory devices.

Известна чейка пам ти дл буферного регистра, построенна на основе трехстабильного триггера на элементах И-2ИЛИ-НЕ, причем в этой схеме входы первого элемента И каждого из трех элементов И-2ИЛИ-НЕ соединены с выходами двух других элементов И-2ИЛИ-НЕ 11.The well-known memory cell for the buffer register, built on the basis of a three-stable trigger on the I-2ILI-NOT elements, and in this scheme the inputs of the first element AND of each of the three I-2IL-NOT elements are connected to the outputs of the two other I-2IL-NO 11 elements .

Недостатком этой чейки вл етс невысокое быстродействие.The disadvantage of this cell is its low speed.

Наиболее близким техническим решением к данному изобретению вл етс чейка пам ти дл буферного регистра , содержаща три элемента И-ИЛИ-НЕ, включенные по схеме трехстабильного триггера так, что входы первого элемента И кгокдого элемента И-ИЛИ-НЕ соединены с выходами двух других элементов И-ИЛИ-НЕj и шесть входных шин, причем перва шина соединена с входами первого и третьего элементов И-ИЛИ-НЕ, втора - с входами первого и второго, треть - с входом первого, а остальные шины с входами второго и третьего элементов И-ИЛИ-НЕ 2.The closest technical solution to this invention is a memory cell for a buffer register containing three AND-OR-NOT elements connected in a three-stage trigger scheme so that the inputs of the first element AND of the AND-OR element are not connected to the outputs of the other two elements AND-OR-HE and six input buses, with the first bus connected to the inputs of the first and third elements AND-OR-NOT, the second with the inputs of the first and second, the third with the input of the first, and the remaining tires with the inputs of the second and third elements AND -Or-NOT 2.

. Однако в буферном регистре, собранном из чеек пам ти указанного. However, in the buffer register collected from the memory cells of the specified

типа кажда порци информации продвигаетс от первой чейки к последней, причем врем , через которое информаци по вл етс на выходе регистра, зависит как от собственных (реальных ) Задержек элементов последнего, так и от его заполнени информацией, что делает невозможной параллельную запись информации в регистр, так как such as each piece of information advances from the first cell to the last, and the time after which the information appears at the output of the register depends on its own (real) Delays for the elements of the last and on its filling with information, which makes it impossible to write information in parallel to the register , because

10 одновременно с записью информации в какую-либо чейку по шинам параллельной записи в ту же чейку может поступить порци информации по шинам сдвига из предыдущей чейки, 10 simultaneously with the recording of information in any cell on the parallel recording tires, a portion of information on shift tires from the previous cell can enter the same cell,

15 что нарушает правильность работы регистра . Отсутствие возможности параллельной записи в чейку ограничивает область ее применени .15 that violates the correctness of the register. The absence of the possibility of parallel writing to a cell limits its scope.

Цель изобретени - расширение об20 ласти применени чейки пам ти за счет обеспечени возможности параллельной записи информации.The purpose of the invention is to expand the scope of application of a memory cell by enabling the parallel recording of information.

Поставленна цель достигаетс тем, что в чейку пам ти дл буферного The goal is achieved by the fact that in the memory cell for the buffer

Claims

25 registers containing the first, second and third elements AND-OR-NOT, connected according to the three-stage trigger scheme, input buses, the first inputs of the second and third elements of AND-I.GM-NOT connected to the first input bus, the first and second inputs respectively the first and second elements AND-OR-NOT to the second input bus, the second inputs of the first and third AND-OR-NOT elements to the third input bus, the third and fourth inputs of the second and third AND-OR-NOT elements to the fourth input bus, fifth and sixth inputs of the second and third elements AND-OR-NOT. the fifth input bus, the third and fourth inputs of the first AND-OR NOT element to the sixth input bus, the fourth and fifth AND-OR-NOT elements connected by the CS-trigger circuitry, and the input buses from the seventh to the tenth, with the seventh inputs the second and third elements AND-OR-NOT and the first input of the fourth element AND-OR are connected to the seventh input bus, the eighth inputs of the second and third elements AND-OR-NOT respectively to the eighth and ninth input buses, the fifth input of the first element AND-OR -NO and the second input of the fourth element AND-OR-NOT connected to the ten th input bus, the third and fourth inputs of the fourth element AND-OR NOT respectively to the second and third input buses, the input of the fifth element AND-OR-NOT connected to the output of the first element AND-OR-NOT, the outputs of the fourth and fifth elements AND- OR-NOT are connected respectively to the ninth and tenth inputs of the second and third elements AND-OR-NOT. The drawing shows a cell diagram for a buffer register. A memory cell contains AND-OR-NOT 1-3 elements with AND elements 4-12, forming a three-stable cell trigger, and AND-OR elements NOT 13 and 14 with AND elements 15- 18, forming an RS trigger cell. The memory cell contains also input buses 19-28 (from the first 19 to tenth 28). The first inputs of the elements AND-OR-NOT 1 OF are connected to the bus 19, the first and second inputs of the elements AND-OR-NOT 1 and 2 respectively to the bus 20, the second inputs of the elements AND-OR-NOT 1 and 3 to the bus 21, the third and the fourth inputs of the elements AND-OR-NOT 2 and 3 - to the bus 2 fifth and sixth. The inputs of the elements AND-IL NOT 2 and 3 - to the bus 23. The third and fourth inputs of the element AND-OR-NOT 1 are connected to the bus 24 The seventh inputs of the elements AND-AND; W-NOT 2 and 3 and the first input of the element AND-OR-NOT 13 are connected to the bus 25, the eighth inputs of the elements AND-OR-NOT 2 and 3 - to the tires 26 and 27, the fifth input element AND-OR-NOT 1 and the second input element AND-OR-NOT 13 n Connected to bus 28, the third and fourth inputs of the AND-OR-NO element 13 respectively to the tires 20 and 21. The input of the AND-OR-NO element 14 is connected to the output of the AND-OR-NOT element 1, the outputs of the AND-OR-NOT elements 13 and 14 are connected respectively to the ninth and tenth inputs of the AND-OR-NOT 2 and 3 elements. The cell works as follows. The three-stable memory cell trigger has the following states, which are determined by the values at the outputs of elements 1-3: OH — information in the cell is erased; ,, BUT — in the cell, H is recorded; 101 - O is written in the cell. The states of the RS flip-flop, which are determined by the values at the outputs of the elements 13 and 14, correspond to: Exhaust gas — the cell is in the parallel recording mode; The 10 cell is in shear mode. In the parallel recording mode, the recording of information into a certain register cell on buses 26 and 27 through elements 9 and 12 occurs only after (1 + 1) - the cell goes into shift mode and the information in it is erased. After the information in the three-stable trigger is recorded and the output of its element 1 is established, the RS-trigger enters the state 10, i.e., the cell will operate in the shift mode. In this case, the change in the states of the three-stable trigger of the 1st cell in the shift mode is the same as in the well-known one, except that the information received by it in the parallel-recording mode is erased after it is transmitted to the (1 + 1) -th cell, regardless of the state of the three-stable (1 + 1) -th cell trigger (the last one at this time is in parallel recording mode). The RS-flip-flop of the 1st cell returns to the state 01 (parallel recording mode) after (i-rl) switches to this mode, and the information in the three-stable trigger of the ith cell is erased. Thus, the transition process of the cells of the buffer register to the parallel writing mode spreads sequentially from the first cell to the last one, and the process of switching cells to the shift mode also spreads sequentially, but in the opposite direction from the last cell to the first one. The buffer register, built on the basis of the memory cells described, allows parallel recording of information into the register, it is advisable to use to convert parallel code into a serial one. Claims A memory cell for a buffer register containing the first, second, and