SU1438007A2 - Series to parallel code converter - Google Patents

Abstract

The invention relates to computing, can be used to convert a serial bipolar code into parallel and is an improvement of the invention according to the author. No. 1231613. The purpose of the invention is to expand the field of use of the converter by enabling information retrieval, starting with a predetermined word, by introducing new blocks and corresponding functional relationships between them. 2 Il.

Description

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The invention relates to computing, can be used to convert a serial bipolar code into a pair: parallel and is an enhancement of the invention according to the author, No. 1 23 61 3 ,, the purpose of the invention is to uncover the field of application of the converter by providing the possibility of picking up information, starting with a predetermined word.

A: FIG. 1 shows a bl-ok scheme (/ serial-to-parallel converter; parallel; FIG. 2 — diag; frames explaining its operation;

The serial to parallel converter (fig) contains a conversion and mapping block 1.1, a controlled oscillator 1, a multiplex p 2, a shift register 3, a block 4, an odd parity, an output register 5, a controller 6, K conversion channels 7 , each of which includes an inverter 8, elements NOT 9 and 10, triggers 11-16, drivers 17-20 pulses, elements ШШ 21-27, elements И 28-33 j counters 34-35 ;, registers 36-38, block 39 operational memory, block 40 in comparison with VII, delay element 41.

The converter works in the following way,

After turning on the power in the controller 6, a Reset signal (FIG. 2a) is generated, which reset all K channels, including register 37; shift, triggers 15 and 16 in each of K channels 5, lock elements And 32 and 33.

At the Start command, coming from the element OR 22 (fig2v) ,, trigger 16 is flung and opens element And 33, Regardless of the Start command. clock pulses arrive (fig, 26) on the elements of AND 32 and the Pause signal on the trigger 15b. On the arrival of the first pause. The trigger 15 opens the element AND 32 and the clock pulses arrive at the shift register 37 synchronously with the information. After the eighth pulse arrives, the shift register 37 generates a strobe signal (fig 2d) 5 which arrives at the element 33 as well. through the element OR 27 and the element 4If- input delay Reset shift register 37., Before the Start command, the address 38 was entered in the address address required word from which you need to get information in

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converter. This address is compared in comparison block 40. The comparison block 40 has two outputs: output V O and output If a signal is triggered after passing the eight pulses (Figure 2e}, then the Strobe signal passes through AND 33 and zeroes the address counter 34 through GPI 26. If signal 0 is generated, then the Strobe signal does not pass through the AND 33 element, and the trigger 16 is reset and blocks the PI 33 element for further passage of the Strobe pulses until the new Start signal arrives,

Thus, finding the appropriate information, the channel will receive information as described for the known device.

Claims (1)

Invention Formula The serial to parallel converter according to autor., .. is about the number and so that5 with the aim of expanding the range of application of the converter by providing the possibility of reading information, starting with a predetermined word, into each of the K channels the fifth and sixth elements are entered, the fifth and sixth triggers, the shift register, the comparison unit, the fourth-fourth pulse generator, the seventh OR element, the delay element and the address register, the information and transmission inputs of which are connected respectively to the The main and ninth inputs of the conversion channel, the output is connected to the first input of the comparison unit, the output of the fifth trigger is connected to the first input of the fifth element. From the output of which is connected to the first input of the shift register, the first output of which is to the second input of the comparison unit, the output of which . It connects to the first inputs of the sixth trigger and the sixth element AND, the output of which is connected to the third, the input of the fifth element HJMj, and the code of the seventh element OR through the delay element is connected to the third input of the shift register, the second output of which is connected to the first input of the seventh element OR and the third input of the sixth element K, the second inputs of the seventh element 1 SHI. and the sixth trigger combined with the input of the even. 1438007 the third pulse generator, the third inputs of the seventh are connected to the fourth input of the channel, the trigger, the shift register and the second output of the fourth pulse driver — the input of the fifth element I are connected with the first input of the fifth .1 respectively to the outputs of the second trigger, the second input of which the plug-in element OR, the first trigger, is peppered to the output of the first driver element OR. element OR.