SU1336002A1 - Asynchronous priority device - Google Patents

Abstract

The invention relates to computing and can be used in control units for public devices. The purpose of the invention is to increase the reliability of the device, expanding the functionality by moving to the service of the next request after receiving the received information. The device contains a register of 1 requests, a group of elements NOT 5, a group of elements AND-NOT 4, a group of elements OR-NOT 6, a delay element 9, an element EXCLUSIVE OR 11, a group of delay elements 7, two triggers 10 and 12. The output information the device is delayed by the duration of the transition process in register 1 requests in a schematic way. The transition to the service of the next request is made depending on the presence of requests at the input of the device, in the presence of which the reset is performed in the write mode to the shared resource with the response signal of the shared resource, and in the read mode, with the read end signal. If there are no unattended requests, the device is reset by the source of the request, after which the device goes to standby. 1 hp f-ly, 4 ill. CO 00 O5 TH.

Description

The invention relates to computing technology and can be used in control units of common devices, for example, in control units of my-input memory.

The purpose of the invention is to increase the reliability of the operation of the device and expand the functionality by moving to the service of the next request in the read mode after receiving the information.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagram of the transition process in the register of requests in the case of simultaneous arrival of the request and prohibitory signals; in fig. 3 and 4 are time diagrams of the procedures for writing and reading, respectively.

The device contains a register 1, queries built on the elements AND-NOT 2 and 3, the group of elements AND-NOT 4, the group of elements NOT 5, the group of elements OR-NOT 6, the group of elements 7 delay, the element AND-NOT 8, the element 9 delay, trigger 10, EXCLUSIVE OR 11 element, trigger 12, request inputs 13, device read inputs 14, device response inputs 15, input 16. End of device maintenance, device outputs 17.

The device works as follows.

In the initial state, the request inputs 13, the device read inputs 14, the device response inputs 15 and the device clock input 16 contain zeros. On the direct inputs of all bits of register 1 there are zeros. On the direct outputs of all bits of register 1 there are units, so the output of the AND-HE element 8 is zero, the inverse output of trigger 12 is 1, the inverse outputs of all bits of register 1 are 1, and the outputs 17 of the device are zeros.

The logical units of the requests from the inputs 13 are fed to the forward inputs of the bits of register 1, while logical outputs are formed at the forward outputs of the corresponding bits of register 1. At the output of the NAND element 8, a logical unit is formed, the occurrence of which causes the appearance of zero on the inverse outputs of those bits of register 1, on the corresponding inputs of which 13 there are no queries. The appearance of a logical unit at the output of the element IS-NE 8 prohibits the further recording of information in the request register 1.

If any request at input 13 comes simultaneously with the prohibition signal from the output of the NAND element 8 (single and zero inputs of the corresponding register 1 bit appear at the same time), through time t after the arrival of single signals (t is time delays on one element) on the forward and inverse outputs of the corresponding register 1 bit, zero signals are formed (Fig. 2). Zero signals on the forward

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and inverse outputs through time again cause the appearance of single signals on the forward and inverse outputs of the corresponding register 1 bit.

The further development of the oscillatory process will be prevented by a zero signal from the output of the corresponding delay element 7, which prevents the transition to the zero state of the inverse output of the corresponding register 1 bit while the direct output of this bit will go to the zero state after 3t .

A single signal from the output of the NAND element 8 through the delay element 9 enters the clock input of the trigger 12 and the leading edge of this signal sets the trigger 12 to the one state, and the delay element 9 and the trigger 12 form a nonlinear delay element, i.e. provide a delay of a single signal with a minimum delay of the zero signal. The parameters of the delay element 9 provide a signal delay for the transient time in register 1.

The zero signal from the inverted output of the trigger 12 is fed to the inputs of the elements of the OR-NOT 6 group, but a single signal appears only on one output 17 corresponding to the most priority request fixed in register 1. Before the end of processing each request to input 16. "End the device serves a single signal, the leading edge of which records information from the output of the EXCLUSIVE OR 11 element in the trigger 10.

If the inputs 13 contain a partial number of requests, the output of the EXCLUSIVE OR 11 element is zero and the trigger 10 is set to the zero state, and the single signal from the inverse output of the trigger 10 does not block the signal from passing through AND-NOT 4. At the end of the internal the service cycle to the corresponding response input 15 of the device receives a single signal.

If the served request source performs a write operation (Fig. 3), a zero is present at the corresponding read input 14, and NOT at the output of the corresponding element 5, so the appearance of a single response signal causes the appearance of a zero at the output of the corresponding AND-NOT 4 group . This causes the occurrence of a unit at the direct output and zero at the inverse output of the corresponding register bit 1 and at one of the device outputs 17 the next request with the highest priority.

If the served request source reads (reads) information (Fig. 4) from a common resource, a single signal appears at the corresponding device input 14, a zero signal is output at the output of the corresponding element NOT 5 and a single signal appears at the corresponding device response input 15 It does not cause the appearance of a zero at the output of the corresponding AND-HE element of the 8th group. The request source, having received the information, removes the read signal, which causes the appearance of a single signal at the output of the corresponding NOT element of the 5th group and the appearance of a zero at the output of the AND-HE element of the 8th group, which resets the corresponding register of the 1 request.

If during the service of the last request there are no new requests at the inputs 13 of the device, the output of the Request element is connected to the first single input of the i-ro bit of the request register, characterized in that, in order to increase the reliability of the device, a group of delay elements is entered into it , a group of elements OR-NOT, an element NAND, a delay element and the first trigger, the inverse output of the gth bit of the query register is connected to the first input of the i-ro element OR-NOT group, to the input of the gth delay element, and with t-m input of the element is NOT in the output of which is connected to the input of the delay element, the first zero inputs of all bits of the first register of requests and the zero input of the trigger, inverse ON or 11, is formed the unit 5 output of which is connected to the second inputs (since at the inputs 13 there is only one single signal corresponding to the served at the moment, the request) and the appearance of a single signal at the input 16 "The end of the device service causes the appearance of a zero at the inverse 20 with the second single input of the g-th trigger trigger 12.p yes register s, a direct output j-ro

Dami all the elements of the OR-NOT group, the outputs of which are connected to the group of outputs of the device, the output of the delay element is connected to the clock input of the first trigger, i-to the response input of the device soyol from the inverse output of the trigger 12, enters the inputs of the elements AND-NOT 4, blocks the appearance of a zero at the output of the corresponding element of the IS-NE 4 group, both when the response signal appears at input 15 and when the read signal is removed at input 14 (if a reading operation is performed). In this case, a reset from the corresponding register bit 1 of the request will be performed by removing a single signal from the corresponding request input 13 after completing all operations for the source of the request. In this case, on the direct outputs of all bits of register 1 requests are formed units, the output of the element IS-HE 8 forms a logical zero, which causes the appearance of inverse outputs of all bits of the register 1 requests for single signals.

Thus, the device comes to the initial state and waits for the next service request.

Claims (2)

1. An asynchronous priority device containing a request register, and 25 the bit of which {/ 1,) is connected to (/ - | -2) -th inputs of the elements OR NOT the group from (/ + 1) -th to L-th, the output of the i-th group delay element is connected to the second zero input / -SH yes register requests. 2. The device according to claim 1, characterized in that, in order to expand the application area by going to service the next request after receiving the received 2Q information, a group of AND-NOT elements, a group of NOT elements, a second trigger and an EXCLUSIVE OR element are entered into it. The gth input reading device is connected to the input of the i-ro element of the NOT group, the output of which is connected to the first input of the gth element of the IS-NOT group, the output of which is connected to the second single input of the g-th bit of the query register, g device’s mating input is connected to the second in With the move of the i-ro element of the NAND group, the rth request input of the device is connected to the i-th 40 by the input of the EXCLUSIVE OR element, the output of which is connected to the information input of the second trigger, the inverse output of which is connected to the third inputs of the AND-NOT group, the input “End 35 ,,,., g -,, the device service is connected to the i-th request input (i, N; N - the number 5 tsu, the input of the second trigger. requests) is connected to the first single input of the i-ro bit of the request register, characterized in that, in order to increase the reliability of the device, a group of delay elements, a group of OR-NOT elements, an NAND element, a delay element and the first trigger are entered into it the inverse output of the gth bit of the register of requests is connected to the first input of the i-ro element of the OR-NOT group, to the input of the g th element of the delay element, and to the tth input of the AND-NOT element whose output is connected to the input of the delay , the first zero inputs of all bits of the first register VAVO trigger input and zero, inverse output is connected to the second vho- of the connections to the second input unit of the ith row different requests register, a direct output j-ro the output of which is connected to the second input with the second single input of the nth section of the query register, direct output j-ro All the elements of the OR-NOT group, the outputs of which are connected to the group of outputs of the device, the output of the delay element are connected to the clock input of the first trigger, the output output of which is connected to the second input to the second single input of the 6th time - p yes register requests, direct output j-ro five the bit of which {/ 1,) is connected to (/ - | -2) -th inputs of the elements OR NOT the group from (/ + 1) -th to L-th, the output of the i-th group delay element is connected to the second zero input / -SH yes register requests. 2. The device according to claim 1, characterized in that, in order to expand the application area by going to service the next request after receiving the incoming information, a group of AND-NOT elements, a group of NOT elements, a second trigger and an EXCLUSIVE OR element are entered into it. The gth input reading device is connected to the input of the i-ro element of the NOT group, the output of which is connected to the first input of the gth element of the IS-NOT group, the output of which is connected to the second single input of the g-th bit of the query register, g device’s mating input is connected to the second in Odom i-ro AND-NO element group, the ith interrogation input device connected to the i-th 0 input element EXCLUSIVE OR, the output of which is connected to the information input of the second trigger, the inverse output of which is connected to the third inputs of the elements of the IS-NOT group, the input "End five FIG. 2 Fig.Z