SU1226467A1 - Two-port priority device - Google Patents

Abstract

The invention relates to digital computing and can be used in control units for public devices, such as shared memory. The purpose of the invention is to increase the reliability of the device by preventing a conflict situation and the occurrence of spurious signals at the device outputs. This is achieved by introducing into the known device three elements NOT with corresponding functional connections between them and known blocks of the device. 1 il. N) GO 05 4 O5

Description

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The invention relates to digital computing and can be used in control units for public devices, such as shared memory.

The purpose of the invention is to increase the reliability of the device by preventing a conflict situation and the occurrence of spurious signals at the device outputs.

The drawing shows the functional diagram of the device.

The device contains three elements NOT 1, four elements AND-NOT 2, - 2, the first and second inputs of devices

and

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first and second outputs

4,. And 4j devices.

The device works as follows.

In the initial state, the signals at the inputs 3 and 3 are equal to zero, the outputs of the elements AND-NOT 2, -2 contain single signals, and the signals at the outputs 4 and 4, the devices are equal to zero.

In the case of a signal arriving at one of the information inputs 3, or 3,., The trigger assembled on the first and second elements AND-NOT 2, and 2 is set in the stable position at the output of one of the elements AND-NOT 2, or a stable signal appears), a single signal appears at the outputs 4 or 4 of the device, and the arrival of a signal at another information input does not change the state of the device. At the output of the third element, AND-NOT 2 J, in this case there is always one. The first and second elements NOT 1 and 1 function as a delay line preventing the false operation of the third element NAND 2, which occurs in the case of a small time interval between the input signals.

The conflict situation, which may occur in case of simultaneous arrival of signals on both inputs 3, and, 3, is characterized by the absence of a stable O at the output of one of the AND-HE elements 2, and 2. At the outputs of these elements, oscillations of the output signals occur with a high frequency which is determined by the parameters of these elements. In order to avoid the passage of these signals to the outputs of the device, the element is NOT I. and the element IS-NOT 2., as well as the elements AND-Hp; 2 are performed on more inertial elements (on chips with lower speed) than AND-NOT 2, and 2. Thus,

for elements 1 and elements 2 and 2, a conflict situation arising on elements AND 2, and 2 can be represented as the presence at the outputs of elements AND 2

and 2, single signals.

Take the delay time of the signal on the elements 1 and 1, and the elements of the EIA 2 and 2 3at, and the time. Delay

signals on elements AND-NOT 2 and 2 and elements NOT 1 - for 21.

When two signals simultaneously arrive at the first and second inputs 3 and 3, the output state of the elements

AND-NOT 2 and 2 (subject to the assumptions made) does not change and remains equal to one, the signal at the outputs of device 4 and 4 is still absent. After a period of 2i

a unit appears at the first input of the AND-NOT 2 element, they are already present at the remaining inputs, and after 4i from the arrival of information signals, the output of the element 2 appears a zero signal, which is 2 times through 2 t through the AND- element Does not pass to the second output of the device - -.

Due to the fact that the conflict situation on the elements AND-NOT 2, and 2 after some period of time can be resolved (i.e. one of the elements AND-NOT 2 or 2, can be indicated as a stable zero at the output ), in order to avoid a conflict at the output of the device (in the case of, if a stable zero is formed at the output of the AND-NOT element 2) a trigger,

assembled on the elements AND-NOT 2, and 2, by applying a zero / o signal from the output of the element AND-NOT 2 to the first input of the element AND-NOT 2, is set to a position at which zero can

set only at the output of the element AND-NOT 2. After a time of 2 L, zero appears at the output of the AND-HE 2, element, a unit is formed at the output p of the element AND-NOT 2, and only the signal taken from the output of the element AND-NOT 2a passes through the second output of the device 4j the invention

A two-input priority device containing four NAND elements, the first request input of the device is connected to the first inputs of the first and second NAND elements, the output of the first NAND element is connected to the second input of the second AND element, and the first input of the third NAND element the output of which is connected to the second input of the first NAND element, the output of the second NAND element is connected to the first input of the fourth AND NAND element, characterized in that, in order to increase the reliability of the device operation by preventing confic by vleSostavitel G.Ponomareva Editor T.Kugrysheva Tehred V.Kadar Corrector I.ErDeyi

Order 2135/49 Circulation 671 Subscription All-Russian Institute of Scientific and Technical Studies of the USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab., A / 3

Production and printing company, Uzhgorod, st. Project, 4

264 (7

the false signals at the outputs of the device, it contains the element NOT, the second request input of the device is connected to the second input 5 of the third AND-NOT element and through the first and second elements NOT to the third input of the second AND-NOT element, the fourth input of which is connected to the output of the third NAND element, whose third input is connected to the output of the second NAND element, the output of the first NAND element is connected to the second input of the 4th NAND element, the output of which is the first 15 information output of the device, output the third element II E through the third element is NOT connected to the second information output of the device.

Claims (1)

Claim A two-input priority device containing four NAND elements, the first request input of the device is connected to the first inputs of the first and second NAND elements, the output of the first NAND element is connected to the second input of the second NAND element and the first input of the third NAND element the output of which is connected to the second input of the first AND-NOT element, the output of the second AND-NOT element is connected to the first input of the fourth AND-NOT element, characterized in that, in order to increase the reliability of the device by preventing a conflict situation and False signals on the outputs of the device, it contains three elements of NOT, with the second request input of the device connected to the second input 5 of the third AND-NOT element and through the first and second elements NOT to the third input of the second AND-NOT element, the fourth input of which connected to the output of the third AND-NOT element, the third input of which is connected to the output of the second AND-NOT element, the output of the first AND-NOT element is connected to the second input of the fourth AND-NOT element, the output of which is the first 15 information output of the device, the output of the third element AND- NOT through the third element is NOT connected to the second information output of the device.