SU1550523A1 - Device for interfacing two trunks - Google Patents

Abstract

The invention relates to automation and computing and can be used to interface two electronic computers in computer complexes. The aim of the invention is to increase the speed of information exchange between backbones by fully utilizing the time between calls to the memory unit. The goal is achieved by the fact that a device for interfacing two highways, containing a pulse generator, a NOT element, a memory unit and two communication units, each of which contains an address register, a zone decoder, a group of elements And, a trigger, two elements And a commutator switch, four OR elements, two delay elements, and two pulse formers on the signal decay are introduced. The introduction of new elements and connections ensures that the address registers are reset immediately after the end of the access to the memory block, which results in the full use of the time between calls to the memory block, the blocking time of one interface block by the other is reduced, and the device speed is improved. 2 Il.

Description

The invention relates to the field of automation of computer technology and can be used to interface two electronic computers in a computer system.

The purpose of the invention is to increase the speed of information exchange between backbones by fully utilizing the time between calls to the memory unit.

FIG. 1 is a schematic of the device for interfacing two highways; in fig. 2 - timing diagrams of control signals for the case of the organization of highways according to OST AND 11.305.903-80.

The device contains registers 1, 2 addresses, pulse generator 3, decoder 4 zones, group 5 elements AND, element 6, group 7 elements And, code 8 decoder, triggers 9, 10, elements 11, 12, 13, 14, elements OR 15, 16, 17, 18, delay elements 19, 20, memory block 21, bus switch 22, pulse drivers 23, 24, bus switch 25. FIG. 1 shows the address data busses 26 of the first highway, the first bus traffic control bus 27, the second bus traffic control bus 28, the second bus address data buses 29, the read bus 30 and the first bus 31

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SL

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Highways, 32 read tire and 33 tire

Records of the second line, bus 34, 35 response signals.

The address registers 1, 2 are for receiving and storing the address code of a memory cell into which information is recorded. The pulse generator 3 and the element HE 6 are intended to form two mutually inverted sequences of pulses. Decoders A, 8 zones are designed to decode the address code and determine whether the address is in the memory zone.

The signal from the output of the flip-flop 9 opens the trunk switch 22. In this case, the transmission direction of the trunk switch 22 is determined by the presence of one of the signals from the first highway Read or Write, i.e. in a bidirectional trunk, either the word to be written to the memory unit 21 is transmitted, or the word is read from the memory unit 21 and supplied via the trunk switch 22 to the buses 26 of the first highway.

The address in memory block 21 arrives

Groups of 5, 7 elements And commute, through a group of 5 elements And, and admin30

35

from address codes to the address input of memory block 2i. The triggers 9, 10 are intended to form the control signals for switching and blocking information. Elements II, 12, 13, 14 are assigned to switch the write and read signals from the trunk. The elements OR 15, 18 perform the logical addition of the write and read signals. The elements OR 16, 17 carry out a logical summation of the read and write signals from the two highways. Delay elements 19., 20 delay the write and read signals. The memory unit 21 is designed to receive, store and output information exchanges between trunk lines. Pulse drivers 23, 24 are designed to generate pulses based on the decay of delayed write and read signals by elements 19, 20. Switches 22, 25 switch information from the trunks to the information input / output of the memory block 21.

The device for interfacing two highways operates as follows.

During the operation of both external devices (processors), the registers 1, 2 addresses on the fronts of the signals Exchange on the buses 27, 28 write down the address codes set on the buses 26, 29. When the address coincides with the addresses of the memory block 21, for example, in address register 1, zone decoder 4 issues a signal to trigger input 9. It triggers on the front of a pulse coming from pulse generator 3 output. When trigger 9 triggers, the reset input of trigger 10 receives a blocking reset signal; whose trigger 10 cannot trigger on a synchronous input.

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The read, write signals determining the operation mode of the memory block 21 are received through AND 11 12 elements, OR elements 16, 17.

The Response signal, which carries information about the end of memory access, is formed from the Read or Write signals from the output of the OR 15 element by delaying them on the delay element 19.

The signal decay Response at output 34 by shaper 23 generates a signal, which is used to reset the address register 1. In this case, the decoder 4 of the zone removes the signal at the input of the trigger 9. After the removal of this signal, the trigger 9 by the next pulse front from the output of the pulse generator 3 is reset and the blocking of the trigger 10 is released, i.e. The blocking of the second communication unit is released immediately after the end of the cycle of accessing the memory unit 21, without waiting for the next address to arrive at input 26, which in addition should not enter the address zone of the memory unit 21. The frequency of the pulse generator is set so that its half period is longer than the duration of the transient processes when the device is switched, i.e. so that a critical situation does not arise during transients at the moment of switching. Simultaneous triggering of the flip-flops 9, 10 is excluded, since the signals in their synchronous inputs are inverse.

Claims (1)

Invention Formula A device for interfacing two highways, comprising a pulse generator, a NOT element, a memory unit, 0 five about 5 0 five 0 five The read, write signals that determine the operation mode of memory block 21 are received through AND 11, 12, and OR 16, 17. The Response signal, which carries information about the end of memory access, is formed from the Read or Write signals from the output of the OR 15 element by delaying them on the delay element 19. The signal decay Response at output 34 by shaper 23 generates a signal, which is used to reset the address register 1. In this case, the decoder 4 of the zone removes the signal at the input of the trigger 9. After the removal of this signal, the trigger 9 by the next pulse front from the output of the pulse generator 3 is reset and the blocking of the trigger 10 is released, i.e. The blocking of the second communication unit is released immediately after the end of the cycle of accessing the memory unit 21, without waiting for the next address to arrive at input 26, which in addition should not enter the address zone of the memory unit 21. The frequency of the pulse generator is set so that its half-period is greater than the duration of the transients when the device is switched, i.e. so that a critical situation does not arise during transients at the moment of switching. Simultaneous triggering of the flip-flops 9, 10 is excluded, since the signals in their synchronous inputs are inverse. Invention Formula A device for interfacing two highways, comprising a pulse generator, a NOT element, a memory unit, the first and second communication units, each of which contains an address register, a zone decoder, an AND group, a trigger, a first and second AND elements, a trunk switch, and in each communication unit, the first group of information inputs / outputs of the trunk switch is - device outputs for connecting to the address and information buses of the corresponding highway and connected to the group of information inputs of the address register, whose information outputs are connected to the first inputs of the elements of the group and to the inputs of the desh the zone fader, the output of which is connected to the information input of the trigger, the direct output of which is connected to the second inputs of the AND elements of the group, to the first inputs of the first and second elements I, to the gate input of the trunk switch, the first control input of the trunk switch is the input of the device for connection to the write bus of the corresponding line and is connected to the second input of the first element I, the second control input of the line switch is the input of the device for connection to the read bus of the corresponding ma the gates and are connected to the second input of the second element I, the second groups of information inputs-outputs of the commutators of the first and second communication units are connected to the information inputs-outputs of the memory block whose address inputs are connected to the outputs of the elements AND groups the first and second communication units, the output 40 and OR, the outputs of the first and second pulse generator are connected to the OR clocks and connected respectively to the first trigger input of the first block with the write and read resolution inputs and the input of the HE element, the output of the block memory 0 which is connected to the clock input of the trigger of the second communication unit, the output of the trigger of the first communication unit is connected to the reset input of the trigger of the second communication unit, the output of the trigger of the second communication unit is connected to the reset input of the trigger of the first communication unit, the sync inputs of the first and second address registers The one-second communication units are connected to the inputs of the device for connection to the synchronization buses of the first and second highways, respectively, so that 5 of increasing the speed of information exchange between highways, the first and second OR elements are entered into it, and in each of the communication blocks - a pulse shaper, a delay element and an element 0 NOT, in each communication unit the first and second inputs of the OR element are connected to the outputs of the first and second elements AND, respectively, the output of the OR element is connected to the input of the delay element, the output of which is connected to the input of the pulse shaper, the output of which is connected to the reset input of the address register , the outputs of the delay elements of the first and second communication units are connected respectively to the outputs of the device for connecting to the response buses of the first and second highways, the outputs of the first AND elements of the first and second communication units are connected respectively, with the first and second inputs of the first element OR, the outputs of the second elements AND of the first and second communication units are connected respectively with the first and second inputs of the second element 0 five In connection Reading jK uaHHbie A. 27.28. 30 31 BEHIND Reading Records