SU1755290A1 - Device for interfacing two main lines - Google Patents

Abstract

The invention relates to computing and can be used in multi-machine and multiprocessor computing systems. The purpose of the invention is to simplify the device by changing the technical implementation of the exchange algorithm. The device contains a memory block, two trunk switches, two address registers, a switch block consisting of a zone decoder, eight AND elements, two 2I-OR-NOT elements, two delay elements, two OR-NOT elements. 1 il.

Description

The invention relates to computing and can be used in multi-machine and multiprocessor computing systems.

The aim of the invention is to simplify the device by changing the technical implementation of the exchange algorithm.

The drawing shows the block diagram of the device

The device contains a block of 1 memory, switches 2 and 3 lines, registers 4 and 5 addresses, a switch consisting of a zone 7 decoder, first through eighth elements AND 8-15, first 16 and second 17 AND-OR-NOT, the first 18 and second 19 delay elements, the first 20 and second 21 elements OR NOT. The drawing shows the tires 22 and 23, the readings of the write of the first highway of the buses 24 and 25, the readings and writes of the second highway, the information address buses 26 and 27, the exchange control tires 28 and

29, tires 30 and 31 of the response of the first and second lines.

Memory unit 1 is a set of memory chips having an input of address lines and a bi-directional information input / output (for example, K541RU2) and a control circuit generating a clock signal used as a response signal.

The address registers 4 and 5 are registers with three output states. As such registers can be used registers K533IR.

The decoder 7 of the address zone is a comparator (comparison circuit) of addresses, at the output of which a voltage level of zero appears when the address at its input coincides with the specified one. In the remaining cases, a high voltage level is present at the output of the decoder.

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The delay elements 18 and 19 are integrating PC chains, the delay time of which is chosen to be longer than the sum of the delay time of the exchange synchronization signal passing through AND-OR-NOT 16 or 17 elements, the time of address decryption on the decoder 7, and the signal passing time through OR elements NOT 20 and 21.

The remaining circuit elements are standard and come in the form of integrated circuits.

The device works as follows.

In the absence of exchange synchronization signals on lines 28 and 29, a low level signal is present. As a result, the outputs of the eighth and seventh 15 elements are And low signals and thus at the outputs of the first 16 and second 17 elements AND OR NOT high signals, at the outputs of the elements OR NOT 20 and 21 low level signals. The enable inputs of the first 2 and second 3 trunk switches receive low-level signals and the switches keep the information address buses 26 and 27 of the trunks from memory 1 off. The absence of unit levels at the enable inputs of AND elements 14-19 causes the signals from lines 22, 23 and 24, 25 to read and write from the first and second lines to the memory block 1, and the output synchronization signals of memory block 1 The tees do not pass on the answer line 30 and 31.

The mode of operation of the interface device depends on the levels of the synchronization signals on lines 28 and 29. The following cases of a combination of the presence of synchronization signals that determine different modes of operation of the device are possible.

The appearance of an exchange synchronization signal from one trunk side, in the absence of an exchange synchronization signal from the other trunk side.

The appearance of the synchronization signal from the exchange of both routes.

Consider the case of the exchange synchronization signal from the first trunk side, in the absence of the exchange synchronization signal from the second trunk side. The drop of the exchange synchronization signal from a low level to a high one, coming through line 28, records the address of the device that is being accessed address bus 26, in the first address register. The signal from line 28 arrives. to the second input of the seventh element And 14. On the first input of this element is a high level signal from the output of the second element AND OR OR 17 (since on the line 29 a low level signal) and therefore at the output of the seventh element AND 4 and the second and third

the inputs of the first element AND-OR-NOT 16 are set to a high level signal. A high voltage level is also present at the fourth input of the first element AND-OR-NOT 16, since the output of line 18

0 high level signal Thus, at the output of the first element AND-OR-NOT 16, a low level signal is set. This signal is fed to the input of the permission to issue the first register 4 addresses and as a result

5 address is fed to the input of the zone 7 decoder. When the address from register A coincides with the address of memory block 1, a low voltage signal is generated at the output of the decoder, and in the case of e0s, a high voltage level remains. Consider each of these cases.

If the address in register 4 does not match the address of memory block 1 (i.e. passes

5, a call not to the interface device) a high level of voltage will remain at the output of the decoder. As a result, at the output of the element OR NOT 20, a low level signal will continue to be present, coming to the enable inputs of the first switch 2 of the trunk, the first 8, the third 10 and the fifth 12 I. Elements. As a result, the information inputs / outputs of the memory unit will be disconnected from The first bus’s information5 address bus 26, and the outputs of the first 14, third 16, and fifth 18 elements will have a low alarm signal regardless of the voltage levels at the inputs of read 22, write 23, and the output of synchronization of the exchange of memory block 1, low signal ur Aries also enters the second input of the first element AND OR NOT 16. After the time of decoding the address at the output of the first delay element 18 by 5 Vits is low, the voltage level is low (because its input has a low voltage level from the output of the first element AND-OR-NO 16) which arrives at the fourth input of the element AND-OR-NOT 16. Therefore, at the output

0 element AND-OR-NOT 16 a high voltage signal appears. High voltage level. The high voltage level at the output of the AND-OR-NOT 16 element is maintained until the next

5 of the synchronization signal of the exchange on line 28. After the high level signal is set at the output of the AND-OR-NOT element 16, the device is ready to receive the synchronization signal from the second line.

If the address in register 4 coincides with the address of memory block 1, after a certain time after the low level signal appears at the output of the AND-OR-HE element 16, the low-level signal at the output of the decoder 7 and the output of the OR-HE element 20 through Wits high signal, High signal from the output of the element OR NOT 20 is fed to the first input of the first element OR OR NOT 16, providing at its output a logical zero signal, regardless of the signal level at the fourth input (i.e. at the output of the first element delays 18). In this case, the low level signal will be present at the output of the AND-OR-NOT element 16 until the end of the synchronization signal on line 28. The high level signal from the output of the OR-NOT element 20 also goes to the enable inputs of the first switch of the highway 2, the first 14, the third 16 and an additional 18 elements I. In this case, the information inputs of the outputs of memory block 1 will be connected to the information bus and address bus 26 of the first highway, read signals, and records from the first highway, received via lines 22 and 23 pass into memory block 1, and the output signal the synchronization of the memory block 1 enters the answer line 30 of the first line. At the end of the cycle of accessing memory block 1, the high level of the synchronization signal on line 28 is removed. At the same time, the low voltage level is set at the output of the seventh element And 14, and the high voltage level is set at the output of the first AND 16 AND element 16 which passes to the output of the element OR 20. As a result, the information inputs, outputs, write, read and sync output of the memory unit are disconnected from the first line. The device is ready for the next cycle of accessing memory block 1.

The operation of the device for the occurrence of an exchange synchronization signal from the second line on line 29, in the absence of a unit level on the exchange synchronization line 28, will occur similarly with the difference that AND-OR-NOT elements 17, I19, 11, 13 will be involved and 15, the elements OR NOT 21 and the delay element 19.

Consider the case of the occurrence of an exchange synchronization signal on one of the trunks, if an exchange synchronization signal is present on another trunk.

If an exchange synchronization signal arrives on line 28, if there is an exchange synchronization signal on line 29, then

the moment when the output of the second element AND-OR-NOT 17 of the zero voltage level is present, the signal from line 28 will be blocked on the seventh element 14. After

setting the output of the second element of the signal high level of operation of the device will occur as for the case of the absence of the synchronization signal on line 29. If the synchronization signal arrives

0 exchange to line 29, if there is an exchange synchronization signal on line 28, then until the first element AND-OR-NOT 16 is at the output of zero level, the signal voltage from lines 29 will be blocked on the seventh element 15.

For the case of simultaneous occurrence of exchange synchronization signals on lines 28 and 29, elements AND 14 and elements AND-OR 16 and 17 represent a trigger, for which the zero level can appear only at the output of one of the elements AND-OR-NOT 16 and 17. A low level signal from the output of one element will set a high level signal at the output of another element. Further operation of the device is similar as in the case of the emergence of an exchange synchronization signal on one of the trunks in the presence of this signal on another trunk.

0

Claims (1)

Claims An apparatus for interconnecting two trunks, comprising a memory block, commutators of the trunks, first and second 5 address registers, a switch block consisting of a zone decoder, from the first to the sixth elements AND, the information inputs of the first and second address registers being connected respectively to the first 0 groups of information inputs-outputs of the first and second commutators of highways with information address buses of the first and second highways, a group of information inputs-outputs of the block 5 is connected to the second groups of information inputs of the first and second commutators of the lines, characterized in that, for the purpose of simplification, the first and second elements AND-OR-NOT are inserted into the device, 0 the first and second delay elements, the first and second OR elements are NOT, the outputs of the first and second address registers are connected to the group of address inputs of the memory block and the information inputs of the 5th zone encoder, the outputs of the first and second elements And are connected to the read input of the memory block , and the first inputs of the first and second elements I are with the read buses of the first and second lines and the first inputs of the exchange direction of the first and second switches of the lines, the outputs of the third and fourth elements I are connected to the write input of the memory unit, and the first inputs of the third and fourth elements I, with the recording buses of the first and second lines and the second inputs of the direction of the first and second commutators, synchronize the output of the memory unit connected to the first inputs of the fifth and sixth elements I, the outputs of which are connected to the response tires of the first and second highways, the output of the zone decoder is connected to the first inputs of the first and second elements OR NOT, the second input of the first element OR NOT is connected to the output of the first element AND-OR-NOT, the first input of the seventh element AND, the input of the permission to issue information of the first register of the address and the input of the first delay element, and the output of the first element OR — is NOT connected to the first input of the first AND-OR-NOT element, the second inputs of the first, third w fifth AND elements and to the enabling input of the first switch rgtey, the second input of the second element OR is NOT connected to the output of the second AND-OR-NOT element, the first input of the eighth AND element, the permission input for issuing information of the second address register and the second delay element input, and the output of the second OR element is NOT connected to the first input of the second AND-OR element NOT to the second inputs of the second, fourth and sixth elements AND to the enabling input the second switch of the lines, the second and third inputs of the first element AND-OR-NOT are combined and connected to the output of the eighth element AND, the second and third inputs of the second element AND-OR-NOT are combined and connected to the output of the seventh element AND, the fourth inputs of the first and second elements AND-OR-NOT are connected to the outputs of the first and second delay elements, respectively, the second input of the eighth element AND is connected to the synchronous input of the first address register and the exchange control bus of the first highway, the second input of the seventh element And it is connected to the synchronous input of the second address register and the control bus the exchange of the second highway. And I - jj ---- uJ: