SU1755285A1 - Device for accessing memory units - Google Patents

Abstract

The invention relates to the digital processing of information, in particular, to blocks (modules) of computing systems containing a network of backbones with blocks. The purpose of the invention is to increase the reliability of the device by eliminating unauthorized sampling. The device contains the main identification node 1, similar to it in the structure of 1 Nm of knots, circuits 2 and 3 of comparison, register 4, block 5 of setting a constant address code, trigger 6. 1 Il.

Description

The invention relates to digital information processing, in particular, to blocks (modules) of backbone computing systems of aircraft containing a network of backbones with blocks. A device for selecting memory blocks (device) can be used, for example, in crystals of an LSI, VLSI memory of an aircraft, a microcomputer, and it allows switching the operation of a memory of a computer.

The node identifying the address of the trunk unit (node) is known, which contains the decoder, the inputs of which are connected to the older bits of the address buses of the highway, and each output of the decoder is connected to the input input of one of the LSI units.

The disadvantages of the node are the quiet one (by setting up the sliding redundancy of the node sections; the inability to switch sections of the node; the presence of additional address line inputs missing in the LSI.

The closest in technical essence to the present invention is the node identifying the address of the trunk module, allowing the module to change the sample code of all bits of the bus of the address of the trunk.

Disadvantages of the node - there is no possibility to perform the setting of the sliding backup of the node sections; inability to switch node sections; increase the number of external contacts of the node address.

The purpose of the invention is to increase the reliability of the device by eliminating unauthorized sampling.

In this case, it is possible to change the sampling code of each section of the node, it is possible to switch sections of the node, almost halving the number of external contacts of the node address.

The goal is achieved by introducing into the device a group of M address identification nodes (M is the number of selectable memory blocks) and a trigger; I will address the address and information inputs of the device, the resolution entries for the address of all address identification nodes are connected to the device resolution enable input, and the information input is connected to the output of the main node of the address ID identifier katsii address is output sampling K-th block of memory devices.

The drawing shows a functional diagram of a device for selecting memory blocks.

The device contains the main node 1 address identification, similar to it in structure, nodes 1i - 1M, schemes 2 and 3 of comparison, register A, block 5 of the task of constant

address code, trigger b, device access permission input 7, device operation permission input B, device address input 9, device address high-order bits, information

device input 11, high bits of the information input 12 of the device, output 13 of the main identification node connected to the trigger information input, 13 NNM sample outputs

the corresponding memory blocks, the input 14 of the logical unit, the inputs 14Н4М permitting the reading of the corresponding address identification nodes.

The device works as follows

To write the tuning address n register 4 of one of the identification nodes of the address of the pertlilleo, the tuning addresses are given by the inputs 11 and 12, the address code from block 5 and the address

through inputs 9 and 10. The tuning address in register 4 is entered when a single signal is received from input 8.

After that, the trigger 6 is reset to O. On a single signal from input 7 and a zero signal from output 13 with mismatched codes of signals from the outputs of register 4 and input 9, the operation of 1NM nodes is prohibited. Tuning of registers 4 nodes 11-1 m is done analogously. Installation is performed

to the trigger unit 6, If the signal codes from input 9 and register 4 output with a single signal from input 7 coincide, the operation of nodes 1Nm is allowed.

The use of this device eliminates unauthorized selection of memory blocks.

Claims (1)

The invention of the device for selecting memory blocks, containing the primary address identification node, the first and second address inputs of which are connected respectively to the address and information inputs of the device, characterized in that, In order to increase the reliability of the device for eliminating unauthorized sampling, a group of M address identification nodes (M is the number of selectable memory blocks) and a trigger are entered into it; The first and second address inputs of the K-th identification of the group address (K 1, M) are connected respectively to the senior bits of the address and information inputs of the device; to the input of the resolution of the work of the device memory devices, and the information va, the read enable inputs of the Kth host are connected to the output of the primary node identification group addresses are connected; address identification, output K-ro nodes to the trigger output, the sync input of which address identification is the output It is an input of access to block-5 for the selection of the K-ro block of the device.