SU1208558A1 - Interface - Google Patents

Description

pa is the second input of the block, the second input of the trigger is connected to the first input of the parity check node, the third input of the synchronization node, the second input of the bus driver, and is the third input of the block, the inputs of the bus driver group are connected to the parity check and register group and are the inputs of the block group, the first and second outputs of the synchronization node and the register output are respectively the fourth, second and third outputs of the block, the third trigger input is connected to the first input of the synchronization node and is with the first input of the block, the output of the parity check node is connected to the second input of the synchronization node and is the first output of the block, the inputs-outputs of the group of the parity check node are the inputs-outputs of the first group of the block, the trigger output is connected to the first input of the bus driver, the third synchronization input and the first input of the register, the second input of which is connected to the fifth input of the synchronization node and is; the fourth entry block.

3. The device according to claim 1, characterized in that the synchronization unit comprises first and second triggers, a delay element, first and second one-shot first and second OR elements, a bus driver, first, second, third, fourth and fifth elements, And the first inputs of the fourth and fifth elements of AND are the first input of the block, the second input of the fourth element. And is the second input of the block, the first and second inputs of the second element OR are respectively the fourth and fifth inputs of 208538

ka, the third input of the first trigger is connected to the third input of the first element I and, together with the inputs-outputs of the first group of the bus driver, are the inputs-outputs of the second group of the unit, the first input of the first one-oscillator, the outputs of the first element And and the inputs of the second group of the bus driver The inputs-outputs of the first group of the block, the output of the fourth element I are connected to the second input of the first element I, the second input of the second trigger ,. third inlet- the house of the first trigger, the second input of the first one-shot and the first input of the second one-shot, the first output of which is connected to the first input of the second trigger, the output of which is connected to the first inputs of the first OR element, first and third elements AND, and the third output of the block, the first output of the first trigger connected to the input of the delay element, the output of which is connected to the second input of the second one-shot, the second output of which is connected to the second input of the third element AND, the output of which is the fifth output of the block, The first output of the first one-shot is connected to the first input of the first trigger, the second output of which is connected to the second inputs of the second element AND to the first OR element and is the second output of the block, the second output of the first one-vibration is connected to the first input of the second element AND whose output is the fourth output block, the output of the first element OR is the first output of the block, the output of the second element OR is connected to the second input of the fifth element AND, the output of which is connected to the input of the bus driver.

The invention relates to the field of computer technology, is intended to control the exchange of information in a computer system and can be used for pairing in process control systems, automatic lines, robot-technical complexes.

The aim of the invention is to improve the speed of the device.

FIG. a block diagram of the device is presented; in fig. 2 - block diagram block diagram.

The interface device contains inputs-outputs 1 of the address-data inputs-outputs 2 of the control, blocks 3 input-output consisting of a bus driver 4, a register 5, a synchronization node 6, a parity node 7, a trigger 8, a multiplexer 9, a register 10, the decoder 11, block 12 synchronization, the first 13 and second 14 bus drivers inputs and outputs 15-19 blocks. The synchronization unit 12 contains the first - fifth elements AND 20-24, the first 25 and second 26 one-shot, the first 27 and second 28 triggers, the delay element 29, the first 30 and second 31 OR elements, and the bus driver 32.

The interface device operates as follows.

The exchange of information between the control processor (not shown) and the I / O units 3 is carried out in asynchronous mode. The communication cycle begins with the output of addresses.

The processor generates an address output signal and an I / O signal indicating that information is being exchanged between the processor and the I / O unit 3, and the input word I (data address) is an address word that is through the second. bus driver 13 is fed to the input of the multiplexer: 9.

The Address Output signal is fed to the input of element 23 and block 12, an I / O signal is applied to its second input. The output of this element removes the blocking of element 20 I, single-shot 25 and 26, and flip-flops 27 and 28. Single-shot 25 is triggered by a release synchronization signal, which tracks the address word generated by the processor.

At the output of the one-shot 25, a pulse appears, which by its leading edge sets trigger 27 to state 1. The signal from the direct output of trigger 27 enters the inputs of element 30 OR, element 21 and the address word is already present at the input of multiplexer 9 . On signal Number of multiplex 08558

The sor 9 selects from the address word from the 6th to the 9th digit indicating the number of the selected block 3. The selected information is recorded in the register g 10 by a signal from the output of element 30 OR The same signal is fed to the input of the driver 13 which translates into a neutral high-impedance state, thereby unblocking the inputs-outputs 1 (data-addresses), and to the input of the decoder 11, allowing decryption of information recorded in register 10, From the output

15 of the decoder 1 1 signal, the drying information about the number of the selected block 3, through the bus fmr 14 arrives at the selected block 3 of the I / O. I / O blocks 3 are connected in such a way that each block 3 having a specific number from O to 15 is connected to the corresponding inputs / outputs having the same number. This signal

25 opened at the trigger input 15, and

its other input receives a signal. The block number from the input-outputs 2 (control), to which this signal comes from the output of the element 21, and its delay relative to the signal received at the input of the trigger 15, carrying information about the block number, is determined by the duration of the blocking pulse. input element

35 21 with the output of the one-shot 25.

Thus, the presence of the connection of these two signals in trigger I5 sets it to state 1, and a signal to its output leads the bus driver out of the disconnected state, thereby giving permission to exchange information between the processor and the selected input / output unit 3.

5 Next, the signal from the output of the trigger 15 connects to the input of the synchronization node 6, removing the lock from it. At the other input of the synchronization node 6 there is a signal

50 Block number from I / O 2 (control). At the output of node 6, a receive synchronization signal is generated, indicating that the selected block is connected. Trigger

55 27 returns to the initial state. In this case, the lock is removed from the bus driver 13, the address word is fed to the input of the multiplex 30

Litter 9, element 21 I is blocked, the signal of the block number is removed, and consequently, the sync - down reception signal is also removed. The selection of the block is made.

The signal from the output of the trigger 27 through the delay element 29 triggers the one-shot 26, the pulse at the output of which by its leading edge sets the trigger 28 to the single state. Next, the signal from the output of the trigger 28 is fed to the inputs of the elements 30 OR, 22 AND, 20 AND and to the input of the multiplexer 9, which selects from the address word 3 to 5, indicating the number of the module to be selected. In register 10, the selected information is recorded by a signal from element 30 OR.

As in the block number selection cycle, this signal blocks the bus driver 13 and enables decryption of information recorded in the register U, C of the output of the decoder 11 through the bus driver 14 and the signal with the decoded module number enters the selected bus input unit 3 on the bus driver 4. Next the signal arrives at the input of register 5, at another input of which the signal is already present. The module number from the output of element 22 I. Moreover, the signal delay The number of the module received at the input of register 5 is relative to the signal at its other input defined a duration of a blocking pulse supplied to the input element 22 and output from the monostable multivibrator 26. simulta- m €; continuously the same number modulation signal supplied to the input node and six synchronization. At the output of the node 6 is formed

0

five

0

five

Receive sync signal indicating that the module is selected. This signal is fed to block 12 at the input of element 20 I, which receives a receive synchronization signal, from the broadcasting processor that the address is complete. The processor removes the address word and signals. Address issuance and Issue synchronization. Signal Dismissing Address issuance blocks single vibrators 25 and 26, triggers 27 and 28, and element 20 I. This removes the signal. Module synchronization number is received and the bus driver 13 is blocked.

After the end of the cycle, the address is followed by the cycle of writing information to the selected module or the cycle of reading information from the selected module.

in the recording cycle, the information is accompanied by a parity check issued by the processor. Through the bus driver 4, information is fed to the input of the parity check node 7, it is checked for parity, compared with the control. In this case, in case of NIN mismatch, node 7 generates a Failure signal, which blocks node 6 of synchronization.

In the read cycle, the information supplied by the selected module to the processor is supplemented by a node 7 with a parity check digit.

Thus, the present invention provides a significant increase in speed due to the fact that the data-address bus is always under constant load of only one selected I / O unit.

Naal data.-addresses 1

Nana / 1 ynpod / feHL / ff 2

15

17

f

/ 7

) /

/ ffiody / fiffffo a- i / o a Figure 1

one

12

/ J

I

fff

PCT

Y j

Vlon - Soooa -ffA / ffffffa

l {M (//) type / hepsor 3 AND piltiplensoruE

H register 10, dashid 11,

ujvHHOfiy ipopfiu- rovate / gyu / J

"M

 register 10, shida rator 11,

ujvHHOfiy ipopfiu- rovate / gyu / J

(Rig.y.

Compiled by N.Maksimov Editor, L.Veselovska Tekhred T.TulikKorrektor S.Shekmar

Order 289/58 Circulation 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PPP Patent, Uzhgorod, st. Project, 4

Claims (3)

1. The device for interfacing, containing input-output blocks, group inputs, first, second and third outputs, the first group of inputs and outputs and the first input of which are group inputs, first, second and third outputs, first group inputs and outputs, and first device input, characterized in that, in order to improve the speed of the device, a multiplexer, a register, a decoder, a synchronization unit, first and second bus drivers, the inputs and outputs of the first group of which are connected to the inputs and outputs of the second group, are introduced into it I / O blocks, the second inputs of which are connected to the corresponding bits of the inputs and outputs of the first group of the second bus driver, the inputs and outputs of the second group of which are connected to the inputs and outputs of the first group of the first bus driver, the inputs and outputs of the second group of which are inputs of the outputs of the second group of devices , the corresponding bits of the inputs and outputs of the second group of the second bus driver are respectively connected to the first input of the multiplexer and the output of the decoder, the first input of which is connected to the first bus driver, the first input of the register and the first output of the synchronization unit, the second and third outputs of which are connected respectively to the second and third inputs of the multiplexer, the output of which is connected to the second input of the register, the output of which is connected to the second input of the decoder, the first and second inputs, inputs - the outputs of the first group, the fourth and fifth outputs of the synchronization unit are, respectively, the second and third inputs, inputs and outputs of the third group, the fourth and fifth outputs of the device, the first and second inputs torogo bus driver connected to first and second inputs of the synchronization unit, the inputs and outputs of the second group are connected to vhodamivyhodami third group of input-output units, the third and fourth inputs and an input-output of which is respectively the fourth and fifth inputs and an input-output device. 2. The device according to π. 1, wherein the input-output unit contains a trigger, a register, a synchronization unit, a parity unit, a bus driver, the inputs and outputs of the first group of which are inputs and outputs of the second group of the unit, the first input of the trigger SU „„ 1208558 ra is the second input of the block, the second input of the trigger is connected, with the first input of the parity node, the third input of the synchronization node, the second input of the bus driver and is the third input of the block, the inputs of the group of the bus driver are connected to the inputs of the group of the parity node register and are the inputs of the block group, the first and second outputs of the synchronization node and the output of the register are respectively the fourth, second and third outputs of the block, the third input of the trigger is connected to the first input of the synchronization node and i is the first input of the block, the output of the parity node is connected to the second input of the node, synchronization is the first output of the block, the inputs and outputs of the group of the parity node are the inputs and outputs of the first group of the block, the trigger output is connected to the first input of the bus driver, the third synchronization input and the first input of the register, the second input of which is connected to the fifth input of the synchronization node and is the fourth input of the block. 3. The device according to π. 1, different. the fact that the synchronization unit contains the first and second triggers, a delay element, the first and second one-shots, the first and second elements OR, bus driver, the first, second, third, fourth and fifth elements And the first inputs of the fourth and fifth elements And are the first input block, the second input of the fourth element. And is the second input of the block, the first and second inputs of the second element OR are the fourth and fifth inputs of the block, the third input of the first trigger is connected to the third input of the first element And and together with the outputs of the first group of the bus driver are the inputs and outputs of the second group of the block, the first input of the first one-shot, the outputs of the first element And the inputs and outputs of the second group of the bus driver are the inputs and outputs of the first group of the block, the output of the fourth element And is connected to the second input the first element And, the second input of the second trigger, the third input of the first trigger, the second input of the first one-shot and the first input of the second one-shot, the first output of which is connected to the first input of the second trigger, the output One of which is connected to the first inputs of the first OR element, the first and third AND elements and is the third output of the block, the first output of the first trigger is connected to the input of the delay element, the output of which is connected to the second input of the second one-shot, the second output of which is connected to the second input of the third element And, whose output is the fifth output of the block, the first output of the first one-shot is connected to the first input of the first trigger, the second output of which is connected to the second inputs of the second element And and the first element OR is the second output of the block, the second output of the first one-shot is connected to the first input of the second AND element, the output of which is the fourth output of the block, the output of the first OR element is the first output of the block, the output of the second OR element is connected to the second input of the fifth AND element, the output of which is connected to the input bus former.