SU1702383A1 - Processor-multibank memory interface - Google Patents

Abstract

The invention relates to computing, can be used to increase the amount of memory when building digital systems based on mini (micro) computers. The purpose of the invention is to expand the functionality by using a tunable multi-block memory. This is achieved in that the device contains a control block 1, a register 2 of the array number, a memory block 3.1-З.Н, an address register 4, a memory bank connection block 5, and a comparison node 6. 2 Il.

Description

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WITH

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The invention relates to computing, can be used to increase the amount of memory when building digital systems based on mini (micro) computers.

The purpose of the invention is to enhance the functionality of the device by using a tunable multi-block memory.

FIG. 1 shows a diagram of the device; Fig. 2 is a schematic of the control unit w of the control unit.

The device contains a control unit 1, register 2 numbers of the array, blocks 3.1. W. memory, register 4 addresses, blocks 5 connecting memory banks, groups of comparison nodes 6. Each memory block 3 contains M memory banks 7 Each of the memory bank connection blocks 5 contains a control node 8 and a register 9. The control block 1, as well as each of the control nodes 8, contains channel transceivers 10, an address decoder 11, a trigger 12, a control decoder 13, an input

14 sync, first and second inputs

15 and 16 modes.

The gadget works as follows.

Each of the H blocks of 3 memory contains M banks of 7 memory and has a maximum capacity corresponding to the format of the address word of the processor, not more than 2N words, where N is the format of the address word of the processor. Each of the memory banks 7 has a read entry entry through which the bank is either allowed or prohibited to work with a common interprocessor exchange bus, for example, a common bus. Each memory bank 7 is managed autonomously. It is possible to connect any set of banks of 7 memory from the total set of NHM banks of 7 multi-block memory. The connection of any bank is made by software and occurs as follows: the corresponding physical bank 7 is assigned its number in the address space of the processor by means of the corresponding register 9 (in one cycle of the processor accessing the corresponding register 9); the corresponding physical bank 7 is connected to the processor's address space by register 2 of the array number (during one cycle of the processor's access to it).

The functional purpose of register bits 2 of the array number is as follows: connect (disable) the physical memory bank 7 to the processor address space. The register form 2 of the array number (respectively, their number s device) is determined by the number of banks

7 multi-block memory, namely -N. where P is the required number of register bits 2 (for P N the number of registers 2 is more than one).

The functional purpose of registers 9 is the following: set the corresponding physical bank 7 bank number of the address space of the processor. The number of register bits 9 needed to set the number is determined by the selected bank size 7. If the full format of the address word of the processor allows connecting a set of banks, then the required number of bits is equal.

To connect a specific set of banks of 7 memory to the address space of the processor, it will be necessary to set the numbers of the address space to the corresponding physical banks 7 by referring to the corresponding registers 9 and connect the corresponding banks 7 by calling register 2 to the array number,

When the system is initialized, after passing through the installation signal arrays, register 2 of the array number and registers 9 are set to the zero state. Therefore, in the initial state, all banks 7 are disconnected. After initialization, the required memory structure is programmed by several cycles of writing the bank numbers to the corresponding registers 9 and connecting bits of the selected banks 7 to the register 2 array numbers. The bank number from the register 9 corresponding to the bank 7 is transferred to the first information inputs of the comparison nodes 6 corresponding to the bank 7, the synchronization input of the comparison node 6 is received from the register 2 of the array number. In register 4, the addresses are remembered by the sync signal 14 of the highest address addresses defining the bank number. From the outputs of the register 4, the bit addresses go to the second information inputs of the comparison nodes 6. When the codes on the first and second information inputs of node 6 coincide, a work enable signal is generated to the corresponding bank 7 from its output. The work enable signal remains until the end of the exchange cycle (write and read) with the memory bank 7 and is removed after the end of the cycle after the signal is removed. 14 sync.

The change, and connections to the backbone of the combination of memory banks 7, is made by changing the codes at the outputs of registers 9 and register 2 of the array number corresponding to the inclusion of the required memory banks 7. Writing codes into the specified registers is done programmatically using separate transfer commands. The control of the assigned numbers to the banks of the memory 7 is carried out when reading the corresponding registers 9 through the control nodes 8. The control of the connected memory bank combination is carried out while reading the register 2 through the control unit 1.

Control unit 1 is intended for. register register 2 array numbers with the exchange backbone. The control unit 8 is designed to interface the corresponding register 9 with the exchange highway, performed similarly to the control unit 1. The execution of block 1 of control nodes 8 is determined by the type and structure of the line, so their specific implementation for different computers may be different.

When the processor addresses, the address along the lines of the trunk data address is fed through the channel transceivers 10 to the inputs of the decoder 11. If the address code matches the specified address, the output of the decoder 11 generates a signal to select the register 2 of the array number, which is stored in the trigger 12 by the processor synchronization signal. If it is a write cycle, then the processor then removes the address, sets the data and generates a write signal, which is fed to input 15. A write signal at the output of the decoder 13 generates a write signal to the register 2 of the array number. The data code transmitted from the outputs of the initial transceivers 10 is transmitted by the processor to register 2. Register 2 of the array number is read by a signal received at input 16 from the processor. The output of the decoder 11 generates a read signal from register 2 of the array number, which is fed to the control input channel transceivers 10. Information from the outputs of register 2 via channel transceivers 10 enters the data address lines and then to the processor. Similarly, writing to registers 9 occurs and reading them.

Claims (2)

Invention Formula A processor interface with a multi-block memory containing the register of the array number, the control unit and the first to N-th memory blocks, H is the number of multi-block memory blocks, the device information input-output, read input, write input and synchronization input the devices are connected respectively to the information input-output, to the first mode input, to the second mode input and to the synchronization input of the control unit, the first and second outputs of which are connected respectively to the information input and to the synchronization input of the register The trail of the array number, the outputs of which are connected respectively to the inputs of the control unit group mode, the informational inputs-outputs from the first to the Nth first group of the device are connected respectively to the informational inputs-outputs of the memory blocks from the first to the Hth, different that, in order to expand 0 functionality, it contains N blocks of connection of the memory banks, N groups of comparison nodes and an address register, moreover, information inputs and outputs from the first to the Nth second group of the device 5 are connected respectively to the information inputs of the first through H th memory bank connection blocks, the write input and the device read input are connected to the first and second control inputs of all the bank memory connection blocks, respectively, the device sync input is connected to the synchronization inputs of all blocks connection of memory banks and address register, information input of which is connected to the address input of the device, outputs of a-th block of memory banks connection (where a 1, 2 ..., H) are connected respectively to the first information inputs of the nodes of the a-group, the output of the register The 0 address is connected to the second information inputs of all the comparison nodes of all groups, the input of the initial installation of the device is connected to the input of the installation in the O register of the array number and to the inputs of the initial installation of all the memory bank connection blocks. The C th input of the a th group (where c 1,2 ..., M, M is the number of memory banks in the memory block) of the register of the array number is connected to the synchronization input of the C th reference node a 0 group, the output of which is connected to the input of the read-write C-th memory bank of the a-th memory block, with each block connecting the memory banks containing a control node and a register, and in each block connecting the memory banks the first and second the control inputs, the synchronization input and the information input / output memory bank switching unit are connected respectively to the first and second mode inputs, to the synchronization input and to the information input / output of the control unit, the first and second outputs of which are connected respectively to the information the main input and to the register synchronization input, the setting input to the About 5 is connected to the input of the initial installation of the memory bank connection unit, the outputs of the register are connected respectively to the inputs of the group mode of the control unit and respectively to the outputs of the memory bank connection unit. ishelgay d