RU1837306C - Computer system interface device - Google Patents

Abstract

 Subtitle 80385, cl, G 06 F 13/28, 1990. INTERFACE DEVICE The invention relates to interfacing devices and can be used to interface two data processing units. The aim of the invention is to increase the speed of the device by eliminating many instructions for applying the operation code and analyzing the contents of the instruction register. The device contains two communication units, two operation code generation units, an AND element and a NOT element, each communication unit comprising a firmware control unit, an exchange unit, a comparison unit, an AND element and two OR elements, each exchange unit contains two decoders, a register instructions, data register, address counter, sixteen groups of AND elements, two NOT elements, nine AND elements, three AND elements, and NOT elements, each operation code generating unit contains a control register, a delay element, an OR element , d and I. bus driver element in each communication unit introduced trigger in each exchange unit - an AND, an OR-Nyo, three groups of AND gates and word counter. 6 ill. cl

Description

The invention relates to computing devices, may be used to interface two data processing devices.

An object of the invention is to increase the device performance by eliminating a plurality of instructions for entering the operation code and analyzing the contents of the instruction register.

Figure 1 shows the structural diagram of the device; Fig. 2 is a block diagram of a communication unit; Fig. 3 is a structural diagram of a microprogram control node; figure 4 is a structural diagram of a node exchange; Fig. b is a block diagram of an operation code generating unit; Fig. 6 - temporal relationships during the exchange of arrays of informMZTS / 1I.

Figure 1 - 1 and 2 indicate communication units;

3, 4 are blocks for generating an operation code;

5-element And (for example, K555LI1 or similar);

6-element NOT (for example K555LN1 or similar);

7, 8 - command inputs and outputs of communication units;

9, 10 - first information inputs and outputs of communication units;

11,12 address inputs of communication units;

13, 14 - sync signal outputs of communication units;

15, 16 are groups of outputs of the operation code of communication blocks;

17, 18 - communication blocking outputs;

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with

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19, 20 - first control inputs of communication units;

21, 22 - outputs of the input communication blocks:

23, 24 - outputs of the output of communication units;

25. 26 - outputs of the interface of the communication blocks;

27, 28 - outputs of equality of blocks. Communication;

29, 30 - second information inputs / outputs of communication units;

31.32 first and second control inputs of the second address of the communication units;

33, 34 - the first V) second control inputs to the first address of the communication units;

35, 36 - increment outputs of communication blocks;

37, 38 - recording inputs of communication blocks;

39, 40 - communication block mode outputs;

41 - second control input of communication units;

42 - third control input of communication units;

43, 44 are groups of outputs of a control code of communication units.

Figure 2 - numeral 45 denotes the firmware control unit;

46- exchange node;

47 - the first element OR (for example, K555LL1 or similar);

48-element And;

49- second element OR;

50 is a comparison unit (implemented on elements such as K530SP1 or the like);

51- group of code inputs of the node is exchanged;

52 - group of code outputs of the exchange node;

53 - control output of the firmware control unit;

54 - input increment node exchange;

55 - output increment node exchange;

56 is a first read input of an exchange node;

57 - output end of the cycle of the exchange node;

58-trigger (for example, K555TM2 or similar);

59 - input end of the exchange of the firmware control unit);

60 - exit end of the exchange node exchange;

61 - reset output of the firmware control node.

In FIG. 62, buffers are indicated by 62, 63;

64-multiplexer (for example, K555KP1 or similar);

65- pulse generator (implemented for example on K555TL2 or similar);

66 - register of the address of microcommands (for example, K589IR12 or similar);

67- read-only memory (e.g. K556PT5 or similar).

In figure 4, numeral 68 denotes an eighteenth group of AND elements (e.g., 559 IP1 or similar with the 3rd state at the output);

69 - word counter (for example K555IE7 or similar); ,,,

70, 71 - the first and second elements OR;

72 - the first element And;

73, 74 - decoders (for example, K555IDZ or similar):

75 - the second element And;

76 - the first element OR-NOT (for example, K555LE1 or similar);

77-79 - the third-fifth element OR; 80 - the third element And; 81, 82 - the sixth and seventh elements OR;

83-85 - the fourth to sixth elements And;

86- eighth element OR;

87 - the seventh element And;

88- second element OR NOT;

89, 90 - the first and second group of elements And;

91 - the third element OR-NOT;

 - third-sixth group of elements And;

96, 97 - the eighth and ninth element of And;

98 - address counter;

99-data register;

100- register of commands;

101- ninth element OR;

102- element is NOT;

103-112 - the seventh to sixteenth group of elements And;

113th element AND;

114- element is NOT;

115 - the eleventh element And;

116- fourth element OR-NOT; 117- seventeenth group of elements And;

118- maidens of the thirteenth group of elements And;

119- group of inputs of the address of the vector. 5, the numeral 120 denotes an OR element;

121-bus driver;

122 - delay element (for example, implemented on the AND and NOT elements of the K555 series or similar);

123- control register; 124,125 - elements of I.

6, TA1 denotes the time the cell address was entered into the counter of the prototype address;

TD1 - the time of entering data into the data register of the prototype;

TK1 - time of entering the operation code into the register of commands and prototype states;

TAK1 is the time of analysis of the contents of the prototype instruction register (for equality 0) to determine the end of the cycle;

TA2 is the time the cell address was entered into the address counter of the claimed device;

TD2. - the time of entering data into the data register of the claimed device;

TK2 - time of entering the operation code in the register of commands and conditions of the claimed device;

TC2 is the time of entering the code of the number of transmitted words into the word counter of the claimed device;

A device for interfacing electronic computers, comprising two communication units 1 and 2, two operation code generating units 3 and 4, an AND element 5 and an HE element 6, each communication unit 1 (2) comprising a microprogram control unit 45. exchange node 46, comparison node 50, trigger 58, AND element 48 and two OR elements 47 and 49, each exchange node 45 contains two decoders 73 and 74, register command 100, data register 99, counter 98 addresses, nineteen groups 89-95,103-112. 117, 68, 118 elements AND, two 102, 114 elements NOT. nine 70, 71, 77-79, 81, 82, 86, 101 elements OR, a counter of 69 words, eleven 72, 75, 80, 83-87, 96, 97, 113, 115 elements of And and four 76, 88,91,116 of an OR-NOT element, each operation code generating unit 3 (4) comprising a control register 123, a delay element 122, an OR element 120, two AND elements 124, 125 and a bus driver 121, the command input-output 7 and 8 of the first 1 and second 2 communication blocks form, respectively, the first and second groups of control inputs and outputs of the device, respectively, the groups of information inputs 11 and 12 of the first 1 and second 2 communication blocks are the first and second address inputs of the device, respectively, the first groups of information inputs and outputs 9 and 10 of the first 1 and second 2 communication blocks form the first and second groups of address data of the inputs and outputs of the device, respectively, the third outputs 13 and 14 of the first 3 and the second 4 units of formation of the operation ode are the first and second outputs of the device clock signals, respectively, the second groups of information inputs / outputs 29 of the first 1 communication unit are connected to the group of information inputs of the first 3 units of formation yes, operations to the third group of informational-input-outputs of the second 2 avi block, the second group of informational-input-outputs 30 of which are connected to the group of informational inputs of the second 4 block of generating the operation code, with the third group of informational input-outputs of the first 1 communication block , equality outputs 27 and 28, conclusions 23 and 24, inputs 21 and 22, interfaces 25 and 26 of the first 1 and second 2 communication blocks are connected respectively to information inputs of the output, input and interface of the first 3 and second 4 blocks of generating the operation code, respectively but, the first control input 19 of the first communication unit 1 is connected to the second output of the first 3 operation code generating unit and the reading input of the second 2 communication unit, the first control input 20 of which is connected to the second output of the second 4 operation code generating unit and to the input reading the first 1 communication unit, the first input of the recording 37 of which is connected to the first output of the second 4 unit of generating the operation code, the first input of writing 38 of the second 2 communication unit is connected to the first output of the first 3 unit of generating the operation code, outputs 39 and 40 of the first 1 modeand second 2 communication blocks are connected respectively to the first and second inputs of the element And 5 of the device, the output of which. connected to the input of element 6 of the device and to the second control inputs of the first 1 and second 2 communication blocks, the output of the second address 31 of the first 3 block of generating the operation code is connected to the first control input of the second address of the first 1 communication block and with the second control input of the second the address of the second communication unit 2, the first control input 33 of which the first address is connected to the output of the first address of the first operation code generating unit 3 and the second control input of the first address of the first communication unit 1, the first input of which record 37 is connected not connected to the second recording input of the second 2 communication unit, the first input of the recording 38 of which is connected to the second recording input of the first 1 communication unit, the first control input of which 34 is connected to the output of the first address of the second operation code generating unit 4 and to the second control input the first address of the second 2 communication unit, the read input 20 of which is connected to the second output of the second 4 unit of generating the operation code and to the first control input of the first 1 communication unit, the third control input of which is connected to the output 42 of the HE 6 element tim control input of the second communication unit 2, input prohibition 17 coupled to an output of the first 1 ban the communication unit, the ban entry 18 is connected to output prohibition

the second 2 communication blocks, the group of inputs of the operation code 15 of which is connected to the group of outputs of the operation code of the first 1 communication unit, the group of inputs of the code of operation 16 of which is connected to the group of outputs of the code of the first 2 communication block, the group of inputs of control code 43 of which is connected to the group of outputs of the control code of the first 1 communication unit, the group of inputs of the control code 44 of which is connected to the group of outputs of the control code of the second 2 communication unit, the input of increment 35 of which is connected to the output of the increment of the first 1 communication unit, input of the increment 36 is connected to the increment output of the second block 2, communication, and in each communication block 1 (2) command input-output 7 (8) of the firmware control unit 45 is respectively the command input-output of the communication unit, the group of input-output addresses / data 9 (10) of the exchange node 46 is the first group of information inputs and outputs of the communication unit, the first group of information inputs and outputs 29 (30) of the exchange node 46 is connected to the first group of inputs of the comparison unit 50 and is, respectively, the second group of information inputs -units of the communication unit, sec. and the group of inputs 11 (12) of the comparison node 50 is a group of information inputs of the communication unit, the first control input of which 19 (20) is connected to the second reading input of the exchange node 46 and to the first input of the second OR element 49, the second input of which is connected to the first control output 53 of the firmware control unit 45, the outputs of the interface 25 (26), output 23 (24) and input 21 (22) of which are respectively the outputs of the interface, output and input of the communication unit, the output of which is the sign of equality 27 (28) which is the equality output of the comparison node 50, the output of the second The contact block OR 49 is connected to the first reading input 56 of the exchange unit 46, the second group of information inputs / outputs 30 (29) of which is, respectively, the third group of information inputs / outputs of the communication unit, the second control input of which is the first control the input 41 of the exchange node, the second control input 44 of which is the third control input of the communication unit, the group of outputs of the operation code 52 of the exchange node 46 is connected to the group of inputs of the operation code of the node 45 of the firmware control, the group of code outputs 51 of which connected to the group of code inputs of the exchange node, the output of the increment code 55 of the exchange node 46 is connected to the first input of the AND element 48 of the communication unit, the second input of which is connected to the output of the first OR element 47, the second input of which is connected to the output of the increment 35 (36) of the firmware node control 45 and is the output of the increment of the communication unit, the input of the increment 36 (35) of which is the second input of the first element OR 47 of the communication unit, the output of the element And 48 of the communication unit is connected to the increment input 54 of the exchange unit 46;

0 the first control input of the second address 31 (32) of which is the first control input of the second address of the communication unit, the second control input of the first address 33 (34) of which is the second input

5 to control the first address of the exchange node, the second control input of the second address 32 (31) of the exchange node is the second control input of the second address of the communication unit, the first control input of the first address 33 (34) of which is the first control input of the first exchange node address; the first 37 (38) and second 38 (37) recording inputs of which are the first and second recording inputs of the communication unit, the input

5 18 (17) and the inhibit output 17 (18) of which are the input and output of the inhibit of the firmware control unit 45, the outputs of input 21 (22), output 23 (24), interface 25 (26) and mode 39 (40)

0 of which are respectively the input, output, interface and mode outputs of the communication unit 1 (2), the group of outputs of the control code 43 (44) of which is the group of outputs of the control code of node 45 of the micro5 program control, the second group of information inputs 16 (15) of the communication unit is the third group of information inputs of the exchange node, the first group of information inputs 44 (43) of which is

0 by the first group of information inputs of the communication unit, the read input 20 (19) of which is the third read input of the exchange node 46, the output of the end 60 of the exchange node 46 is connected to the trigger synchronization input

5 58, the output of which is connected to the control input of the end of the exchange 59 of the microprogram control unit 45, the reset output 61 of which is connected to the installation input in the trigger 58 of O, the output is the end of the loop 57 of the node

0 exchange 46 is connected to the same input of the microprogram control node 45, and in the exchange node “46 the outputs of the elements And the ninth 105, the tenth 106, the eleventh 107 and the fifteenth 111 groups and the first inputs

5 elements And the first 89, the third 92 and the sixth 95 groups form respectively a group of inputs / outputs of the address / data 9 (10) of the exchange node 46, the outputs of the elements And the eighth of the 104 group and the first inputs of the elements And the ninth of the 105 group respectively form the first group of information inputs - the outputs 29 (30) of the exchange node 46, the outputs of the elements And the twelfth 108, thirteenth 109 and fourteenth 110 groups and the first inputs of the elements And the second 90, fourth 93 and fifth fifth groups 94 form respectively the second group of information inputs and outputs 30 (29) of the node exchange, command register outputs 100 are connected respectively to the first inputs of the And elements of the fourteenth 110, the fifteenth 111 and the sixteenth 112 groups and form the first group of outputs of the operation code 15 (16) of the exchange unit 46, the groups of inputs 51 and 44 of the first 74 and second 73 decoders form respectively a group of code inputs and the third group of information inputs of the exchange node, the sync input of the command register 100 is connected to the output of the first 76 element OR NOT, the first input of which is connected to the first output of the first 74 decoder, the second inputs of the elements And the first 89 groups are connected to the first input Ohm of the second 88 OR-NOT element and with the second output of the first 74 decoder, the third output of which is connected to the second inputs of the AND elements of the fourth 93 group and with the first input of the third 9.1 OR-NOT element, the output of which is connected to the sync input of the data register 99, information the inputs of which are connected to the corresponding outputs of the AND elements of the third 92 and the fourth 93 groups, the second input of the third 91 elements OR is NOT connected to the first output of the second 73 decoder, the first inputs of the elements And the tenth group 106 are connected to the output of the address counter 98 and the input inputs of the corresponding elements of the thirteenth 109 group, the second inputs of which are connected to the fourth output of the first 74 decoder, the fifth output of which is connected to the first inputs of the elements of the twelfth 108 group, the second inputs of which are connected to the corresponding outputs of the data register 99 and the first inputs of the elements And the eleventh group 107, the second output of the second decoder 73 is connected to the second inputs of the elements And the eighth group 104, the sixth output of the first 74 decoder is connected to the second inputs of the elements And the fourteenth 110 gr pp, element output groups And the seventh 107 and sixteenth 112 groups form the second group of outputs of the operation code 52 of the exchange node 46, the first group of element inputs And the seventh group 103 is the group of control inputs 16 (15) of the exchange node, the information inputs of the instruction register 100 are connected with outputs of the corresponding elements And that of 94 and the sixth 95 groups, the first input

reading 56 of the exchange node 46 is the first input of the first OR element 70, the second input of which is connected to the first input of the first decoder 73, the output of the first OR element 70 is connected to the first input of the second decoder 73, the third output of which is connected to the first input of the third OR element 77, the second input of which is connected to the seventh output of the first 74 decoder, the eighth output of which is connected to the second inputs of the AND elements of the second 90 group and to the second input of the second 88 OR-NOT element, the output of which is connected to the synchronization input of the counter 98 address A processor whose information inputs are connected to the outputs of the corresponding AND elements of the first 89 and second 90 groups, the input of the increment 54 of the exchange unit 46 is the counting input of the address counter 98, the second inputs of the AND elements of the tenth group 106 are connected to the output of the fourth OR element 78, the first input which is connected to the fourth output of the second 73 decoder, the fifth output of which is connected to the first input of the sixth 81 OR element, the second input of which is connected to the ninth output of the first 74 decoder, the tenth output of which is connected to the second input of the 78th OR element, the output of the third 77th OR element is connected to the second inputs of the AND eleventh group 107 / the eleventh output of the first 74 decoder is connected to the third input of the third 91th OR-NOT element and to the first input of the fifth 79th OR element, the output of which is connected to the second inputs of AND elements of the third 92 group, the second input of the fifth 79 OR element is connected to the first output of the second 73 decoder, the sixth output of which is connected to the first input of the third 80 AND element, the output of which is connected to one of the outputs in the group of outputs 9 (10) CA / data of the exchange node 46, the second input of the third element 80 And is connected to one of the outputs of the second group of outputs of the operation code 52 of the exchange node 46, the second inputs of the elements And of the fifteenth 111 group are connected to the twelfth output of the first 74 decoder, the thirteenth output of which is connected to the second the inputs of the AND elements of the sixth 95 group and with the second input of the first 76 element OR NOT, the first input of which is connected to the second inputs of the AND elements of the fifth group 94, the second inputs of the elements AND the ninth 105 group are connected to the output of the tenth 113 element I. The first input to it is connected to the sixth output of the second decoder 73, the second input of the tenth element AND is connected to the output of the second element 114, the input of which is connected to the seventh input of the first decoder 74, the output of the eleventh element And 115 is connected to the installation input in the register of 100 commands, bit before the output of which is the command code 55 of the exchange unit 46, the seventh output of the second decoder 73 is connected to the second inputs of the AND elements of the seventh group 103 and to the input of the first element 102 NOT. the output of which is connected to the second inputs of the AND elements of the sixteenth 112 group, the second input of the first decoder 74 is connected to the output of the second OR element 71, the first and second inputs of which are connected respectively to the outputs of the first 72 and second 75 AND elements, the first input of the last is the second input 19 (20) reading the exchange node, the third input 20 (19) of reading which is the first input of the first 72 element And, the second input of which is the second control input 41 of the exchange node and connected to the first inputs of the fourth 83, sixth 85 and eighth 96 e And, the second input of the second 75 AND element is the first control input 42 of the exchange unit and is connected to the first inputs of the fifth 84, the seventh 87 and the ninth 96 AND elements, the first input of the record 38 (37) of the exchange unit is the second input of the fourth 83 AND elements, the output of which is connected to the first input of the seventh 82 OR element, whose output is connected to the third input of the first 74 decoder, the fourth input of which is connected to the output of the eighth OR element 86, the first and second inputs of which are connected respectively by the outputs of the sixth 85 and seventh 87 electric And, the second input of which is the first control input of the second address 31 (32) of the exchange node, the second control input of the second address 32 (31) of which is the second input of the sixth 85 AND element, the second input of the seventh OR 82 element is connected to the output of the fifth 84 AND element, the second input of which is the second input of the exchange unit record 37 (38), the first control input of the first address 34 (33) of which is the second input of the eighth AND element 96, the output of which is connected to the first input of the ninth 101 OR element, the second input of which is connected to the output d of the 97th AND element, the second input of which is the second control input to the first address 33 (34) of the exchange node, the output of the ninth 101th OR element is connected to the fifth input of the first 74 decoder, the output of the sixth 81th OR element is the output end of the node cycle 57 exchange and connected to the first input of the eleventh 115 element And, the second input of which is connected to the fourteenth

the output of the first 74 decoder, the fifteenth and sixteenth outputs of which are connected respectively to the first inputs of the fourth 116 elements OR, NOT elements of the seventeenth 117 group and the second inputs of the fourth 116 elements OR, NOT elements of the eighteenth 68 group, the outputs of which are connected to the outputs of the elements And the seventeenth 117 group and with the information inputs of the 69-word counter, the synchronization and decrement inputs of which are connected respectively to the output of the fourth 116 OR-NOT element and to the increment input

5 of the address counter 98, the transfer output of the counter of 69 words is the output of the end of the exchange node 60, the group of inputs of the installation of the vector 119 of which are the first inputs of the elements of the nineteenth 118 group, the second inputs of which are connected to the eighth output of the second 73 decoder, the output of the eleventh 115 the And element is connected to the reset input of the instruction register 110, and in the operation code generating unit 3 (4), the first information input of the control register 123 is the information input 27 (28) of the operation code generating unit, the output of the first 124 element a And connected to the first entrance

0 of the OR element 120 and is the first output 19 (20) of the operation code generating unit, the output of the second 125 And element is connected to the second input of the OR element 120 and is the second output 37 (38) of the block

5 of generating the operation code, the first inputs of the first 124 and second 125 AND elements are respectively the inputs of the input 21 (22) and the output 23 (24) of the operation code generating unit, the output of the delay element

0 122 is connected to the clock input of the control register 123, the installation input of which is connected to the input of the delay element 122 and is the input of the interface 25 (26) of the operation code generating unit, the group of information inputs of the control register 123 is a group of information inputs 29 (30) an operation code generating unit, the output of the second 31 (32) address and the output of the first 33 (34) address of which are 0 are respectively the first and second outputs of the control register 123, the third output of which is connected to the second inputs of the first 124 and second 125 AND elements generating operation code, exit

5, the OR element 120 is connected to the input of the bus driver 121, the output of which is the third output 13 (14) of the operation code generating unit.

The operation of the device is shown by the example of using it to pair two

COMPUTERS CONNECTING TOTAL BUS. In this case, the inputs / outputs 7, 8 are connected to the groups of control signals for the interface from the first and second computers. Inputs 9, 10 are supplied with groups of address / data signals from the first and second computers, respectively. The outputs 13 and 14 of the bus drivers 121 are connected to the SIP circuits of the computer1 and computer2 interface. At the initial moment, computers1 and computer2 in the groups of control signals for the interface generate RESET signals coming from one of the input / output circuits 7, 8 of the communication unit to the installation input in register 66 of the command address, providing the addresses of the first microcommand of the working microprogram on its outputs - frames and circuit 61 to the trigger reset input 58.

The device provides four types of information exchange between two computers:

- simultaneous bidirectional exchange of words (input and output commands), in which the information from the first

to the second computer and from the second to the first;

- simultaneous bidirectional exchange of arrays (ENTER + 1 and OUTPUT + 1 commands), in which data arrays are simultaneously transmitted from the first to the second computer and from the second to the first;

- alternate unidirectional exchange of words (commands V80D-0 and YOU-VOD-0),

in which information is alternately transmitted from one computer to another;

- alternate unidirectional exchange of arrays (input-0 + 1 and output-0-n commands). in which it carries out, with alternately transferring arrays of information from the first to the second computer and from the second

in the first.

The type of exchange is determined by the opcode written to the instruction register. The operation of the device when performing the first three types of exchange is discussed in detail in the description of the copyright certificate No. 1580385 of the prototype, so here we consider:

Unidirectional exchange of information. The operation of the device in this mode starts after information is written to the address and data registers and the command code of this mode with the bit set (for example).

In the initial state, the firmware 45 at the outputs 51, 43 (44), 39 (40). 17 (18), 35 (36) generates the following code:

39 (40) - high level signals;

17 (18) - low level signals;

43 (44) - signals supplied to the inputs of the decoder 74;

35 (36) - low level signals;

53 - low level signal;

51 - signals supplied to the inputs of the decoder 73.

The code at the input of the decoder 73 provides a signal at its second output that opens the AND elements of group 104. In this case, the signals from the inputs / outputs 9 (10) through the AND elements of the group 104 enter the group of inputs and outputs 29 (30).

Preparation of the interface device for operation and transmission of information is carried out by cycles of writing and reading information from registers 99, 100, counters 98 and 69 of the exchange node 46 of the second 2 and first 1 communication units.

The transfer of the first word of information from computer1 and computer2 at the initiative of computer1 includes:

a write cycle to the counter 98 of the address of the communication unit 46 of the communication unit 2 of the address of the first computer memory cell2 for the first element of the transmitted information array;

a write cycle to the 69-word counter of the exchange unit 46 of the communication unit 2 of the code for the number of words in the information array transmitted to the computer 1;

a write cycle in the register 100 of the exchange unit 46 of the communication unit 2 of the operation code ENTER-0 + 1.

Information transfer from computer2 and computer1 on the initiative of computer1 includes:

a write cycle to the counter 98 of the address of the communication unit 46 of the communication unit 2 of the address of the first computer memory cell2 for the first element of the transmitted information array;

a write cycle to the 69-word counter of the exchange node 46 of the communication unit 2 of the code for the number of words in the information array transmitted to the computer 1;

a write cycle in the register 100 of the exchange unit 46 of the communication unit 2 of the operation code ENTER-0 + 1;

a reading cycle from the register 99 of the exchange unit 46 of the communication unit 2 of the required information.

Computer-initiated information transfer is similar, but the registers and counters of the exchange unit 46 of the communication unit 1 are used. Information exchange operations between the register 99 and the computer memory 2 (1) are carried out in the direct memory access mode under the control of the MA of the corresponding node 45 of the communication unit 2 (1).

Consider a cycle of writing (reading) information in computer 1 to registers 99, 100, counters 98 and 69 of exchange unit 46 of communication unit 2. In accordance with the logic of the shared bus interface in the first phase of each exchange cycle along lines 9, the address-data is transferred to the address of the register or counter with which information will be exchanged. With a certain delay with respect to the address transfer, an SIA signal is issued for the group of inputs / outputs 7. The address signals are transmitted by the exchange node 46 of the communication unit 1 from the inputs / outputs 9 through the elements 104 to the outputs 29, the most significant bits go to the second inputs of the node 50, on the first inputs 11 of the comparison node 50, the group address code of the interface device assigned to it in the computer address space is supplied. When the address on the second inputs of the comparison node 50 matches the code of the first inputs, a signal of a logical unit is generated at its output to the information input DO of the control register 123 of the operation code generating unit 3. The low-order bits of the address, which determine the address of one of the registers 99, 100 or counters 98, 69, are fed to the group of inputs D1, D2 of the control register 123 from the highway 29. The CHA signal is transmitted through amplifiers 62 to the output 25 of the communication unit 1 and then to the input of the installation in O of the control register 123 and the input of the delay element 122 of the operation code generating unit 3. At the same time, the presence of the SIA signal at the installation input of register 123 ensures the inactive state of this input. From the output of the delay element 57, the SIA signal at the active level is fed to the input of the register register 123 and records the address code of one of the registers 99,100 or counters 98, 69 applied to the group of information inputs of the control register 123 and the signal from the output of the comparison node.

The second phase of the exchange cycle will be considered separately for the write and read operation of the address counter 98 and the registers 99, 100 (only the write operation is valid for the 69 word counter) of the exchange unit 46 of the communication unit 2.

The operation Write, The second phase of the exchange cycle begins with removing the address from lines 9, setting the recorded information on these lines, and receiving the signal EXIT from the computer interface 1 one of the circuits of the input-output group 7 through amplifiers 62 of the node 45 of the communication unit 1 to its output 23 and the output of the communication unit 1, to the input of the operation code generating unit 3 and the input of the second AND element 125 of the operation code generating unit 3. The recorded information is supplied through circuits 9 through the elements 104 of the exchange unit 46 of the communication unit 1 to the group of inputs / outputs 29 of the communication unit 1 and through

highway 29 then to a group of inputs / outputs 30 of the exchange unit 46 of the second communication unit 2. When the signals coincide at the two inputs of the AND element 125 (the OUTPUT signal and the information recorded from the element 50) of the operation code generating unit 3, the output of the And 125 element generates a signal supplied through the circuit 37 to the input of the And element 83 of the exchange unit 46 of the communication unit 2, which together with a group of address code signals from the outputs of the control register 123 supplied through circuits 31, 33 to the inputs of the elements 1/1 85, 96 of the exchange unit 46 of the communication unit 2, the decoder 74 outputs an information signal from the group of input-output groups 30 of the node 46 exchanges to one of the counters 98, 69 or p Registers 99, 100 of the exchange unit 46 of the communication unit 2.

The register or counter number is provided by a code supplied from the outputs of the control register 123 via circuits 31, 33 and a signal at input 39.

The signals from the outputs of the decoder 74 (recording signals) provide the opening of one of the groups of elements And 90, 68, 93, 94 and the flow of information to the counters 98, 69 or registers 99,100. At the same time, through the corresponding elements of OR-NOT 88, 116.91, 76, recording signals are fed to the recording inputs of one of the counters 98, 69 or registers 99, 100 and information is recorded in the selected block. The response signal (SIP) is generated in the computer interface by the OR element 120 and the bus driver 121, from the output of which the SIP signal is supplied to the computer interface. The computer, having received the SIP signal from the device, removes the SIGNAL signal, which leads to the removal of the recording signal generated by the decoder 74 and to the removal of the SIP signal generated by the OR element 120 and the bus driver 121.

The OUTPUT phase is completed by removing the SIA signal at the inputs / outputs 7 of the first communication unit 1. At the same time, an active level is set at the input of the installation in O of the control register 123 and the register 123 is reset to the zero state, providing a resolution signal at the input of the second AND 125 element. This causes a logical zero at the output of the And 125 element, which leads to the installation of the decoder 74 of the exchange node 46 of the communication unit 2 to the neutral state, while at its fourteenth output (at the input of the I.115 element) there is constantly a low level potential prohibiting the passage of signals to the reset input of the register 100 commands.

Operation Read. The second phase of the exchange cycle begins with removing the address from lines 9 and receiving a signal. Input from the computer interface through one of the circuits of the group of inputs / outputs 7 through amplifiers 62 of block 45 to output 21 and then to the input of the first element AND 124 of block 3 of generating the operation code. From the output of the AND element 124, a coincidence signal (the Input and recorded information signal from block 50) is input to the OR element 49 of the communication unit 1, to one of the inputs of the OR element 120, and via circuit 19 to the input of the And element 72 of the exchange unit 46 of the 2 communication unit zee. From the output of the OR element 49, the signal goes to the input 56 of the exchange unit 46 of the communication unit 1 and provides the output of the decoder 73 to generate a signal that opens, through the And 113 element, the And 104 elements. Next, the processes are similar to the RECORD operation, except that the code for the decoder 74 of the exchange unit 46 of the communication unit 1 is supplied together via circuits 19, 33, 31, and the decoder 74 of the exchange unit 46 of the communication unit 1 generates a read signal that opens the I 107 elements and ensures the translation of the contents of the register 99 to the group of I / O 9 of the unit 46 exchange unit 1 communication and further in interface computer1.

The functioning of the firmware (MA). The execution of the microprogram starts with the analysis of the signals coming from the register 100 through the AND elements 112 through the circuits 52 and representing the command code for the MA on the group of inputs 52 of the node 45 of the communication unit 2, and the control signal coming through the circuit 55 to the input of the And 48 element Upon detection of the mode code and one of the commands (input or output), the MA issues from the ROM 67 through amplifiers 63 one of the I / O circuits 8 of the TPD signal, providing access to the computer interface 2. The receipt of the PPD confirmation signal from the computer2 through one of the circuits of the I / O group 8 through the amplifiers 62 to the multiplexer 64 provides for branching the microprogram and installing the PV signal at the output of the ROM 67 through the amplifiers 63 to the computer2 interface. The transfer of information to (from) the computer begins with the installation at the outputs 51, 53 of the node 45 of the communication unit 2 of the code, arriving respectively at the group of inputs 51 of the node 46 of the exchange of the communication unit 2 and through the OR element 49 to the input 56 of the exchange node 46 and providing the output of the decoder 73 and the OR element 78 is a signal opening the AND elements 106. The contents of the address counter 98 are transmitted via the And 106 elements to the computer address / data line 10 and the computer is interpreted as the address of the cell with which information will be exchanged. Then, at the output of the ROM 67, an SIA signal is generated, which passes through amplifiers 63 and inputs-outputs 8 to the computer interface2.

After that, the MA, through the multiplexer 64, analyzes the type of command on the group of inputs 52 and proceeds to the operation INPUT-O + G or OUTPUT-0 + 1. Upon detection of the command OUTPUT-0 + 1 MA at the outputs 51, 53, 35 generates a code,

0 arriving respectively at the inputs of the exchange node 46 of block 2. This code provides the output of the decoder 73 (communication block 2) to remove the signal, opening, the And elements 106 and the appearance of the signal opening

5 elements And 107, and a signal that increases the contents of the counter 98 addresses on the chain: - output 35, element OR 47, input element And 48, input 54 of the node 46 exchange unit 2 communications. The contents of the data register 99

0 of the exchange unit 46 of the communication unit 2 is received through the element And 107 of the exchange unit 46 of the communication unit 2 in the computer 2, the contents of the address counter 98 are increased by 1, and the contents of the word counter 69 are reduced by 1. Then

5 from the ROM 67 through the amplifiers 63 to the inputs / outputs 8 in the computer output signal is output, then MA waits from the computer 2 signal confirmation SIP, which is received from the computer 2 through one of the circuits through

0 amplifiers 62 to the multiplexer 64. Upon receipt of the SIP signal, the MA removes the previously generated SIGNAL output on line 8 from the output of the ROM 67. The MA then analyzes the SIP signal from

5 of the computer interface 2, at the same time re-activates the signal 54, increasing the contents of the counter 98 by 1 and decreasing by 1 the contents of the counter 69.

When resetting the computer interface signal

0 SIP MA performs the formation at the outputs of the ROM of a code that provides at the output of the decoder 73 a high-level signal supplied through the OR element 81 to the output 57 of the exchange unit 46 and then to

5, the input of the multiplexer 64 of block 45 for transferring the MA to the transmission-reception mode of the second word from the array of exchanged information.

When 52 commands are detected at the inputs

0 INPUT-0 + 1 MA carries out from the ROM through the amplifiers 63 the input signal to the inputs-outputs 8 of the device. The receipt from the computer of the SIP signal through one of the input-output circuits 8 through amplifiers 62 means

5 that the required information is supplied to circuit 10, the MA generates a code at the output of the ROM 67 and at the outputs 53, 51, 35, which ensures the removal of the signal that opens the I 107 elements and the appearance of the signal coming through the OR elements at the output of the decoder 73 79 and AND elements 92, and through the OR element 91 which writes information from inputs / outputs 10 to the data register 99. At the same time, the signal in circuit 54 is activated, increasing the contents of the address counter 98 by 1 and decreasing the contents of the counter 69 words by 1. Next, MA completes execution of operation B OD similar output to complete the operation.

Similarly, exchange operations are carried out on the initiative of the second computer2.

Transmission / reception of the second word from an array of information. Upon receipt of a single signal on line 57 to the input of the multiplexer 64 of the node 45 of the communication unit 2, the firmware on the outputs 40, 18, 44, 36 generates the following code:

40 - a low-level signal supplied to the input of the And 5 element and forming a low-level potential at its output, received at the inputs 41 of the exchange nodes 46 of the communication units 1 and 2 and prohibiting the receipt of control signals from the operation code generating unit 3 through the And 72 elements , 83, 85, 96 of the exchange unit 46 of the communication unit 2 and from the operation code generating unit 4 via the AND elements 72, 83, 85, 96 of the exchange unit 46 of the communication unit 1. The high-level signal at the output of element 6 is fed through circuit 42 to the inputs of the elements I 75, 84, 87, 97 of the exchange nodes and allows the control signals to pass through the operation code generation unit 3 through the elements And 75, 84, 87, 97 of the block exchange node 46 1 communication to and from the operation code generating unit 4 via AND elements 75, 84, 87, 97 of the exchange unit 46 of the communication unit 2;

at the same time, at the output of the decoder 73 of the exchange unit 46 of the communication unit 1, a potential is formed that allows information to pass through the AND elements 104;

44 is a group of signals received at the inputs of a decoder 74 of an exchange unit 46 of a communication unit 1 and having a high voltage level;

36 is a low level signal input to an OR element 47 of an exchange unit 46 of a communication unit 1.

At this time, computer 1 transmits or receives the second word of information to / from computer 2,

Sending or receiving a second word from an array of information includes:

- only the write cycle in the register 99 of the exchange unit 46 of the communication unit 1 of the transmitted data or the read cycle from the register 99 of the exchange unit 46 of the communication unit 1 of the required information, since address of the memory cell with which

an exchange will be carried out and the operation code is in the corresponding counter and register of the exchange unit 46 of the communication unit 2. Communication.

The first phases of the exchange cycle (write-read) are similar to the above. Second

consider the phase of the exchange cycle separately

for the operation of writing and reading information

to / from data register 99.

Write operation. Second phase of the cycle

0 exchange starts with removing the address of the data register from lines 9, setting the recorded information on these lines and receiving the signal EXIT from the computer1 interface through one of the circuits of the input-output group 7 through the amplifiers 62 of the node 45 of the communication unit 1 to its output 23 and the output of the communication unit 1, to the input of the operation code generating unit 3 and the input of the second AND element 125 of the operation code generating unit 3. The recorded information is received through circuits 9 through the elements 104 of the exchange unit 46 of the communication unit 1 to the group of inputs / outputs 29 of the communication unit 1 and through the line 29 then to the group of inputs and outputs 30 of the exchange unit 46

5 of the second communication unit 2. When the signals coincide at the two inputs of the AND 125 element (the OUTPUT signal and the information recorded from the 50 element) of the operation code generating unit 3 at the output of the And 125 element

0, a signal is generated that is supplied through the circuit 37 to the input of the AND element 84 of the exchange unit 46 of the communication unit 1, which, together with a group of address code signals from the outputs of the control register 123 supplied via

5 circuits 31, 33 to the inputs of the elements And 87, 97 of the exchange node 46 of the communication unit 1 provides, at the output of the decoder 74, a signal for recording information from the group of inputs and outputs 9 of the exchange node 46 to the register 99 of the exchange node 46

0 communication unit 1.

The register number is provided by a code supplied from the outputs of the control register 123 via circuits 31, 33 and a signal at input 39.

5 The signals from the outputs of the decoder 74 (recording signals) provide the opening of the And elements from the group of And 92 elements and the supply of information to the register 99. At the same time, through the OR-NOT 91 element, the signal

0 records goes to the entries of the register 99 and writes information to the register 99.

The response signal (SIP) is generated in the computer interface by the OR element 5 120 and by the bus driver 121, from the output of which the SIP signal is supplied to the computer interface. The computer, having received the SIP signal from the device, removes the OUTPUT signal, which leads to the removal of the recording signal generated by the decoder 74 and to

removing the SIP signal. formed by the OR element 120 and the bus driver 121.

OASE OUTPUT is completed by removing the CIA signal on I / O 7 of the first communication block 1. At the same time, an active level is set at the input of the installation in O of the control register 123 and the register 123 is reset to the zero state, providing a resolution signal 1 at the input of the second AND 125 element. This causes a logical zero at the output of the And 125 element, which leads to the setting the decoder 74 of the exchange unit 46 of the communication unit 2 to the neutral state. At the same time, at its fourth output (at the input of AND element 115), there is constantly a low-level potential prohibiting the passage of signals to the reset input of the register of 100 commands

With Peraci Read. The second phase of the exchange cycle begins with the removal of the address from the lines) and the input signal input from the computer interface through one of the circuits of the input-output group 7 through amplifiers 62 of the unit

45Not output 21 and further to the input of the first element AND 124 of the operation code generating unit 3. From the output of the AND element 124, a coincidence signal (the INPUT signal and recorded info emation from block 50) is fed to the input of the OR element 49 of the communication unit 1, to one of the input to the OR element 120, and through the circuit 19 to the input of the And element 72 of the block exchange unit 46 2. From the output of the OR element 49, the signal enters the input 56 of the exchange unit 46 of the communication unit 1 and provides the output of the decoder 73 with the formation of a signal opening; through element AND 113, elements AND 105, and blocking elements AND 104. Next, the processes are similar to the RECORD operation, except that the code for the decoder 71 of the exchange node 46 is supplied together by chains 19, 33, 31 and the block decoder 74

46, the exchange of the communication unit 1 generates a read signal, opening the AND elements 107 and securing the translation of the contents of the data register 99 to the group of inputs / outputs 9 of the exchange unit 46 of the communication unit 1 and further to the computer interface 1.

Upon completion of the ENTER or OE OD operation with the registers and counter of the communication unit 46 of the communication unit 2, the firmware i of the communication unit 2 resets all previously generated signals (end of the loop) and proceeds to the execution of the command with a single bit on line 57.

The execution of the microprogram begins with the analysis of the signals coming from the register 100 of the exchange unit 46 of the communication unit 2.

If there is an exchange mode code (the code must be kept the same) and one of the commands (the code of which must also be saved), the MA issues the output from

ROM 67 of the following code, output 40 is a high signal level to enable inputs 31, 33, 19, 37 of communication unit 2.

Next, the MA performs the issuance of the ROM 67 through the amplifiers 63 in one of the circuits

0 inputs / outputs 8 of the TPD signal, providing requirements for access to the computer interface2. The receipt of the confirmation signal PPD from the computer2 on one of the circuits of the group of inputs-outputs 8 through amplifiers 62 on

5, the multiplexer 64 provides for the branching of the firmware and installation at the output of the ROM 67 of the PV signal supplied through amplifiers 63 to the computer interface2. The transmission of information to (from) the computer begins with the installation at outputs 51. 53 nodes 45 of the communication unit 2 of the code, respectively, received at the input group 51 of the exchange unit 46 of the communication unit 2 and through OR element 49 to the input 56 of the exchange unit 46 and providing at the output5 of the decoder 73 and the OR element 78, the signal opening the AND elements 106. The contents of the address counter 98 are transmitted through the And 106 elements to the computer address / data line 10 and interpreted

0 Computer as the address of the cell with which information will be exchanged. Then, at the output of the ROM 67, an SIA signal is generated that passes through amplifiers 63 and inputs / outputs 8 to the computer interface2.

5 After that, the MA, through the multiplexer 64, analyzes the type of command on the group of inputs 52 and proceeds to the operation INPUT-0 + 1 or OUTPUT-0 + 1. When an OUTPUT-0 + 1 command is detected

0 MA at outputs 44 generates a code arriving respectively at the inputs of the exchange unit 46 of the communication unit 1. This code provides, at the output of the decoder 74 (communication unit 1), the appearance of a signal that opens the I5 elements, 108, at the output of the decoder 73 (communication unit 2), the appearance of a signal that opens the And 105 elements, and a signal that increases the contents of the address counter 98 circuit: output 35. element OR 47.

0 input of AND element 48, input 54 of exchange unit 46 of communication unit 2. In this case, the contents of the data register 99 of the exchange unit 46 of the communication unit 1 enters through the elements AND 108 of the exchange unit 46 of the communication unit 1, a group of inputs-outputs 30, through the elements And 105 in the computer 2. The contents of the address counter 98 are increased by 1, and the contents of the counter 69 words is reduced by 1. Then, from the ROM 67 through the amplifiers 63 to the inputs / outputs 8 in the computer output signal is output, then MA waits from the computer 2 signal confirmation SIP, which is received from the computer 2 through one of the circuits through the amplifiers 62 to multiplexer 64. When a signal is received, the SIP MA removes from the output of the PP At 67, the previously generated output signal on line 8. Then, the MA analyzes the SIP signal coming from the computer interface 2, simultaneously activates the signal 54 again, increasing the contents of counter 98 by 1 and decreasing by 1 the contents of counter 69.

When the SIP MA signal is reset in the computer interface, the MA generates a code at the outputs of the ROM that provides the output of the decoder 73 of the zero level signal, which passes through the OR element 81 to the output 57 of the exchange node 46 and then to the input of the multiplexer 64 of the node 45 to put the MA in transmission mode -reception of the next word from the array of exchanged information.

Upon detection at the inputs 52 of the input-0 + 1 command, the MA carries out the input from the ROM through the amplifiers 63 of the input signal to the input-output 8 of the device. The receipt of the SIP signal from the computer via one of the input-output circuits 8 through amplifiers 62 means that the required information is supplied to circuit 10. MA performs the formation at the output of the ROM 67, at the outputs 53, 51, 44, a code that ensures the removal of the signal, the opening element And 105 of the exchange unit 46 of the communication unit 2, and the appearance of the signal at the output of the decoder 73, opening the And elements 104, and also, the output of the decoder 74 of the exchange unit 46 of the communication unit 1 of the communication unit opening the And 93 elements and through the OR element 91 recording the information received from the inputs and outputs of the communication unit 2 through the OR unit 91 of the exchange unit 46 of the communication unit 1 via elements AND 104 of the communication unit 46 of the communication unit 2 to the inputs 30 of the communication unit 1. Next, the MA completes the operation INPUT similar to the completion of the OUTPUT operation. Similarly, exchange operations are carried out on the initiative of the second computer2.

When transmitting / receiving the last word from the information array at the output of the O transfer of the 69-word counter, a low-level signal appears, which on line 60 will go to the setup input 1 of trigger 58 and put it into a state in which the signal 59 is output high level This signal will be fed to the input of the multiplexer 64 of node 45 of the communication unit 2, and at the output 51 of the ROM 67, a code will be received, at which the output of the decoder 73 will receive a reset signal received at the input of the OR element 81, and at the output 18 of the ROM 67 wits

a high level signal which will be input to the multiplexer 64 of the node 45 of the communication unit 1. At the same time, at the output of the ROM 67 of the communication unit 1, a TPR signal is received, which through the amplifier 63 will enter the interface of the computer1. Computer 1 satisfies the requirement and generates the input and SPR signals, which are sent along lines 7 through amplifiers 62 to the inputs of multiplexer 64. In doing so,

the output 51 of the ROM 67 is a code in which a signal is generated at the output of the decoder 73 of the communication unit 1, which arrives at the first inputs of the AND elements 118, opens them, and passes them to the inputs and outputs

9 is the address of the interrupt vector. Next, the ROM 67 generates an SIP signal and removes the TPR interrupt demand signal. Computer 1 receives the address of the interrupt vector and picks up the signals of ENTER and SPR. In this case, the output

51 ROM 67 a code is displayed that removes the opening signal of AND elements 118, output 44 displays a signal that opens AND gate 115 to pass a reset signal from the output of OR element 81 through AND element

115 to the reset input of the instruction register 100, and the SIP signal is removed. Further, the MA of the communication unit 2 carries out a reset of all previously generated signals, and there is also a reset (by removing the signal on line 18) of all

previously generated signals of the communication unit MA 1. The computer processor 1 performs the necessary operations and proceeds to the execution of the subroutine of the completion of the exchange of information and the transition to the main program.

Computer2 accesses to computer1 in this mode after reading the register of instructions, while on line 10 of the computer2 there is either the contents of the register of 100 commands of the exchange unit 46 of the communication unit 1, which is equal to zero at the end of the exchange (upon receipt of control signals from the unit 4 of generating the operation code to communication unit 1), or the bit is BUSY from the output of AND element 80

(upon receipt of control signals from the operation code generating unit 4 to the communication unit 2). The BUSY bit arrives at the output of the register of 100 commands through the outputs 15 of the communication unit 1, through inputs 16 and the AND element

103 of the communication unit 46 of the communication unit 2.

The presence of a bit on the trunk determines the availability of information in the registers and counter of the communication unit 1 (busy). The presence of a zero code on the trunk determines the possibility of accessing the computer1.

Claims (1)

SUMMARY OF THE INVENTION A computer interface device comprising two communication units, two operation code generating units, an AND element, and an element is NOT, each communication unit contains a firmware control node, an exchange node, a comparison node, an AND element (two OR elements, each exchange node contains two decoders, a command register, a data register, an address counter, sixteen groups of AND elements, two NOT elements, nine OR elements, ten AND elements and three OR-NOT elements, each operation code generating unit contains a control register, a delay element, an OR element, two AND elements and a bus driver, the command input and output of the first and second blocks whether the first and second control groups of the inputs and outputs of the device are respectively formed, the groups of information inputs of the first and second communication blocks are the first and second address inputs of the device, respectively, the first groups of information inputs and outputs of the first and second communication blocks form respectively the first and second groups of address data of the inputs and outputs of the device, respectively, the third outputs of the first and second blocks of the formation of the operation code are the first and second outputs of the clock signals Accordingly, the second group of information inputs / outputs of the first block is connected to the group of information inputs of the first block of forming the code) operation and to the third group of information inputs and outputs of the second communication unit, the second group of information inputs and outputs of which is connected to a group of information inputs of the second unit of generating the operation code, with a third group of information inputs and outputs of the first communication unit, equality outputs, the output of the i-input and the interface of the first and second communication blocks are connected respectively, with the information inputs of the output, input, and interface of the first and second blocks of generating the operation code, respectively, the first control input of the first block is connected to the second output of the first block of generating the operation code and the reading input of the second communication block, the first control input of which connected to the second output of the second operation code generating unit and to a reading input of the first communication channel, the first recording input of which is connected to the first output of the second operation code generating unit, the first recording input is w cerned communication unit connected to the first output of the first operation code generating unit outputs the first mode and the second communication unit connected respectively to the first and second inputs of the device element AND, the output of which is connected to the input of the element NOT of the device and to the second control inputs of the first and second communication units, the output of the second address of the first operation code generating unit is connected to the first control input of the second address of the first communication unit and with the second control input, the second address of the second communication unit, the first control input of which is connected to the output of the first address of the first operation code generating unit and to the second control input the first address of the first communication unit, the first recording input of which is connected to the second recording input of the second communication unit, the first recording input of which is connected to the second recording input of the first communication unit, the first control input of which is connected to the output of the first address of the second block the operation code and with the second control input the first address of the second communication unit, the read input of which is connected to the second output of the second operation code generating unit and with the first control input of the first communication unit, the third the equalizing input of which is connected to the output of the element NOT and the third control input of the second communication unit, the inhibit input of which is connected to the inhibit output of the first communication unit, the inhibit input of which is connected to the inhibit output of the second communication unit, the group of inputs of the operation code of which is connected to the group of outputs of the operation code of the first communication unit, the group of inputs of the operation code of which is connected to the group of outputs of the operation code of the second communication unit, the group of inputs of the control code of which is connected to the group of outputs of the control code of the first communication terminal, the group of inputs of the control code of which is connected to the group of outputs of the control code of the second communication unit, the input of the increment of which is connected to the output of the increment of the first communication unit, the input of the increment of which is connected to the output of the increment of the second communication unit, and in each communication unit the command input-output of the firmware control node is, respectively, the command input-output of the communication unit, the group of input / output addresses / data of the exchange unit is the first group of information input-outputs of the communication unit, the first the group of information inputs / outputs of the exchange node is connected to the first group of inputs of the comparison unit and is, respectively, the second group of information inputs and outputs of the communication unit, the second group of inputs of the comparison node is the group of information inputs of the communication unit, the first control input of which is connected to the second reading input of the exchange node and the first input of the second OR element of the communication unit, the second input of which is connected to the first control output of the firmware control unit, the outputs of which are output and input interface are respectively the outputs of the output and input interface of the communication unit, the output of the register attribute of which is the equality output of the comparison node, the output of the second OR element of the communication unit is connected to the first reading input of the exchange node, the second group of information inputs / outputs of which is the third group, respectively information inputs / outputs of the communication unit, the second control input of which is the first control input of the exchange unit, the second control input of which is the third control input of the communication unit, group Pa outputs of the operation code of the exchange node is connected to the group of inputs of the operation code of the microprogram control node, the group of code outputs of which is connected to the group of code inputs of the exchange node, the output of the increment code of the exchange node is connected to the first input of the AND element of the communication unit, the second input of which is connected to the output of the first of an OR element of a communication unit, the second input of which is connected to the output of the increment of the firmware control unit and is the output of the increment of the communication unit, the input of the increment of which is the second input of the first ele of the OR of the communication unit, the output of the element AND of the communication unit is connected to the increment input of the exchange unit, the first control input of the second address of which is the first control input of the second address of the communication unit, the second control input of which the first address is the second control input of the first node address exchange, the second control input of the second address of the exchange node is the second control input of the second address of the communication unit, the first control input of which is the first control input of the first address of the exchange node, the first and the second recording inputs of which are the first and second recording inputs of a communication unit, the inhibit input and output of which are the microprogram control node input and output inhibit, the input, output, interface and mode outputs of which are controlled respectively by the input, output, interface outputs and the mode of the communication unit, the group of outputs of the control code of which is the group of outputs of the control code of the firmware control unit, the second group of information inputs of the communication unit is the third group of information x inputs of the exchange node, the first group of information inputs of which is the first group of information inputs of the communication unit, the read input of which is the third reading input of the exchange node, and in the exchange node the outputs of the elements Ninth and ninth, 0 of the eleventh and fifteenth groups and the first inputs of the And elements of the first, third and sixth groups respectively form a group of inputs and outputs of the data of the exchange node, the outputs of the elements of the Eighth group and the first inputs of the elements of the ninth group respectively form the first. Group of information inputs - the outputs of the exchange node, the outputs of the elements of the twelfth, thirteenth and fourteenth groups 0 and the first inputs of the And elements of the second, fourth and fifth groups respectively form the second group of information inputs and outputs of the exchange node, the outputs of the command register are connected respectively to the first inputs of the And elements of the fourteenth, fifteenth and sixteenth groups and form the first group of outputs of the node operation code exchange, the input groups of the first and second decoders form, respectively, a group of code inputs and a third group of information inputs of the exchange node, the sync input of the command register is connected to the output of the first element NOR-coagulant, a first input coupled to the first output 5 of the first decoder, the second inputs of the AND elements of the first group are connected to the first input of the second OR-NOT element and the second output of the first decoder, the third output of which is connected to the second inputs of the AND elements of the fourth group and to the first input of the third OR-NOT element, the output of which is connected with a data register clock input, the information inputs of which are connected to the corresponding 5 outputs of the AND elements of the third and fourth groups, the second input of the third element OR is NOT connected to the first output of the second decoder, the first inputs of the elements of the tenth group are connected to the output of the address counter and the first inputs of the corresponding elements AND of the thirty group, the second inputs of which are connected to the fourth output of the first decoder, the fifth output of which is connected to the first inputs of the And elements, the twelfth group, the second inputs of which are connected to the corresponding outputs of the data register and the first inputs of the And elements innadtsatoy group, the second output of the second decoder coupled to the second inputs of elements And the eighth group, the sixth output of the periode decoder is connected to the second inputs of the elements And the fourteenth group, the group of outputs of the elements And the seventh and sixteenth groups form the second corpus of t outputs of the operation code of the exchange unit, the first group of inputs of the elements And the seventh corpse is the group the control inputs of the exchange unit, the information inputs of the command rep are connected to the outputs of the corresponding elements And the fifth and sixth circuits, the first input of reading the exchange unit is the first input of the first OR element, the second input is It is connected to the first input of the first decoder, the output of the first OR element is connected to the first input of the second decoder, the third output of which is connected to the first input of the third OR element, the second input of which is connected to the seventh output of the first desorter, the eighth output of which is connected to the second inputs of the AND elements of the second group and with the second input of the second OR-NOT element, the output of which is connected to the synchronization input of the address counter, the information inputs of which are connected to the outputs of the corresponding elements AND the first groups and elements of the second group, the increment block of the exchange unit is with the input of the address counter, the second inputs of the elements of the tenth group are connected, i to the output of the fourth element OR, the first input of which is connected to the fourth output of the second decoder, the fifth output is connected with the first input of the sixth OR element, the second input of which is connected to the ninth output, of the first decoder, the tenth output of which is connected to the second input of the fourth OR element, the output of the third OR element is connected | with the second inputs of the elements one- nadatoy group eleventh output of the first decoder is connected to a third input of the third OR-NO element and to the transition of the fifth OR gate, the output vom cat horn is connected to the second inputs of AND elements of the third group, the second input of the fifth OR element is connected to the first house of the second decoder, the sixth move third element AND, the output of which is connected nen which is connected to the first input with one of the outputs in the output group edros / data exchange node, the second input of the third element AND is connected to one of Dov of the second group of outputs of the code of the operating unit of exchange, the second inputs of AND elements output p of the fifteenth group are connected to the twelfth output of the first decoder, the thirteenth output of which is connected to the second inputs of the AND elements of the sixth group and to the second input of the first element OR NOT, the first input of which is connected to the second inputs of the AND elements of the fifth group, the second inputs of the elements AND the ninth groups are connected to the output of the tenth element And, the first input of which is connected to the sixth output of the second decoder, the second input of the tenth element And is connected to the output of the second element NOT. the input of which is connected to the seventh input of the first decoder, the bit of the output of the command register is the output of the command code of the exchange unit, the seventh output of the second decoder is connected to the second inputs of the AND elements of the seventh group and the input of the first element NOT, the output of which is connected to the second inputs of the elements AND of the sixteenth group , the second input of the first decoder is connected to the output of the second OR element, the first and second inputs of which are connected respectively to the outputs of the first and second elements, the first input of the last is the input shadow of the exchange node, the third reading input of which is the first input of the first element I. The second input of which is the second control input of the exchange node and connected to the first inputs of the fourth, sixth and eighth elements And, the second input of the second element And is the first control the input of the exchange node and connected to the first inputs of the fifth, seventh and ninth AND elements, the first input of the record of the exchange node is the second input of the fourth AND element, the output of which is connected to the first input of the seventh OR element, the output of which is connected connected to the third input of the first decoder, the fourth input of which is connected to the output of the eighth OR element, the first and second input of which are connected respectively to the outputs of the sixth and seventh elements AND, the second input of which is the first control input to the second address of the exchange node, the second control input to the second address which is the second input of the sixth AND element. the second input of the seventh OR element is connected to the output of the fifth AND element, the second input of which is the second input of the exchange node record, the first control input is not whose first address is the second input of the eighth element I. The output of which is connected to the first input of the ninth OR element, the second input of which is connected to the output of the ninth AND element, the second input of which is the second control input of the first address of the exchange node, the output of the ninth element OR is connected to the fifth input of the first decoder, and in the block generating the operation code, the first information input the control register is the information input of the operation code generating unit, the output of the first AND element is connected to the first input of the OR element and is the first output of the operation code generating unit, the output of the second AND element is connected to the second input of the OR element and is the second output of the operation code generating unit , the first inputs of the first and second elements AND are respectively the inputs of the output and input of the operation code generating unit, the output of the delay element is connected to the sync input of the control register, the input is set k O in which is connected to the input of the delay element and is the input of the operation code generating unit, the group of information inputs of the control register is the group of information inputs of the operation code generating unit, the output of the second address and the output of the first address of which are the first and second the outputs of the control register, the third output of which is connected to the second inputs of the first and second elements AND of the operation code generating unit, the output of the OR element is connected to the input of the bus forming, you the course of which is the third output of the operation code generating unit, characterized in that, in order to increase the speed of the device by eliminating many instructions for entering the operation code and analyzing the contents of the instruction register, a trigger is introduced into each communication unit , in each exchange node - an element And, an OR-NOT element, three groups of AND elements and a word counter, and on the communication unit, the end output of the exchange node is connected to the trigger synchronization input, the output of which is connected to the end-of-exchange control input of the microprogram control, the reset output of which is connected to the trigger input of the trigger O , output The end of the cycle of the exchange node is connected to the input of the firmware control node of the same name, and in the exchange node the output of the sixth element OR is the output The end of the cycle of the exchange node and connected to the first input of the eleventh element A second input coupled to an output of the first decoder fourteenth, and the fifteenth. the sixteenth outputs of which are connected respectively to the first inputs of the fourth element OR NOT, the elements AND of the seventeenth group AND and the second inputs of the fourth element OR, NOT elements of the eighteenth group, the outputs of which are connected to the outputs of the elements AND the seventeenth group and with the information inputs of the word counter, inputs synchronization and decrement which is connected to the output of the fourth OR-NOT element and the input of the increment of the address counter, the output of the transfer of the word counter is the output of the end of the exchange node, the group of inputs is set whose vector vectors are the first inputs of the elements of the nineteenth group, the second inputs of which are connected to the eighth output of the second decoder, the output of the eleventh element And is connected to the reset input of the instruction register. # w // fsffsi yeah fig 2 fig.Z L. 5 fff) FIG. 5 FIG. b