SU561180A1 - Device for interfacing a digital computer with peripheral devices - Google Patents

Description

data, the first output of which and the third output of the storage of control words are connected to the third input of the signal amplifiers block of communication with a digital computer. The second output and the third input of the signal amplifier unit with the power supply devices are connected schematically with the fourth input and the second output of the data buffering unit.

The disadvantage of the device is that it has very limited possibilities for stopping (.dp diagnostics and localization of the neioepamfOCteft of its own equipment, which ortvodpt to a large amount of time to restore and reduce the speed of the device.

The purpose of the invention is to reduce the time of diagnosis and localization of faults.

This goal is achieved by the fact that the proposed device contains a block of state of peripheral devices, a block for setting imitation modes, a control block for HHH imitation modes, a block for monitoring time intervals, and an autonomous check block. The first, second inputs and the first OUTPUT assignment of simulated connection modes, respectively, with the second output of the UCSVM, with the fourth JTbtM output of the decryption module and the Yokode of the simulation mode control unit. First and second entrances. the aapomyad block in the state of peripheral devices are connected to the fifth output, respectively;) address deciphering lock and to the third output, 1 ppm, 1 amplifiers of communication signals with peripheral devices, the first and second output inputs of which are connected to nepBbii and the second inputs of the autonomous verification unit, the third and fourth entrances. vykopy, I the first and second outputs of which are connected, respectively, with primary and second tiM to the weedodes and the outputs of the amplifier unit for communication with digital computers, with the input of the time interval control unit, with four 4 home of the exchange control unit, and the third inputs / outputs of which are connected to the inputs / outputs, respectively, of the control mode, imitation and time interval control unit. The second output of the simulation mode setting unit and the output of the peripheral devices memory unit are connected to the third input of the signal amplifier unit communication with digital computers

The block diagram of the device is given in cher "tezhe,

The device for interfacing the digital computer with peripheral devices comprises a block 1 of communication signal amplifiers with a digital computer, a block 2 of communication signal amplifiers with peripheral devices, a block 3 of address decoding,

a control word storage unit 4, a data buffering unit 5, a blended control unit 6, an imitation mode setting unit 7, a simulation mode control unit 8, a peripheral state memory unit 9, a time control unit 1O, and an autonomous checkout unit 11. In the drawing there are groups 12, 13 of the device's output-outputs, input-output 14, output 15 and inputs-outputs 16, 17 of the autonomous testing unit, outputs 18, 19, dy 20, 21-% output 22 and input 23 of the signal amplifier unit communication with the computer, outputs 24, 25, inputs 26, 27, 28 and output 29 of the signal amplifier unit of communication with peripheral devices, outputs ZО-ЗЗ of the deshi block (}, address radio, inputs-outputs 34-36 of the exchange control unit, output 37 units of setting modes and shtacii, output 38 of the autonomous check block, output 39 of the address encryption block, output 40 of the exchange control block, Bxofr-output 41 of the auto block og scanning duration.

The device can operate in the following main modes in the operating mode, in the mode of imitation of the peripheral system and in the B mode of autonomous testing.

In the operation mode can be executed ©% you:

a) software exchange of information between the RAM memory of the digital computer and peripheral devices under the control of the prog. frames of digital computers |

b) the exchange of information between the memory RAM of digital computers and ieriferknymi devices under the control of the device in the mode || vie direct access E memory;

i c) automatic search for power supply from the peripheral devices. I When operating in the operating mode, devices are addressed to five addressable RHOES of the common bus, registers bpock 4: the control register and the state, the regrind of the GISGR count of the slab of the high data byte register, and the non-addressable register of automatic request processing (as the drawing is not shown) You can load and read information from the cyeivfbix registers addresses programmatically.The appeal to any of them is as follows: The processor sets the address of the register on the line, on the code of the operation code – read code, or record. The writing on the data line sets up the loading information, after which the synchronization signal of the common bus is set. Unit 3 decrypts the address and operation code of the common bus coming in from output 18 and sets the corresponding signal at the output of the access register to the registers. When recording information into the corresponding register of block 4 comes from outputs 19, when information from the registers of block 4 is sent to a group of inputs and outputs 13 through & 21. Block 3 signals to block 6 teincMV about the output 39 operation, after which block 6 generates a response The first signal that arrives at the VOGOG group BEFORE & OUTPUT 13 is from input 23. The processor, having received this signal, ends the operation on the common bus. If the peripheral device registers a register, bluesh 3 is encrypted from the address of this peripheral device received from outputs 18 and the signal from output 39 starts block 6. Block 6 scrolls input-output 34 into the register of the command of peripheral number 4 the device, and the register number of the peripheral device from output 18, ncKJ; the number of the peripheral device; the register number of the peripheral device; the function code on input 2 through unit 2 is transmitted to the peripheral devices. If a recording type operation is carried out, block 6 with an output 40 signal, gates in block 5 to receive data from the 1Y output, and then from “open the output valves and data on block 5 to input 26 arrive through | block 2; per group of 12 I / O. In addition, when recording, information from the high byte register of block 4 is transmitted from the input 27 ® of the high-order line of the 12th order group, febJxoAOB. I If a complete log is recorded; datafe periphery devices, and a cycle of direct access to them in a group of 13 inputs-bins of the cache 6. & . You can loop into the register of the first byte of its byte blocks 4: the higher bit is given fciix. After eugo charging 7 c the perfume device cycle, for which block 6 exposes signal 28 from input 2 of block 2 (synchronization. After executing the operation, all the peripheral devices output the output clock response signals received at output 29 in block 6 Upon receipt of these clock signals, block 6 finishes the operation at the peripheral devices removes the clock signal from input 28. At a read operation, block 6 gates signals at output 40 and input / output 34 to receive information into block 5 and into the high byte register of block 4. operats In group 13 I / O, for which block 6 exposes a response synchronization signal to input 23, When reading a unit 6, pre-output signal 4 opens the output valves of block 5 to input 21, having received a response signal from the device from the device, the processor orders operation on an I / O pillar 13. In the direct memory access mode, the device operates 1 as follows: The contents of the bits are assigned to the direct command register access and function code of the peripheral devices stored in the control and status register edayuts by vhoda1 -Exit 34 of block 4 to block 6. Block a function code decrypts peripherals. If this is a reading code, i.e., the data will be transferred from peripheral devices to the memory of the digital computer, unit 6 starts the cycle of peripheral devices. To do this, from block 4, the peripheral device number, the device register number and the function code are transmitted to the output input group 12, and the function 6 is sent to the unit 28 and the sync signal is fed to the input 28 of the unit 2. After executing the command, the periphery {a live device exposes the data to a corresponding clock signal. Block 6, having received it from output 29 of block 2, by output signal J4O gates the reception of data into block 5. flea 6 removes the synchronic signal from input .28 of block 2 and performs a capture operation; groups 13 inlets-outputs for up to memory After the device becomes an invader unit 6 opens the output address register register of the 4th block of the 4th block with a signal on the acode 34 and it, the front of the autos to the input 2O of the block 1, opens the output valves Sj and its contents are transmitted to the input 21 of the block Ij to the input 23 of cell 1, the weights and signal code l hronizatsnn ca. After the operation is completed, the digital computer responds with a response snnhrosigny, which is nostuaet in blszh 6 at the remote control 22 1. lIlEaHJate: STiST signal; |, bpok. -6 completes the operation removes the signal snkkrony3.atsVy-gayitem / signal on the input j 34 myyfkts rut smesterzimye rvgstrv address us and type accounts blojSa 4. IF the block transfer is prohibited, then the group 13 input-output frees her cycle after the cycle of the cycle, after the cycle of the loop of the loop of the program, after the cycle of the loop of the loop of the input of the block If block transfer is enabled, group 13 input & Sh) 1 input (common bus) does not release c, n, nickle repeats without phase | capture this group. During the operation of writing data from the memory of the digital computer to the peripheral device, unit 6 first SOUTH the operation of capture 13 in 6BDB) HODs, and then the reading cycle of the contents of the memory cell of the digital computer, the address of which is stored in the memory address register of unit 4, is performed. For this, unit 6

a signal on input-output 34 opens the output valves of the register of the block memory address to the input 20 of block 1 and sets a read code to the synchronization signal on input 23 of block 1. After the reading operation is executed, block 6 signals 40 on the output of the output gate of block 1 in block 5. block 6 starts the cycle of peripheral devices, for which, using a high-voltage signal 4O, opens the output valves of block 5 on

input 26 of block 2, a command of peripheral devices is sent to input 27 of block 2, and a synchronization signal is sent to input 28 of block 2. After executing the command peripheral

Devices block 6 modifies the contents of the memory address and word count registers with the input-output signal 34. After this, as in the previous case, the transmission operations are repeated in a similar way.

If the bit resolution resolution is set for peripheral device addresses, then after each word is transferred, the peripheral device register number stored in 5B in the command register of block 4 is modified simultaneously with the contents of the memory address and word count registers.

In all cases, the end of work in the memory direct access mode occurs when the word count register is over-fulfilled, which signals this unit 6 to 34o input-output. After receiving this signal, unit 6 completes all operations and puts the device into its initial state In the automatic processing mode for Erosov, the device operates as follows: The discharge, the resolution of the automatic processing of the requests of the peripherals of the control register and the state of the block 4 is programmed from the digital computer. and the interruption from the transf & serial devices on output 24 of block 2, if the device is free from other operations, it automatically performs a read operation on the interrogation peripheral ™ devices.

. From block 6 to the input 28 of block 2, commands for reading the query word and the synchronization signal are given. When the command is executed, the peripheral devices send their own requests to the output 25 of block 2. Block 6, having received in response sync signals on output 29 of block 2, indicating that the command has been executed, the input-output signal 34 of the strobe receiving information from output 25 of block 2 to the register 4 for automatic processing of block 4 requests. Each peripheral device corresponds to an interrupt vector - the address of the memory cell of the digital computer, I storing the initial address of the service program given. After determining the highest priority protection and the corresponding vector of interruption, block 6 carries out the operation of interrupting the DVM program. As a result, the signal is passed from block 4 to input 21 of block 1 to the processor.

The mode of imitations of the perpendicular devices is intended for the dough check of the information paths and the function of the end nodes of the device. The simulation mode is defined by the program 1 by writing the mode control bits and the digits into the address 7 of the fleas 7, which can be addressed from the side of the group 13,

Consider the work of the device when checking the data buffering chains. The contents of the bits of block 7 at output 37 are not provided to block 8. When installed — the check of the buffers circuit dash; s, the block 8 blocks input – output 35 blocks in block 6 the output of the synchronization signal to input 28 of block 2 and the signal outputs exit 40, strobe reception and I’m looking at. formations from block 5 to peripheral roystvos. When a group of 1-3 inputs OUTPUTS is being accessed to peripheral devices, unit 8 simulates the response signals of peripheral devices. Otherwise, the sequence of operation in the device remains the same as in peripheral devices in working mode. Thus, in this mode, the input and output amplifiers of communication with the group 13 of the output outputs, the data recording circuit in the block 5 and the reading circuit of the contents of the 5o block are checked. In addition to the tsgr, the block 5, as well as In this mode, the same synchronization chains are used. as in working mode

For autonomous testing of a device, I use a self-checking test unit 11, This block contains a register of key switches for setting signals from the side of group 13 and 12 input-output indication circuit of these 12, input-output 12 of these, simulation circuit of control unit of input 13 group -exits; TsVM, sz: to it imitation of peripheral devices the register of plug-out switches for installation of an operating mode of the block. Verification of the device and system (i.e., DVC - interface device — the peripheral devices as a whole with the help of block 11 can be performed in modes A, B, C, D and D.

Claims (2)

1. US Patent No. 3815099, cl. 34O172, 1972. 2.SAMAS Bu "eiiti No. 7, 1973, p. 283.,