SU1100627A1 - Device for debugging programs - Google Patents

Abstract

DEVICE FOR DEBUGGING PROGRAMS containing a fixing memory block, a control block, an address generation block and a mode register, where the information input and output of the device are connected via a data bus to the input and data outputs of the adjusting memory block and the control block, the address inputs of the adjusting memory block These and address generation units form the device’s input address bus, the control, the inputs of the memory setup unit, the control unit, and the mode register form the device control bus, the register output the mode is connected to the input of the control unit mode, distinguishing it from the fact that, in order to expand the functionality of the device by increasing service operations, the display unit has been entered into the unit Kn optjiaiifm with the first, second. The third and quarter 1 | th outputs of the control unit are connected respectively to the first, second, third inputs of the Address Formation block and the control output of the device’s main memory access resolution, the third output of the control unit is connected to the control inputs of the setup memory block and the display unit, bus device data is connected to the input and output of the data of the address generation unit and to the first inputs of the information display unit, the control bus of the device is connected to the second input of the information display unit and, the control unit contains five triggers, transition commands, a group of AND elements, six AND-NOT elements, the first, second and third decoders, O) the IL-NOT element and the NOT element, the first bit of the control input of the block is connected to The D input of the first trigger, with the first inputs of the first and second AND-NOT elements, the second bit of the control input of the block is connected to the second inputs of the first and second elements of the AND-NO and the synchronization input of the first trigger, the third bit of the control input of the block is connected with sync input second the trigger- and through the element NOT with the control inputs of the third, fourth, fifth and sixth elements AND-NOT, the fourth bit of the control input of the block is connected to the inputs of the zero setting of the second and third triggers and to the first input of the element OR NOT, the output of which is connected to the input of setting zero of the fourth trigger, the data input of the block is connected to the information inputs of the first and second decoders, you, whose paths are connected respectively with SG by the inputs of the fourth trigger and

Description

with the first input of the sixth INE element, the mode input of the control unit is connected to the third inputs of the first and second AND-NOT elements, the output of the first trigger is connected to the first control input of the first decoder, to the control input of the second decoder, the output of the second trigger is connected to the input of the third element NAND, the output of which is connected to the control inputs of the AND elements of the group, the unit output of the third trigger is connected to the first input of the fourth element, to the first input of the third decoder, to the fourth input of the second element This AND-NOT, with the second control input of the first decoder with the input of the fifth element AND-NOT and the second input of the sixth element AND-NOT, Zero output of the third trigger and connected to the fourth input of the first element AND-NOT, the output of which is connected to single inputs second and

the third trigger, - with the second input of the element OR NOT and is the first output of the block, the output of the fourth trigger is connected to the second input of the third decoder, with the synchronization input of the third trigger and the second input of the fourth AND-NOT element, the output of which is the second output of the block , the output of the fifth trigger is connected to the third input of the third decoder, the first and second outputs of which are respectively the third and fourth outputs of the block, the outputs of the fifth and sixth elements AND-NOT are connected to the synchronization inputs fourth and fifth flip-flops, an output of second AND-NO element is connected to the third input of OR-NO element and the fifth unit vpsodom trigger branch instruction register output is connected to information inputs of the AND group whose outputs are connected to the output yes: nnyh block.

The invention relates to computing and can be used to debug programs and test microprocessor systems. . . A device for debugging programs is known comprising a control unit, a switching unit with a memory device, an information receiving and receiving unit, a control unit and a decoder register t1.

But the known device has narrow functionality, since the debugging programs are included in the main memory of the corresponding system.

It is also known a device for debugging microprocessor systems comprising a memory block, common to the device and the system being debugged, an information bus switch, a control block associated with the control buses of the debugging system L23.

The device allows debugging of the program of the system in various modes, however, it is rather complicated as it includes its own microprocessor with the appropriate equipment. Besides.

This device translates the system into debugs by an interrupt signal, which constantly requires an appropriate mode of the system being debugged.

The closest to the invention to the technical essence is a device for debugging programs, containing a setup memory

a unit connected by information input and output to the first output and input of the receiving and sending numbers and commands, the second output of which is the information output of the device, the address generation unit connected to the address input of the setup memory block, and the first input to the address input of the device, and a control unit, the input and output of which are the input of the access command and the output of the device commands, and the second output is connected to the access input of the setup memory block. The facility also contains the program mode register, whose inputs are control, and the output is connected to the second input of the SOC control unit. The disadvantage of the prototype is the need for resolving the interruption in the debugging program area, the belonging of the field of memory addresses, which stores the setup programs to the set of addresses of the main memory of the system being debugged. The latter limits the functionality of both the expansion of the setup programs, the faK, and the allowed amount of main memory. the invention is the expansion of the functionality of the system by increasing service operations programmatically. This goal is achieved by the fact that a device for debugging a program contains a setup memory block, a control block, an address generation block and a mode register, the information input and output of the device being connected via a data bus to the input and data outputs of the setup memory block and the control block, the address inputs of the setup memory and the address generation unit form the input address bus of the device, the control inputs of the setup memory unit, the control unit and the mode register form the control The device bus, the output of the mode register is connected to the mode input of the control unit, the information displaying unit is entered, the first, second, third and fourth outputs of the control unit are connected to the first, second, third inputs of the address generation unit and the control resolution code respectively device memory, the third output of the control unit is connected to the control inputs of the setup memory block and the information display unit, the device data bus is connected to the input and output data of the forming unit addresses and with the first inputs of the information display unit, the control bus of the device is connected to the second input of the information display unit, the control unit contains five flip-flops, a transition command register, a group of AND elements, six AND-NOT elements, the first, second and third decoders ,, element OR NONE. and element NOT, and the first discharge of the control unit the first discharge of the control input of the unit is connected to the D input of the first trigger, with the first inputs of the first 1,274 and second AND elements, the second discharge control input block Inen with the second inputs of the first and second elements AND-NOT and with the synchronization input of the first trigger, the third discharge of the control input of the block is connected to the synchronization input of the second triple and through the element NOT with the control inputs of the third, fourth, fifth and sixth elements AND - NOT, the fourth bit, the control input of the block is connected to the inputs of the zero setting of the second and third triggers and the first input of the OR-NOT element, the output of which is connected to the input of the zero setting of the fourth trigger, the input of the data block is connected to the information the inputs of the first and second decoders, the codes of which are connected respectively to the B-inputs of the four trigger and to the first input of the sixth AND-NOT element, the mode input of the control unit is connected to the third inputs of the first and second elements of the IS-NE, the output of the first trigger is connected to the first control the input of the first decoder, with the control input of the second decoder, the output of the second trigger is connected to the input of the third AND-NOT element, the output of which is connected to the control inputs of the AND elements of the group, the unit output of the third trigger inen with the first input of the fourth NAND element, with the first input of the third decoder, with the fourth input of the second NAND element, with the second control input of the first decoder, with the input of the fifth NAND element and the second input of the sixth AND NAND element, the zero output of the third trigger is connected to the fourth input of the first NAND element, the output of which is. It is connected to the single inputs of the second and third flip-flops, with the second input of the IPN-NOT element and is the first output of the block, the code of the fourth trigger is connected to the second input of the third decoder, the synchronization input of the third trigger and the second input of the fourth AND-NOT element, the output of which is the second output of the unit, the output of the fifth trigger is connected to the third input of the third decoder, the first and second outputs of which are. The third and fourth outputs of the unit are NOT – are connected to the synchronization inputs of the fourth and fifth triggers, the output of the second AND – NE element is connected to the third input of the ILINE element and the single output of the fifth the trigger, the output of the command transition register is connected to the information inputs of the AND elements of the group, the outputs of which are connected to the data output of the block. The essence of the matter is that when going into debug mode, the address of the next command extracted by the microprocessor from the main memory for execution is stored in the address generation unit, and the code on the data buses of the elements is replaced with a specific part of the program of the adjustment memory block (NBP). Since at the same time the control unit of the device permits the operation of the setup memory block and prohibits the operation of the main memory of the processor, thus ensuring the transition to the execution of the debugging program recorded in the NBP. The return to the continuation of the execution of the program of the main memory occurs according to the corresponding instruction O7 of the mode register according to the address stored in the address generation unit, and is followed by the reverse switching of the memory blocks. Such a solution of the device leads to the Tofty that the memory address field of the setup memory block cannot coincide with the memory address field of the Microprocessor-based debugging of the Microprocessor system, and the transition of the processor from the working mode to the fix mode (test) does not require the resolution of the fault, but increasing the set of service operations is associated only with an increase in subroutines in the NBP. Each of the debugging routines written to the LEP begins with the preservation of the microprocessor state word and the contents of its internal registers, and before returning to the main program, these parameters are restored. The results of the debugging (test) operation on the display unit, also controlled by the program in the NBP. Thus, a microprocessor controlled system, remaining in the automatic mode of operation, can provide on any part of the program both automatic and command execution of the main program, program change, reading and writing to any address of the main memory, reading the state words programs at each debugging step, automatic input and output of sections of the main program using technical tools, etc. At the same time, only by building up the software in the NBP it is possible to obtain a wide range of service operations in the amount of full memory addressed by the microprocessor, without restrictions on the volume and content of the program being smoothed, which is in the main memory. FIG. 1 is a block diagram of the debugging device of FIG. 2 is a functional block diagram of the control unit; in fig. 3 the truth table of the decoder of the control unit} in FIG. 4 is a functional diagram of an address generation unit; in fig. 5 - functional register mode register | in fig. 6 is a functional diagram of an adjustment memory block; FIG. 7 is a functional diagram of the information display unit; Fig. 8 is a timing diagram of the operation of the control unit when moving from the main program to the work with the NBP; in fig. 9 shows the structure of software recorded from the NBP; in fig. 10 is a timing diagram of the operation of the control unit in the execution, read and write command; FIG. 11 time diagram of the operation of the control unit when entering the main program. The proposed device (Fig. 1) consists of a control unit 1 connected by two-way communication with a data bus, an address generation unit 2, a setup memory unit 3, an information display unit 4, a mode register 5 and control ladders. To shchi-, data blocks are also attached to us 2-5, and blocks 2 and 4 are also connected to the address buses of a controlled microprocessor system. In addition, the control unit is connected to the microprocessor main memory sample enable input, as well as the sample enable inputs of blocks 2, 3, and 4. In FIG. 2 shows a functional block diagram of the control unit, which is an automaton containing five triggers 6-10, six elements AND-NO 11-16, element NOT 17, element OR-NOT 18, decoder 19.1 (return command code), decoder 19.2 ( memory access command code), a group of elements AND 20, a transition command register 21 and a decoder 22, the truth table of which is shown in FIG. 3. In FIG. 4 shows a functional block diagram of an address generation unit 2, which is a memory register 23, an input r -multiplexer 24, which connects an address bus or a data bus to the input register 23, and an output set of three-stable keys 25. FIG. 5 shows a functional diagram of the register 5 of the mode, which is a multi-bit register 26, the inputs of which receive control actions that determine the mode of operation and the type of serving operation, as well as a set of three stable switches 27 connected to the data bus. FIG. 6 shows a functional diagram of a setup memory block 3 built according to a known circuit using RAM and ROM memory elements on integrated circuits. Elements 28-28 are a subset of the RAM elements necessary for the operation of the debugging programs recorded in the ROM on the elements 29-29. The address decoder 30 has a sample enable input associated with the output b; unit 1. Communication with the microprocessor data bus (SM) is via bi-directional buffer 31. Block A is interfaced with the microprocessor as a standard external device via data, address and control buses. Various devices can be used as a display module g, for example, a standard display panel ПИУ-2. The structure of the block 4 is shown in FIG. 7. It includes a register 32 and a display module 33. The device operates as follows. In the initial state at the output b of the control unit 1 there is a single NBP prohibition signal, and at the output bg there is a zero potential for resolving the sample of the main memory. The microprocessor operates in automatic mode. A connected device does not interfere with the normal operation of the microprocessor system. The signal of the start of the mode from the frame arrives in the form of a single level from the output from the mode register to the input dj of control unit 1. This signal in the next-instruction microprocessor cycle from the main memory by the I-NE unit 11 of the control unit 1 produces a signal, KOTojJhrt along b, j, is transmitted to the eJj of the forcing of the address input as a recording signal of the frequency of the main memory from which Should be next team. In the absence of a permission signal at output b of block 1, connected to input 3 of a flea 2 through a multiplexer 24, an address bus is connected to the input of register 23. As a result, the corresponding address is recorded in register 23 of block 2. Simultaneously, the triggers 7 and 8 are set to t and the memory sample enable signal is switched from 15th output b to Ь4 of block 1. With the arrival of a control signal on the input "signal, block 1 sends through the IS-NE 13 input b to the bus The data is the code of the transition command to the initial memory area of block 3, which is executed by the microprocessor in subsequent cycles. The falling edge of the signal fhi is reset by trigger 7. The timing diagram of the operation of block 1 during the transition to debug mode is shown in FIG. 8. Thus, the device places the microprocessor in the mode of operation with a debugging program recorded in the ROM of the setup memory 3. The structure of the debugging program is shown in FIG. 9. The program begins with memorizing the processor status word and the contents of the internal registers, then, using the mode code read from mode register 5, it goes to one or another module (subroutine) of service maintenance (N -N), among which There may be Start, Read registers, Photo drive, Read from memory, Write to memory, Test, etc. The number of these modules, i.e. the size of the NBP memory is limited only by the microprocessor and coping addressing capabilities, since in general the NBP volume can be equal to the total volume of the main memory of the microprocessor system. All service modules (subroutines), with the exception of the Start-up module, provide the transition to the service module of the display unit, where the results of the operation are output. The program then goes back to the polling module of the mode register 5, waiting for a new indication. Only after the execution of the Start instruction, the registers and the word of the state of the main program are restored and the transition to working with the main j memory is performed. Separately, we stop the operation of the device in the read / write mode of the main memory. NBP modules (subprograms) that implement read / write operations to the main memory are used directly to implement a read / write operation on one of the modifications of read / write commands that should not be used in the NBP. for other purposes, tf With the arrival of a command code (memory accesses to the data bus (input a, control unit T)) the decoder 19 is triggered. 2 codes of these commands, and on the falling edge of the signal through the IS-NE element 16, turns on trigger 10, which indicates, according to the table (Fig. 3), the reverse switching of the resolution signals of the main memory and the NBP (outputs b, for "25

The timing diagram of the operation of unit 1 when accessing the main memory at; shown in FIG. 10. Reverse switching, i.e. the return to work with the NBP takes place with the arrival of the sign of the choice of the next team. Thus, the device provides sampling of the read command from the N-PSU, and execution of the operating part of the read / write command with the connected main memory.

The transition to the execution of the processor's main memory programs is also carried out according to the code read from the mode register (start operation code). Moving to the corresponding module o (subroutine) in the NBP (Fig. 3), the microprocessor performs one of the modifications of the return command that is prohibited in other parts of the NBP memory. The timing diagram of the operation of the control unit for switching to main memory is shown in FIG. 11. With the arrival in the sampling cycle of the command code of the specified modification to the input 3 of control block 1, the decoder 19.1 is triggered and the trigger is activated on the rising edge of the rtri signal 9. In this case, according to the logic of the decoder-22 of block 1 (Fig. 3), the resolution is removed from the outputs of L4 D 45 of block 1. And during the execution of the operational part of the return command, the pulse 14 will force a pulse on the data bus of the transition address stored in block 3 of the formation of the address. This pulse from the output of block 1 enters the input cfj of block 3 and enables the transfer of the code from register 23 to the SD, which is read by the microprocessor and determines the address of the next command to be executed. With the arrival of the next indication of the command selection, the signal from the output of the element ILINE 18 is switched off sequentially by the trigger 9 and 8, which, according to the logic of operation of the decoder 22, determines the resolution of the sampling of the main memory and the prohibition of the NBP sampling l. At this point, the transition to executing the program being debugged is completed.

The proposed device allows for the process of debugging software and hardware and software operating under microprocessor control. Debugging can be done using a wide range of debugging operations. Expanding and modifying debugging functions does not require an increase or change in the hardware in the device, but only an increase or change in the software recorded in the NBP. The capacity of the NBP can be increased to the volume of the entire memory addressed by the microprocessor. At the same time, the transition to the debugging mode does not require restrictions on the contents of the program (for example, resolution of the pregloanie) in the main memory of the microprocessor system. In addition, the microprocessor system being debugged may not have hardware in step mode and display facilities. Even being constantly in the automatic mode of operation, the microprocessor with the help of the proposed device can provide step-by-step execution of the program and an indication of all the necessary setup information. Taking into account these possibilities, the proposed device allows to increase the efficiency of the debugging process and makes it possible to use it as a simple portable console for debugging, monitoring and diagnosing microprocessor systems.

/ Lm-v

(g

ofj, o

M ej

WS D4 SCH. /

ou / - / afMff7e /

H rful.

 gA / /

G /

2

/ Cinech: a, Favorable O signal

Vr

(

fiS / i inc allowing 57 x- anpeutef / ffoe composition Hue

hi.S

KllID

about

Fy

KttA

/ ytu / pffue

MofKuom6 l {St} f

9

4/2. L

Claims (1)

DEVICE FOR DEBUGGING PROGRAMS, comprising a setup memory unit, a control unit, an address generation unit and a mode register, wherein the information input and output of the device via the data bus are connected respectively to the input and output data of the setup memory unit and the control unit, address inputs of the setup memory unit and unit the formation of the address form the input address bus of the device, control, the inputs of the adjustment memory unit, the control unit and the mode register form the control bus of the device, the output of the mode register connected to the control unit mode input, characterized in that, in order to expand the functionality of the device by increasing service operations, an information display unit is introduced into the device, the first, second, third and fourth outputs of the control unit ^ 'being connected to the first , second, third by the inputs of the address generation unit and the control output of the sampling resolution of the main memory of the device, the third output of the control unit is connected to the control inputs of the adjustment memory unit and the display unit For information, the data bus of the device is connected to the input and output of the data of the address generation unit and to the first inputs of the information display unit, the control bus of the device is connected to the second input of the information display unit, and the control unit contains five triggers, a jump instruction register, a group of AND elements, six AND-NOT elements, first, second and third decoders, OR-HE element and NOT element, moreover (the first bit of the control input of the unit is connected to the D-input of the first trigger, with the first inputs of the first and second elements s NAND, a second discharge control input unit is connected to the second inputs of the first and second AND-NO element and to the input of sync 'of the first flip-flop, a third · discharge unit control input connected to the input of the second synchronization trigGe-. and through the NOT element with the control inputs of the third, fourth, fifth and sixth AND-NOT elements, the fourth bit of the control input of the unit is connected to the zero-setting inputs of the second and third triggers and to the first input of the OR-HE element, the output of which> is connected to the installation input zero of the fourth trigger, the data input of the block is connected to the information inputs of the first and second decoders, the outputs of which are connected respectively to the D inputs of the fourth trigger and, 129.0.01 (“Zh” with the first input of the sixth INE element, control unit mode input the phenomenon is connected to the third inputs of the first and second AND-NOT elements, the output of the first trigger is connected to the first control input of the first decoder, to the control input of the second decoder, the output of the second trigger is connected to the input of the third AND-NOT element, the output of which is connected to the control inputs of AND elements group, the single output of the third trigger is connected to the first input of the fourth AND-NOT element, with the first input of the third decoder, with the fourth input of the second AND-NOT element, with the second control input of the first decoder; with the input of the fifth AND-NOT element and the second input of the sixth AND-NOT element, the zero output of the third trigger is connected to the fourth input of the first * AND-NOT element, the output of which is connected to the unit inputs of the second and third triggers, - with the second input of the OR element- HE is the first output of the block, the output of the fourth trigger is connected to the second input of the third decoder, with the synchronization input of the third trigger and the second input of the fourth NAND element, the output of which is the second output of the block, the output of the fifth trigger is connected to the third input a third decoder, the first and second outputs of which are the third and fourth outputs of the block, respectively, the outputs of the fifth and sixth AND elements are NOT connected respectively to the synchronization inputs of the fourth and fifth triggers, the output of the second AND element is NOT connected to the third input of the OR element HE and a single output of the fifth trigger, the output of the transition command register is connected to the information inputs of elements AND groups, the outputs of which are connected to the data output of the block.