SU1442990A1 - Memory addressing device - Google Patents

Abstract

The invention relates to computing and can be used to create microprocessor systems with a large memory capacity. The purpose of the invention is to increase the reliability of the device. The device for addressing the memory contains the address decoder 1, the element NOT 2, the three elements AND 3-5, the resource register 6, the shift register 7, the ele

Description

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mentor 8, pulse generator 9, two registers 10, 11, delay element 12, trigger 13 and switch 14. New in the device are the third AND element, resource register, shift register and pulse generator with their functional connections. The device allows to execute the command of the microprocessor system when moving from cube to cube of memory by any command that does not require the presence of

data access programs in each memory cube. The device also makes it possible to mask memory cubes in which commands or data are stored that are to be protected, while recording information into masked memory cubes is prohibited. Thus, simplifying access to data and commands, protecting memory cubes results in increased reliability of the device. I il.

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The invention relates to computing and can be used to create microprocessor systems with a large memory capacity.

The purpose of the invention is to improve the reliability of the device

The drawing shows a functional diagram of the device.

The device for addressing the memory contains the decoder address I, the element NOT 2, the first 3, the second 4 and the third 5 And elements, the resource register 6, the shift register 7, the OR element 8, the pulse shaper 9, the first 10 and second 11 registers, the element 12 delays, trigger 13, switch 14.

The device works as follows.

 Suppose that the i-th output of the switch 14 is connected to the control input of the NIN of the i-ro memory cube, and (the primary input of which is connected to the address input of the device. When it is initially installed, the Reset signal is generated in the micro-computers generator, which sets the address input to the zero state and resetting to the zero state registers 10 and 11 (not shown), the zero code from the outputs of which goes to the first information input of the switch 14 and leads to the switching of control signals to the input of the zero cube memory. 13 at the beginning, it is set arbitrarily and determines which of the registers, 10 or 11, provides information.

; The transition from cube to cube can be accomplished, either by commands IMPADDR CAbLADDR, RET, or by any other command. The entry in the resource register is performed by the commands SH1, OUT. When executing the OUT command, the decoder 1 outputs the logical I, which passes through the first element 3 and enters the clock input of the register 6 resources, the latter enters the code M. The device operates in two modes.

The low order of resource register 6 controls the operating modes of the device. The first mode of operation of the device is established if a logical o is written in the lower order of the resource register 6, the operation of the pulse shaper 9 is enabled and the operation of the And 5 element is blocked. To go from cube O to cube 1 (0), it is necessary to write code i into the microprocessor battery in the main program and, using the OUT command, write the contents of the battery to register 10 with address Z.

When the OUT Z command is executed, the microprocessor reads the command in the first machine, the address in the second, and the address Z in the third device address, the i code on the information input, and a signal on the device access input, which enables the decoder to work. In this case, the decoder outputs a logical 1, which, through the element 4, to the second input from the output.

the inverter is supplied logically, is fed to the clock input of register 0, the latter writes the code i from the information input. The logical output of the AND 4 element also zeroed the shift register 7.

When executing the next command (all commands are accompanied by a signal

The code of the memory cube containing data1.15 in register 10 is similar to the first mode of operation.

Next, the main program is executed. In this case, if a command reading cycle occurs, the code to the first information input of the switch 14 issues a register 1 I, if it occurs

Ml, which enters the input of the command any other cycle, then the signal Ml, the device’s finite loop), which can be either a command, С ALL, IMP or any other command, shift register 7 enters the logical 1 for the first time Then, the microprocessor executes the command, when any next command arrives at the second output of the shift register 7, logical 1 appears. When it appears, the pulse generator 9 generates a pulse at the output, which resets the trigger 13 and enters the delay element. Since the flip-flop 13 is cleared, the information begins to issue a register 10, and the output of the register P goes into the third state.

Upon completion of these operations, the pulse signal delayed by the delay element 12 is fed to the clock input of the register 11, according to which the code contained in the register 10 is written to it. At the beginning of the next exchange of the microprocessor, the trigger 13 is set by the synchronization signal

The second one accompanies any microprocessor cycle, except for the command one, enters the non-command cycle, the device passes through an element, 5, 15 element OR 8 and resets trigger 13, which causes switching to issue a code to the first information input of switch 14 of register 10. V At the beginning of the next cycle of deception, the trigger 20 ger 13 is set again.

There are no conflict situations when resetting and installing 13, since the HI signal comes later than the exchange synchronization signal. 25 Switch 14 operates in the following manner.

If in the second section of the register 6 of the device resources arriving at the control input of the switch 14, 30 is recorded 1, the execution of the mask installation program begins. This program is recorded in the 0th memory cube. In this case, the recording and reading of all memory cubes, except zero, is blocked, and

If in the second section of the register 6 of the device resources arriving at the control input of the switch 14, 30 is recorded 1, the execution of the mask installation program begins. This program is recorded in the 0th memory cube. In this case, the recording and reading of all memory cubes, except zero, is blocked, and

exchange, which arrives at the input on the switch -g 14 by the recording signal, started the cycle of the device, the outputs of register 10 go to the third state, and register 11 starts to issue a code to the first information input of the switch.

The process of returning to the original or any other cube memory occurs in a similar way after the OUT Z command is executed by the microprocessor. The device waits for the next command to be executed for OUT Z and then switches registers 10 and 11 so that the cube code of the cube to which it returns or transition occurs to the first information input of the switch.

The second mode of operation of the device is set if the logical 1 is written to the younger register of the resource register, and the operation of the pulse shaper 9 is blocked, and re eg the AND.5 bot of the element 5 is resolved. Register 11 contains the memory cube code containing the command. Further, the microprocessor performs the recording procedure.

step on its third information input, writes information to the mask register, the code of which is fed to its fifth information input from the resource register 6 (older 5 bits). After recording the masks for all memory cubes, the microprocessor writes a logical O to the second bit of the resource register, while

45, the switch 14 transmits the address codes of the memory cubes, arriving from register 11 and 10 to its first information input, and the signals from the sample of the memory cube and writing to the memory cubes, arriving at its second and third information inputs, respectively. From masks; A bath memory cube can only read information.

Claims (1)

Invention Formula A device for addressing memory containing an address decoder, first and second register, first and second 50 The code of the memory cube containing data1.15 in register 10 is similar to the first mode of operation. Next, the main program is executed. In this case, if a command reading cycle occurs, the code to the first information input of the switch 14 issues a register 1 I, if it occurs It accompanies any microprocessor cycle, except the command one, enters the non-command cycle, passes the device through element 5, 5 element OR 8 and resets trigger 13, which causes switching to issue a code to the first information input of switch 14 of register 10. V At the beginning of the next cycle of deception, the trigger 0 ger 13 is set again. There are no conflict situations when resetting and installing 13, since the HI signal comes later than the exchange synchronization signal. 5 Switch 14 operates in the following manner. If in the second bit of the register 6 of the device resources arriving at the control input of the switch 14, 0 is recorded 1, the execution of the mask installation program begins. This program is recorded in the 0th memory cube. In this case, the recording and reading of all memory cubes, except zero, is blocked, and g switch 14 signal recording, by step on its third information input, writes information to the mask register, the code of which is fed to its fifth information input from the register of 6 resources (senior 5 bits). After recording the masks for all memory cubes, the microprocessor writes a logical O to the second bit of the resource register, while the switch 14 passes the address codes of the memory cubes, coming from registers 11 and 10 to its first information input, and the signals from the sample of the memory cube and writing to the memory cubes, arriving at its second and third information inputs, respectively. From masks; A bath memory cube can only read information. Invention Formula A device for addressing memory containing an address decoder, first and second register, first and second the OR elements, the delay element, the trigger and the switch, the information input of the address decoder is connected to the device’s input input, the information input of which is connected to the information input of the first register, the output of which is connected to the information input of the second register, the output of which is connected to the first information input of the switch; which is connected to the inputs of the setting of the memory operation mode of the device-. in order to improve the reliability of the device, the third element AND, the element NOT, the resource register, the shift register and the pulse shaper are entered into it, and the minimum address bit of the device address is connected to the first input of the first the element AND and the input of the element SCH, the code of which is connected to the first input of the second element MS, the second input of which is connected to the second input of the first element AND and the output of the address decoder, the control input of which is connected to the device input, the input The cube memory has a recording entry into the memory cubes of which are connected respectively to the second and third information inputs of the switch, the fourth information input of which is connected to the information input of the device and the information input of the resource register, the output of the first bit of which is connected to the first input of the third element And the prohibitive entrance of the imager imt pulses, the output of which is connected to the input of the delay element and the nepEbiM input of the OR element, the second input of which is connected to the output of the third element And, the second input of which is dinen with non-command loop input the device whose cycle start input is connected to the trigger setup input, the clock input of which is connected to the output of the OR element, and the information input to the zero potential input of the device, the command cycle input of which is connected to the shift register shift input, the parallel input information input is connected to the input zero potential of the device, and the information input of the sequential entry - with the input of a single potential the device, the output of the first element I is connected to the clock input of the resource register, the output of which is connected to the fifth information input of the switch, the control input of which is connected to the output of the second bit of the resource register, the information input of the pulse former is connected to the output of the shift register, the parallel write enable input which is connected to the output of the second element I and the clock input of the first register, the input resolution of which information is connected to the inverse output of the trigger, the direct output of which is connected to the input of the information output permission of the second register, the clock input of which is connected to the output of the delay element, the output of the first the register is connected to the first information input of the switch.