JP2648017B2 - Microcomputer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly, to a bus control mechanism of a microcomputer used in a development support device.

[Conventional technology]

Generally, this kind of microcomputer is placed in the development support equipment, and it is necessary to access not only the resources (memory and I / O) of the prototype system but also the resources inside the development support equipment. It is used in combination with a bus monitoring circuit and a bus switching circuit.

FIG. 5 is a block diagram showing an example of a bus signal control unit of a conventional microcomputer.

When the bus needs to be accessed inside the microcomputer 202b, the cycle request signal 110 becomes active, and the timing signal generator 102 starts operating in synchronization with the timing clock signal 109. The internal address signal 106 is taken into the address latch 101 by the address latch signal 108 output from the timing signal generator 102, and is output as the address signal 107 to the outside of the microcomputer 202b.

Separately from this, the cycle start signal generating circuit 104 in the bus cycle start signal generator 103 is activated by the trigger signal 111 output from the timing signal generator 102, and the bus cycle is externally provided to the microcomputer 202b. Output as the start signal 112a.

FIG. 6 is a block diagram showing an example of a conventional development support device using a microcomputer. Here, a portion surrounded by a dashed line is the development support apparatus 201a, and a prototype system 207 is located outside the development support apparatus 201a.

The address signal 107 output from the microcomputer 202b is connected to the prototype system 207 through the address buffer 203.

The bus cycle start output signal 112a output from the microcomputer 202b is input to the prototype system 207 via the mask circuit 204.

The development support device 201a not only executes the program stored in the prototype system 207, but also executes the development support device 201a.
Since it is necessary to execute a control program for accessing various memories and I / O devices placed inside 201a, a memory circuit 206 on which a control program is written and a memory circuit 206 for switching between them are provided. Circuit.

The address monitoring circuit 205 has an access switching function. The address monitoring circuit 205 constantly compares and monitors a value set in the circuit in advance and an address signal 107 output from the microcomputer 202b, and starts a bus cycle when accessing the prototype system 207. The signal output inhibit signal 210 is made ink active, and the bus cycle start output signal 112a is supplied to the prototype system 207.

Conversely, when the microcomputer 202b executes the control program, the address monitoring circuit 205
Activates the bus cycle start signal output inhibition signal 210 to inhibit access to the prototype system 207, and activates the memory selection signal 213 to access the memory circuit 206.

[Problems to be solved by the invention]

As described above, in a conventional microcomputer, a signal indicating the start of a bus cycle is output at the same time as an address signal. Therefore, when this signal is used on a development support device, it is based on the address signal. When the control for permitting or prohibiting the output of the signal indicating the start of the bus cycle is performed, the bus cycle start signal 214a as shown in FIG.
However, there is a drawback that glitches occur on timing.

Cycle is timing clock signal 109 is cycle T
It is started from the point of 1, and after each cycle T2, T3,
Transition to the next cycle.

When the cycle T1 starts, the address signal 107 and the internal cycle start signal 112a are simultaneously enabled.

At this time, if the value of the address signal 107 indicates that the internal memory of the development support device 201a is accessed,
The mask signal 214a becomes active to inhibit (mask) the output of the bus cycle start output signal 112a.

However, the mask signal 214a is the address signal 107 output at the same timing as the bus cycle start output signal 112a.
, The mask timing is not in time, and a glitch shown in a dotted circle is generated.

An object of the present invention is to provide a microcomputer capable of permitting or prohibiting the output of a signal indicating the start of a bus cycle.

[Means for solving the problem]

Therefore, according to the present invention, at the start of a bus cycle in which an address signal is output to an address bus to access data, a bus cycle start signal indicating the start of the bus cycle is externally output in synchronization with the output timing of the address signal. A bus cycle start signal generating means, wherein the bus cycle start signal is masked in accordance with the address signal and is output to an external access destination of the data. A cycle start signal generating circuit that outputs an internal cycle start signal indicating the start of the bus cycle and a delay signal thereof in synchronization with the output timing; and Switching to either the internal cycle start signal or the delay signal It comprises a signal switching circuit for external output, as was the bus cycle start signal.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a bus control unit of a microcomputer according to a first embodiment of the present invention.

The microcomputer 202 receives an internal address signal 106 and an address latch signal 108 and outputs an address signal 107 to the outside. The microcomputer 202 receives a cycle request signal 110 and a timing clock signal 109 to receive a trigger signal 111 and an address latch. A timing generator 102 for generating a signal 108; a timing clock signal 109 and a trigger signal 111;
And a bus cycle start signal generator 103 for outputting a bus cycle start signal 113 in response to the bus cycle start signal 113.

The bus cycle start signal generator 103 has two signals 111
Start signal generation circuit 104 that outputs internal cycle start signal 114 and internal cycle start delay signal 115 by inputting signals 109 and 109, and starts one of two signals 114 and 115 according to external timing switching input signal 113 Signal 112
And a signal switching circuit 105 that outputs a signal.

When the bus needs to be accessed inside the microcomputer 202, the cycle request signal 110 becomes active, and the timing signal generator 102 starts operating in synchronization with the timing clock signal 109.

The address output from the timing signal generator 102
In response to the latch signal 108, the internal address signal 106 is taken into the address latch 101 and output as an address signal 107 outside the microcomputer.

Separately, a bus cycle start signal generator
To activate 103, a timing signal generator 102 outputs a trigger signal 111.

The bus / cycle start signal generator 103 includes a cycle start signal generator 104 and a signal switching circuit 105. The trigger signal 111 output from the timing signal generator 102 is input to the cycle start signal generator 104.

The cycle start signal generation circuit 104 is activated by the trigger signal 111, and outputs an internal cycle start signal 114 and an internal cycle start delay signal 115 to the signal switching circuit 105.

The internal cycle start delay signal 115 is a signal generated based on the internal cycle start signal 114, and has a delay synchronized with the timing clock signal 109 with respect to the internal cycle start signal 114.

The signal switching circuit 105 outputs either the internal cycle start signal 114 or the internal cycle start delay signal 115 as a bus cycle start signal 112 according to the setting of the timing switch input signal 113 input from the outside of the microcomputer. Output to

Thus, the address signal 107 can be output relatively earlier than the bus cycle start signal.

FIG. 2 is a block diagram of an example of a development support device using the microcomputer of FIG.

The portion surrounded by the dashed line is the development support device 201, and the prototype system 207 is located outside the development support device 201.

The address signal 107 output from the microcomputer 202 is connected to the prototype system 207 through the address buffer 203.

The bus cycle start signal 112 output from the microcomputer 202 is connected to the prototype system 207 via the mask circuit 204.

The development support apparatus 201 includes, in addition to the conventional address monitoring circuit 205 and memory circuit 206, a timing switching input signal 113 for changing the output timing of the bus cycle start signal 112, which is a feature of the present invention, and a switching signal 212. A switching signal generator 211 for controlling is included.

Here, the switching signal generator 211 has a function of activating the timing switching input signal 113 by a control system different from the microcomputer 202.

As described in the conventional example, the development support apparatus 201 switches whether the address monitoring circuit 205 accesses the prototype system 207 or the memory circuit 206 based on the value of the address signal 107 output from the microcomputer 202. .

As shown in FIG. 3, when the switching input signal 113 is inactive, the microcomputer 202 operates the memory circuit 206.
Access, the address signal 107 is output at the same timing as the bus cycle start signal 112, so that the mask circuit 204 cannot mask the bus cycle start signal 112, but the switching input signal 113 remains active. When the memory circuit 206 is accessed, the bus cycle start signal 112 is output at a timing later than the address signal 107, so that the output inhibit signal 210 is activated before the bus cycle start signal 112 is output. Thus, the output of the bus cycle start signal 112 to the prototype system 207 can be prohibited.

Cycle T1 with switching input signal active
Thus, the internal cycle start signal 114 is output one clock later than the address signal. Since the mask signal 210 is generated based on the address signal 107, the output of the bus cycle start signal 214 can be completely inhibited.

 FIG. 4 is a block diagram of a second embodiment of the present invention.

The bus cycle start signal generator 103a includes a cycle start signal generation circuit 104, a signal switching circuit 105, and a shift register 11.
It is composed of 7.

When it becomes necessary to access the bus inside the microcomputer 202a, the cycle request signal 110 becomes active, and the timing signal generator 102 starts operating in synchronization with the timing clock signal 109.

Trigger signal 1 output from timing signal generator 102
11 is also input to the shift register 117 at the same time as being input to the signal switching circuit 105 in the bus cycle start signal generator 103a.

The shift register 117 delays the trigger signal 111 from the timing clock signal 109 for a fixed time, generates a delayed trigger signal 116, and outputs the signal to the signal switching circuit 105.

The signal switching circuit 105 outputs one of the trigger signal 111 and the delay trigger signal 116 as a trigger signal of the cycle start signal generation circuit 104 according to the setting of the timing switching input signal 113 input from outside the microcomputer 202a.

The cycle start signal generating circuit 104 outputs a bus cycle start signal 112 to the outside of the microcomputer 202a in response to the trigger signal 111.

 Therefore, the same effect as in the first embodiment can be obtained.

〔The invention's effect〕

As is apparent from the above description, according to the microcomputer of the present invention, the output timing of the signal indicating the start of the bus cycle can be delayed from the output timing of the address signal.
An effect of controlling permission or prohibition of outputting a signal indicating the start of a cycle to the outside of the development support device can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a bus signal control unit of a microcomputer according to a first embodiment of the present invention, FIG. 2 is a block diagram of an example of a development support device using the microcomputer of FIG. 1, and FIG. FIG. 4 is a timing chart of each signal for explaining the operation of the block in FIG. 2, FIG. 4 is a block diagram of a bus signal control unit of the microcomputer according to the second embodiment of the present invention, and FIG. FIG. 6 is a block diagram of a development support device using the microcomputer of FIG. 5, and FIG. 7 is a block diagram of each signal for explaining the operation of the block of FIG. It is a timing chart. 101: address latch 102: timing signal generator 103, 103a: bus cycle start signal generation circuit 10,
4 Cycle start signal generation circuit 105 105 Signal switching circuit 106 Internal address signal 107 Address signal
108: Address latch signal, 109: Timing clock signal, 110: Cycle request signal, 111: Trigger signal, 112: Bus cycle start signal, 113: Timing switching input signal, 114: Internal Cycle start signal, 115
…… Internal cycle start delay signal, 116 …… Delay trigger signal, 117… Shift register, 201 …… Development support device, 20
2,202a: microcomputer, 203: address
Buffer 204 mask circuit 205 address monitoring circuit 206 memory circuit 207 prototype system 210 cycle start signal output inhibit signal 211 switching signal generator 212 timing Switching input signal, 213 ...
... Memory selection signal, 214... Bus cycle start signal.

Claims (1)

(57) [Claims] At the start of a bus cycle for outputting an address signal to an address bus and accessing data, this bus
Bus cycle start signal generating means for externally outputting a bus cycle start signal indicating the start of a cycle in synchronization with the output timing of the address signal, wherein the bus cycle start signal is masked in accordance with the address signal Wherein the bus cycle start signal generating means outputs an internal cycle start signal indicating the start of the bus cycle and a delay signal thereof in synchronization with the output timing. A cycle start signal generating circuit that performs switching to select either the internal cycle start signal or the delay signal according to whether or not to access the data of the external access destination, and externally outputs the signal as the bus cycle start signal And a circuit comprising: