JPH03282667A - Computer device - Google Patents

Computer device

Info

Publication number
JPH03282667A
JPH03282667A JP2082767A JP8276790A JPH03282667A JP H03282667 A JPH03282667 A JP H03282667A JP 2082767 A JP2082767 A JP 2082767A JP 8276790 A JP8276790 A JP 8276790A JP H03282667 A JPH03282667 A JP H03282667A
Authority
JP
Japan
Prior art keywords
cpu
data
memory
instruction
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2082767A
Other languages
Japanese (ja)
Inventor
Hiroyuki Suzuki
Kazuhide Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2082767A priority Critical patent/JPH03282667A/en
Publication of JPH03282667A publication Critical patent/JPH03282667A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

PURPOSE: To evade the extension of an integrated circuit and to prevent the large power consumption by transferring the data between a data memory and a peripheral device in a period when a CPU has no access to the data memory during one instruction of the CPU and via an exclusive data bus not via a data bus.
CONSTITUTION: A CPU 1 receives an instruction from an instruction memory 7 via a bus 6 and has an access to a data memory 2 or a peripheral device 3 via a data bus 4 in response to the instruction. Then the data are transferred between the device 3 and the memory 2 via an exclusive data bus 5 in a period when the CPU 1 has no access to the memory 2 during one instruction of the CPU 1. Thus it is possible to transfer a large quantity of data to the device 3 from the memory 2 without deteriorating the executing speed of the CPU 1 nor the processing speed of the device 3. Then the CPU 1 is never expanded and the large power consumption can be prevented.
COPYRIGHT: (C)1991,JPO&Japio
JP2082767A 1990-03-29 1990-03-29 Computer device Pending JPH03282667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2082767A JPH03282667A (en) 1990-03-29 1990-03-29 Computer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2082767A JPH03282667A (en) 1990-03-29 1990-03-29 Computer device

Publications (1)

Publication Number Publication Date
JPH03282667A true JPH03282667A (en) 1991-12-12

Family

ID=13783589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2082767A Pending JPH03282667A (en) 1990-03-29 1990-03-29 Computer device

Country Status (1)

Country Link
JP (1) JPH03282667A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100343461B1 (en) * 1999-12-06 2002-07-11 박종섭 Low power bus apparatus
WO2004073252A1 (en) * 2003-02-14 2004-08-26 Sony Corporation Authentication processing device and security processing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5884333A (en) * 1981-11-13 1983-05-20 Ricoh Co Ltd Memory controlling system
JPS62231367A (en) * 1986-04-01 1987-10-09 Meidensha Electric Mfg Co Ltd Dma data transfer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5884333A (en) * 1981-11-13 1983-05-20 Ricoh Co Ltd Memory controlling system
JPS62231367A (en) * 1986-04-01 1987-10-09 Meidensha Electric Mfg Co Ltd Dma data transfer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100343461B1 (en) * 1999-12-06 2002-07-11 박종섭 Low power bus apparatus
WO2004073252A1 (en) * 2003-02-14 2004-08-26 Sony Corporation Authentication processing device and security processing method
US7739506B2 (en) 2003-02-14 2010-06-15 Sony Corporation Authentication processing device and security processing method

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